crypto/mlx5: fix size of UMR WQE

The size of the UMR WQE allocated object is decided by a sizof
operation on the struct, however since the struct contains
a union of flexible array members this sizeof results can differ
between compilers.

GCC for example treats the union as 0 sized, MSVC adds a padding
of 16Bits.

To resolve the ambiguity the allocation size will be calculated
by the sizes of the members excluding the flexible union.

Fixes: a1978aa23bf4 ("crypto/mlx5: add maximum segments configuration")
Cc: stable@dpdk.org
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c
index 6bebc83c39276fc28e7e0c7dfda7fb32e00ffa26..07c2a9c68b5e163f44d219d3d5f7adcbd965e78c 100644 (file)
--- a/drivers/crypto/mlx5/mlx5_crypto.c
+++ b/drivers/crypto/mlx5/mlx5_crypto.c
@@ -909,7 +909,9 @@ mlx5_crypto_dev_probe(struct mlx5_common_device *cdev)
        priv->keytag = rte_cpu_to_be_64(devarg_prms.keytag);
        priv->max_segs_num = devarg_prms.max_segs_num;
        priv->umr_wqe_size = sizeof(struct mlx5_wqe_umr_bsf_seg) +
-                            sizeof(struct mlx5_umr_wqe) +
+                            sizeof(struct mlx5_wqe_cseg) +
+                            sizeof(struct mlx5_wqe_umr_cseg) +
+                            sizeof(struct mlx5_wqe_mkey_cseg) +
                             RTE_ALIGN(priv->max_segs_num, 4) *
                             sizeof(struct mlx5_wqe_dseg);
        rdmw_wqe_size = sizeof(struct mlx5_rdma_write_wqe) +