FM10K_TPH_RXCTRL_HDR_WROEN);
        }
 
-       /* set max hold interval to align with 1.024 usec in all modes */
+       /* set max hold interval to align with 1.024 usec in all modes and
+        * store ITR scale
+        */
        switch (hw->bus.speed) {
        case fm10k_bus_speed_2500:
                dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1;
+               hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN1;
                break;
        case fm10k_bus_speed_5000:
                dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2;
+               hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN2;
                break;
        case fm10k_bus_speed_8000:
                dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3;
+               hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN3;
                break;
        default:
                dma_ctrl = 0;
+               /* just in case, assume Gen3 ITR scale */
+               hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN3;
                break;
        }
 
        FM10K_WRITE_REG(hw, FM10K_TDBAL(vf_q_idx), tdbal);
        FM10K_WRITE_REG(hw, FM10K_TDBAH(vf_q_idx), tdbah);
 
+       /* Provide the VF the ITR scale, using software-defined fields in TDLEN
+        * to pass the information during VF initialization
+        */
+       FM10K_WRITE_REG(hw, FM10K_TDLEN(vf_q_idx), hw->mac.itr_scale <<
+                                                  FM10K_TDLEN_ITR_SCALE_SHIFT);
+
 err_out:
        /* configure Queue control register */
        txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) &
        for (i = queues_per_pool; i--;) {
                FM10K_WRITE_REG(hw, FM10K_TDBAL(vf_q_idx + i), tdbal);
                FM10K_WRITE_REG(hw, FM10K_TDBAH(vf_q_idx + i), tdbah);
+               FM10K_WRITE_REG(hw, FM10K_TDLEN(vf_q_idx + i),
+                               hw->mac.itr_scale <<
+                               FM10K_TDLEN_ITR_SCALE_SHIFT);
                FM10K_WRITE_REG(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx + i);
                FM10K_WRITE_REG(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx + i);
        }
 
 #define FM10K_TDBAL(_n)                ((0x40 * (_n)) + 0x8000)
 #define FM10K_TDBAH(_n)                ((0x40 * (_n)) + 0x8001)
 #define FM10K_TDLEN(_n)                ((0x40 * (_n)) + 0x8002)
+#define FM10K_TDLEN_ITR_SCALE_SHIFT            9
+#define FM10K_TDLEN_ITR_SCALE_MASK             0x00000E00
+#define FM10K_TDLEN_ITR_SCALE_GEN1             4
+#define FM10K_TDLEN_ITR_SCALE_GEN2             2
+#define FM10K_TDLEN_ITR_SCALE_GEN3             1
 #define FM10K_TPH_TXCTRL(_n)   ((0x40 * (_n)) + 0x8003)
 #define FM10K_TPH_TXCTRL_DESC_TPHEN            0x00000020
 #define FM10K_TPH_TXCTRL_DESC_RROEN            0x00000200
        bool get_host_state;
        bool tx_ready;
        u32 dglort_map;
+       u8 itr_scale;
 };
 
 struct fm10k_swapi_table_info {
 
 STATIC s32 fm10k_stop_hw_vf(struct fm10k_hw *hw)
 {
        u8 *perm_addr = hw->mac.perm_addr;
-       u32 bal = 0, bah = 0;
+       u32 bal = 0, bah = 0, tdlen;
        s32 err;
        u16 i;
 
                       ((u32)perm_addr[2]);
        }
 
+       /* restore default itr_scale for next VF initialization */
+       tdlen = hw->mac.itr_scale << FM10K_TDLEN_ITR_SCALE_SHIFT;
+
        /* The queues have already been disabled so we just need to
         * update their base address registers
         */
                FM10K_WRITE_REG(hw, FM10K_TDBAH(i), bah);
                FM10K_WRITE_REG(hw, FM10K_RDBAL(i), bal);
                FM10K_WRITE_REG(hw, FM10K_RDBAH(i), bah);
+               FM10K_WRITE_REG(hw, FM10K_TDLEN(i), tdlen);
        }
 
        return FM10K_SUCCESS;
        /* record maximum queue count */
        hw->mac.max_queues = i;
 
-       /* fetch default VLAN */
+       /* fetch default VLAN and ITR scale */
        hw->mac.default_vid = (FM10K_READ_REG(hw, FM10K_TXQCTL(0)) &
                               FM10K_TXQCTL_VID_MASK) >> FM10K_TXQCTL_VID_SHIFT;
+       hw->mac.itr_scale = (FM10K_READ_REG(hw, FM10K_TDLEN(0)) &
+                            FM10K_TDLEN_ITR_SCALE_MASK) >>
+                           FM10K_TDLEN_ITR_SCALE_SHIFT;
+
+       /* ensure a non-zero itr scale */
+       if (!hw->mac.itr_scale)
+               hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN3;
 
        return FM10K_SUCCESS;
 }