crypto/qat: add 3DES cipher algorithm

3DES support added to QuickAssist PMD with CTR and CBC mode.
Both cipher-only and chained with HMAC_SHAx.

Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>

diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 558c1f4..70bc2b1 100644 (file)
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -42,6 +42,8 @@ The QAT PMD has support for:
 
 Cipher algorithms:
 
+* ``RTE_CRYPTO_CIPHER_3DES_CBC``
+* ``RTE_CRYPTO_CIPHER_3DES_CTR``
 * ``RTE_CRYPTO_CIPHER_AES128_CBC``
 * ``RTE_CRYPTO_CIPHER_AES192_CBC``
 * ``RTE_CRYPTO_CIPHER_AES256_CBC``
@@ -73,7 +75,7 @@ Limitations
 
 * Chained mbufs are not supported.
 * Hash only is not supported except SNOW 3G UIA2 and KASUMI F9.
-* Cipher only is not supported except SNOW 3G UEA2 and KASUMI F8.
+* Cipher only is not supported except SNOW 3G UEA2, KASUMI F8 and 3DES.
 * Only supports the session-oriented API implementation (session-less APIs are not supported).
 * Not performance tuned.
 * SNOW 3G (UEA2) and KASUMI (F8) supported only if cipher length, cipher offset fields are byte-aligned.

diff --git a/doc/guides/rel_notes/release_16_11.rst b/doc/guides/rel_notes/release_16_11.rst
index 6114b26..d17f1e3 100644 (file)
--- a/doc/guides/rel_notes/release_16_11.rst
+++ b/doc/guides/rel_notes/release_16_11.rst
@@ -73,6 +73,7 @@ New Features
   * SHA384-HMAC algorithm
   * GMAC algorithm
   * KASUMI (F8 and F9) algorithm
+  * 3DES algorithm
   * NULL algorithm
   * C3XXX device
   * C62XX device

diff --git a/drivers/crypto/qat/qat_adf/qat_algs.h b/drivers/crypto/qat/qat_adf/qat_algs.h
index 057219b..78a92f3 100644 (file)
--- a/drivers/crypto/qat/qat_adf/qat_algs.h
+++ b/drivers/crypto/qat/qat_adf/qat_algs.h
@@ -59,6 +59,10 @@
 
 #define KASUMI_F8_KEY_MODIFIER_4_BYTES   0x55555555
 
+/* 3DES key sizes */
+#define QAT_3DES_KEY_SZ_OPT1 24 /* Keys are independent */
+#define QAT_3DES_KEY_SZ_OPT2 16 /* K3=K1 */
+
 #define QAT_AES_HW_CONFIG_CBC_ENC(alg) \
        ICP_QAT_HW_CIPHER_CONFIG_BUILD(ICP_QAT_HW_CIPHER_CBC_MODE, alg, \
                                        ICP_QAT_HW_CIPHER_NO_CONVERT, \
@@ -138,4 +142,5 @@ void qat_alg_ablkcipher_init_dec(struct qat_alg_ablkcipher_cd *cd,
 int qat_alg_validate_aes_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
 int qat_alg_validate_snow3g_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
 int qat_alg_validate_kasumi_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
+int qat_alg_validate_3des_key(int key_len, enum icp_qat_hw_cipher_algo *alg);
 #endif

diff --git a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
index 90af1b8..0b66b37 100644 (file)
--- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
+++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c
@@ -512,6 +512,10 @@ int qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cdesc,
                cipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_KASUMI_BLK_SZ >> 3;
                cipher_cd_ctrl->cipher_padding_sz =
                                        (2 * ICP_QAT_HW_KASUMI_BLK_SZ) >> 3;
+       } else if (cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_3DES) {
+               total_key_size = ICP_QAT_HW_3DES_KEY_SZ;
+               cipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_3DES_BLK_SZ >> 3;
+               proto = ICP_QAT_FW_LA_PROTO_GET(header->serv_specif_flags);
        } else {
                total_key_size = cipherkeylen;
                cipher_cd_ctrl->cipher_state_sz = ICP_QAT_HW_AES_BLK_SZ >> 3;
@@ -553,8 +557,12 @@ int qat_alg_aead_session_create_content_desc_cipher(struct qat_session *cdesc,
 
        if (total_key_size > cipherkeylen) {
                uint32_t padding_size =  total_key_size-cipherkeylen;
-
-               memset(cdesc->cd_cur_ptr, 0, padding_size);
+               if ((cdesc->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_3DES)
+                       && (cipherkeylen == QAT_3DES_KEY_SZ_OPT2))
+                       /* K3 not provided so use K1 = K3*/
+                       memcpy(cdesc->cd_cur_ptr, cipherkey, padding_size);
+               else
+                       memset(cdesc->cd_cur_ptr, 0, padding_size);
                cdesc->cd_cur_ptr += padding_size;
        }
        cd_size = cdesc->cd_cur_ptr-(uint8_t *)&cdesc->cd;
@@ -845,3 +853,16 @@ int qat_alg_validate_kasumi_key(int key_len, enum icp_qat_hw_cipher_algo *alg)
        }
        return 0;
 }
+
+int qat_alg_validate_3des_key(int key_len, enum icp_qat_hw_cipher_algo *alg)
+{
+       switch (key_len) {
+       case QAT_3DES_KEY_SZ_OPT1:
+       case QAT_3DES_KEY_SZ_OPT2:
+               *alg = ICP_QAT_HW_CIPHER_ALGO_3DES;
+               break;
+       default:
+               return -EINVAL;
+       }
+       return 0;
+}

diff --git a/drivers/crypto/qat/qat_crypto.c b/drivers/crypto/qat/qat_crypto.c
index 3e5c61e..f8db12f 100644 (file)
--- a/drivers/crypto/qat/qat_crypto.c
+++ b/drivers/crypto/qat/qat_crypto.c
@@ -456,6 +456,46 @@ static const struct rte_cryptodev_capabilities qat_pmd_capabilities[] = {
                        }, }
                }, }
        },
+       {       /* 3DES CBC */
+               .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+               {.sym = {
+                       .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+                       {.cipher = {
+                               .algo = RTE_CRYPTO_CIPHER_3DES_CBC,
+                               .block_size = 8,
+                               .key_size = {
+                                       .min = 16,
+                                       .max = 24,
+                                       .increment = 8
+                               },
+                               .iv_size = {
+                                       .min = 8,
+                                       .max = 8,
+                                       .increment = 0
+                               }
+                       }, }
+               }, }
+       },
+       {       /* 3DES CTR */
+               .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+               {.sym = {
+                       .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
+                       {.cipher = {
+                               .algo = RTE_CRYPTO_CIPHER_3DES_CTR,
+                               .block_size = 8,
+                               .key_size = {
+                                       .min = 16,
+                                       .max = 24,
+                                       .increment = 8
+                               },
+                               .iv_size = {
+                                       .min = 8,
+                                       .max = 8,
+                                       .increment = 0
+                               }
+                       }, }
+               }, }
+       },
        RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
 };
 
@@ -589,8 +629,23 @@ qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
                }
                session->qat_mode = ICP_QAT_HW_CIPHER_F8_MODE;
                break;
-       case RTE_CRYPTO_CIPHER_3DES_ECB:
        case RTE_CRYPTO_CIPHER_3DES_CBC:
+               if (qat_alg_validate_3des_key(cipher_xform->key.length,
+                               &session->qat_cipher_alg) != 0) {
+                       PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
+                       goto error_out;
+               }
+               session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
+               break;
+       case RTE_CRYPTO_CIPHER_3DES_CTR:
+               if (qat_alg_validate_3des_key(cipher_xform->key.length,
+                               &session->qat_cipher_alg) != 0) {
+                       PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
+                       goto error_out;
+               }
+               session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
+               break;
+       case RTE_CRYPTO_CIPHER_3DES_ECB:
        case RTE_CRYPTO_CIPHER_AES_ECB:
        case RTE_CRYPTO_CIPHER_AES_CCM:
        case RTE_CRYPTO_CIPHER_AES_F8: