type);
}
}
+
+void
+qede_hw_err_notify(struct ecore_hwfn *p_hwfn, enum ecore_hw_err_type err_type)
+{
+ char err_str[64];
+
+ switch (err_type) {
+ case ECORE_HW_ERR_FAN_FAIL:
+ strcpy(err_str, "Fan Failure");
+ break;
+ case ECORE_HW_ERR_MFW_RESP_FAIL:
+ strcpy(err_str, "MFW Response Failure");
+ break;
+ case ECORE_HW_ERR_HW_ATTN:
+ strcpy(err_str, "HW Attention");
+ break;
+ case ECORE_HW_ERR_DMAE_FAIL:
+ strcpy(err_str, "DMAE Failure");
+ break;
+ case ECORE_HW_ERR_RAMROD_FAIL:
+ strcpy(err_str, "Ramrod Failure");
+ break;
+ case ECORE_HW_ERR_FW_ASSERT:
+ strcpy(err_str, "FW Assertion");
+ break;
+ default:
+ strcpy(err_str, "Unknown");
+ }
+
+ DP_ERR(p_hwfn, "HW error occurred [%s]\n", err_str);
+ ecore_int_attn_clr_enable(p_hwfn->p_dev, true);
+}
struct vf_pf_resc_request;
enum ecore_mcp_protocol_type;
union ecore_mcp_protocol_stats;
+enum ecore_hw_err_type;
void qed_link_update(struct ecore_hwfn *hwfn);
u8 *input_buf, u32 max_size, u8 *unzip_buf);
void qede_vf_fill_driver_data(struct ecore_hwfn *, struct vf_pf_resc_request *,
struct ecore_vf_acquire_sw_info *);
+void qede_hw_err_notify(struct ecore_hwfn *p_hwfn,
+ enum ecore_hw_err_type err_type);
#define OSAL_VF_FILL_ACQUIRE_RESC_REQ(_dev_p, _resc_req, _os_info) \
qede_vf_fill_driver_data(_dev_p, _resc_req, _os_info)
/* TODO: */
#define OSAL_SCHEDULE_RECOVERY_HANDLER(hwfn) nothing
-#define OSAL_HW_ERROR_OCCURRED(hwfn, err_type) nothing
+#define OSAL_HW_ERROR_OCCURRED(hwfn, err_type) \
+ qede_hw_err_notify(hwfn, err_type)
#define OSAL_NVM_IS_ACCESS_ENABLED(hwfn) (1)
#define OSAL_NUM_ACTIVE_CPU() 0
u32 mask = ~bitmask;
val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
ecore_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & mask));
- DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n",
+ DP_ERR(p_hwfn, "`%s' - Disabled future attentions\n",
p_bit_name);
}