]> git.droids-corp.org - dpdk.git/commitdiff
net/mlx5: share realtime timestamp configure
authorMichael Baum <michaelba@nvidia.com>
Mon, 14 Feb 2022 09:35:02 +0000 (11:35 +0200)
committerRaslan Darawsheh <rasland@nvidia.com>
Mon, 21 Feb 2022 10:36:47 +0000 (11:36 +0100)
The realtime timestamp configure work for Linux as same as Windows.
This patch removes it to the function implemented in the folder shared
between the operating systems, removing the duplication.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
drivers/net/mlx5/linux/mlx5_os.c
drivers/net/mlx5/mlx5.c
drivers/net/mlx5/mlx5.h
drivers/net/mlx5/windows/mlx5_os.c

index d1bf89922ed480c17d43b034f14b407bbc28ad18..bee055772ba9b2e4286ad5f7d31c714ba7c644cd 100644 (file)
@@ -1516,27 +1516,8 @@ err_secondary:
                                priv->dev_port);
                }
        }
-       if (sh->cdev->config.devx) {
-               uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];
-
-               err = hca_attr->access_register_user ?
-                       mlx5_devx_cmd_register_read
-                               (sh->cdev->ctx, MLX5_REGISTER_ID_MTUTC, 0,
-                               reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP;
-               if (!err) {
-                       uint32_t ts_mode;
-
-                       /* MTUTC register is read successfully. */
-                       ts_mode = MLX5_GET(register_mtutc, reg,
-                                          time_stamp_mode);
-                       if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME)
-                               config->rt_timestamp = 1;
-               } else {
-                       /* Kernel does not support register reading. */
-                       if (hca_attr->dev_freq_khz == (NS_PER_S / MS_PER_S))
-                               config->rt_timestamp = 1;
-               }
-       }
+       if (sh->cdev->config.devx)
+               mlx5_rt_timestamp_config(sh, config, hca_attr);
        /*
         * If HW has bug working with tunnel packet decapsulation and
         * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip
index 34b3f3f1373fe3e4e45e8aa3150c3ff8c7c0579e..48841985098c79c8822c7e1d3f95cfe58aac4bde 100644 (file)
@@ -1129,6 +1129,43 @@ mlx5_setup_tis(struct mlx5_dev_ctx_shared *sh)
        return 0;
 }
 
+/**
+ * Configure realtime timestamp format.
+ *
+ * @param sh
+ *   Pointer to mlx5_dev_ctx_shared object.
+ * @param config
+ *   Device configuration parameters.
+ * @param hca_attr
+ *   Pointer to DevX HCA capabilities structure.
+ */
+void
+mlx5_rt_timestamp_config(struct mlx5_dev_ctx_shared *sh,
+                        struct mlx5_dev_config *config,
+                        struct mlx5_hca_attr *hca_attr)
+{
+       uint32_t dw_cnt = MLX5_ST_SZ_DW(register_mtutc);
+       uint32_t reg[dw_cnt];
+       int ret = ENOTSUP;
+
+       if (hca_attr->access_register_user)
+               ret = mlx5_devx_cmd_register_read(sh->cdev->ctx,
+                                                 MLX5_REGISTER_ID_MTUTC, 0,
+                                                 reg, dw_cnt);
+       if (!ret) {
+               uint32_t ts_mode;
+
+               /* MTUTC register is read successfully. */
+               ts_mode = MLX5_GET(register_mtutc, reg, time_stamp_mode);
+               if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME)
+                       config->rt_timestamp = 1;
+       } else {
+               /* Kernel does not support register reading. */
+               if (hca_attr->dev_freq_khz == (NS_PER_S / MS_PER_S))
+                       config->rt_timestamp = 1;
+       }
+}
+
 /**
  * Allocate shared device context. If there is multiport device the
  * master and representors will share this context, if there is single
index 6bc7a34f60b7640533811207f1f68fe90773e7fe..0f90d757e95132cab4d662a63759e65f805048cf 100644 (file)
@@ -1517,6 +1517,9 @@ void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh);
             port_id < RTE_MAX_ETHPORTS; \
             port_id = mlx5_eth_find_next(port_id + 1, dev))
 int mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs);
+void mlx5_rt_timestamp_config(struct mlx5_dev_ctx_shared *sh,
+                             struct mlx5_dev_config *config,
+                             struct mlx5_hca_attr *hca_attr);
 struct mlx5_dev_ctx_shared *
 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
                           const struct mlx5_dev_config *config);
index cca99f3eea234efe6c018a6f81a393caacd55505..cf0819e013befbdb441fc3db1eaf9fd76a02533c 100644 (file)
@@ -483,27 +483,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
                DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
                        (config->hw_vlan_strip ? "" : "not "));
                config->hw_fcs_strip = hca_attr->scatter_fcs;
-       }
-       if (sh->devx) {
-               uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];
-
-               err = hca_attr->access_register_user ?
-                       mlx5_devx_cmd_register_read
-                               (sh->cdev->ctx, MLX5_REGISTER_ID_MTUTC, 0,
-                               reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP;
-               if (!err) {
-                       uint32_t ts_mode;
-
-                       /* MTUTC register is read successfully. */
-                       ts_mode = MLX5_GET(register_mtutc, reg,
-                                          time_stamp_mode);
-                       if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME)
-                               config->rt_timestamp = 1;
-               } else {
-                       /* Kernel does not support register reading. */
-                       if (hca_attr->dev_freq_khz == (NS_PER_S / MS_PER_S))
-                               config->rt_timestamp = 1;
-               }
+               mlx5_rt_timestamp_config(sh, config, hca_attr);
        }
        if (config->mprq.enabled) {
                DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");