dev_tx_offloads_nodis;
dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
+ dev_info->default_rxportconf.nb_queues = 1;
+ dev_info->default_txportconf.nb_queues = 1;
+ dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH;
+ dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH;
return 0;
}
/* RX queue tail drop threshold (CGR Based) in frame count */
#define CGR_RX_PERFQ_THRESH 256
+#define CGR_TX_CGR_THRESH 512
/*max mac filter for memac(8) including primary mac addr*/
#define DPAA_MAX_MAC_FILTER (MEMAC_NUM_OF_PADDRS + 1)
dev_info->max_vmdq_pools = ETH_16_POOLS;
dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
+ dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size;
+ /* same is rx size for best perf */
+ dev_info->default_txportconf.burst_size = dpaa2_dqrr_size;
+
+ dev_info->default_rxportconf.nb_queues = 1;
+ dev_info->default_txportconf.nb_queues = 1;
+ dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
+ dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
+
return 0;
}
#define MAX_TX_QUEUES 16
#define MAX_DPNI 8
+#define DPAA2_RX_DEFAULT_NBDESC 512
+
/*default tc to be used for ,congestion, distribution etc configuration. */
#define DPAA2_DEF_TC 0