crypto/qat: support GMAC in GEN4 legacy mode

Add AES-GMAC algorithm in legacy mode to generation 4 devices.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>

diff --git a/drivers/crypto/qat/qat_sym_capabilities.h b/drivers/crypto/qat/qat_sym_capabilities.h
index 5c6e723..cfb176c 100644 (file)
--- a/drivers/crypto/qat/qat_sym_capabilities.h
+++ b/drivers/crypto/qat/qat_sym_capabilities.h
@@ -1174,7 +1174,32 @@
                                },                                      \
                        }, }                                            \
                }, }                                                    \
-       }
+       },                                                              \
+       {       /* AES GMAC (AUTH) */                                   \
+               .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,                     \
+               {.sym = {                                               \
+                       .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,        \
+                       {.auth = {                                      \
+                               .algo = RTE_CRYPTO_AUTH_AES_GMAC,       \
+                               .block_size = 16,                       \
+                               .key_size = {                           \
+                                       .min = 16,                      \
+                                       .max = 32,                      \
+                                       .increment = 8                  \
+                               },                                      \
+                               .digest_size = {                        \
+                                       .min = 8,                       \
+                                       .max = 16,                      \
+                                       .increment = 4                  \
+                               },                                      \
+                               .iv_size = {                            \
+                                       .min = 0,                       \
+                                       .max = 12,                      \
+                                       .increment = 12                 \
+                               }                                       \
+                       }, }                                            \
+               }, }                                                    \
+       }                                                               \
 
 
 

diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c
index 6b87fc0..3f2f673 100644 (file)
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -710,6 +710,8 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
        struct qat_sym_dev_private *internals = dev->data->dev_private;
        const uint8_t *key_data = auth_xform->key.data;
        uint8_t key_length = auth_xform->key.length;
+       enum qat_device_gen qat_dev_gen =
+                       internals->qat_dev->qat_dev_gen;
 
        session->aes_cmac = 0;
        session->auth_key_length = auth_xform->key.length;
@@ -717,6 +719,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
        session->auth_iv.length = auth_xform->iv.length;
        session->auth_mode = ICP_QAT_HW_AUTH_MODE1;
        session->is_auth = 1;
+       session->digest_length = auth_xform->digest_length;
 
        switch (auth_xform->algo) {
        case RTE_CRYPTO_AUTH_SHA1:
@@ -773,6 +776,10 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
                        session->auth_iv.length = AES_GCM_J0_LEN;
                else
                        session->is_iv12B = 1;
+               if (qat_dev_gen == QAT_GEN4) {
+                       session->is_cnt_zero = 1;
+                       session->is_ucs = 1;
+               }
                break;
        case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
                session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
@@ -858,7 +865,6 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,
                        return -EINVAL;
        }
 
-       session->digest_length = auth_xform->digest_length;
        return 0;
 }
 
@@ -1814,6 +1820,7 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc,
                || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC
                || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC
                || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL
+               || cdesc->is_cnt_zero
                        )
                hash->auth_counter.counter = 0;
        else {

diff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_sym_session.h
index 1568e09..33b236e 100644 (file)
--- a/drivers/crypto/qat/qat_sym_session.h
+++ b/drivers/crypto/qat/qat_sym_session.h
@@ -103,6 +103,8 @@ struct qat_sym_session {
        uint8_t is_iv12B;
        uint8_t is_gmac;
        uint8_t is_auth;
+       uint8_t is_cnt_zero;
+       /* Some generations need different setup of counter */
        uint32_t slice_types;
        enum qat_sym_proto_flag qat_proto_flag;
 };