ixgbe/base: allow access to PHY register without lock

Signed-off-by: Jijiang Liu <jijiang.liu@intel.com>
Acked-by: Helin Zhang <helin.zhang@intel.com>
Tested-by: Waterman Cao <waterman.cao@intel.com>
[Thomas: split code drop]

diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c
index fc5f7d7..13fa4da 100644 (file)
--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c
+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c
@@ -318,7 +318,7 @@ s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
 
        DEBUGFUNC("ixgbe_init_ops_82599");
 
-       ret_val = ixgbe_init_phy_ops_generic(hw);
+       ixgbe_init_phy_ops_generic(hw);
        ret_val = ixgbe_init_ops_generic(hw);
 
        /* PHY */

diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c
index 33d6551..382b0ed 100644 (file)
--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c
+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c
@@ -65,6 +65,8 @@ s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
        phy->ops.reset = &ixgbe_reset_phy_generic;
        phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
        phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
+       phy->ops.read_reg_mdi = &ixgbe_read_phy_reg_mdi;
+       phy->ops.write_reg_mdi = &ixgbe_write_phy_reg_mdi;
        phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
        phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
        phy->ops.check_link = NULL;
@@ -308,8 +310,88 @@ out:
        return status;
 }
 
+/**
+ *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
+ *  the SWFW lock
+ *  @hw: pointer to hardware structure
+ *  @reg_addr: 32 bit address of PHY register to read
+ *  @phy_data: Pointer to read data from PHY register
+ **/
+s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
+                      u16 *phy_data)
+{
+       u32 i, data, command;
+
+       /* Setup and write the address cycle command */
+       command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
+                  (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
+                  (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
+                  (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
+
+       IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
+
+       /*
+        * Check every 10 usec to see if the address cycle completed.
+        * The MDI Command bit will clear when the operation is
+        * complete
+        */
+       for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
+               usec_delay(10);
+
+               command = IXGBE_READ_REG(hw, IXGBE_MSCA);
+               if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
+                               break;
+       }
+
+
+       if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
+               ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
+               return IXGBE_ERR_PHY;
+       }
+
+       /*
+        * Address cycle complete, setup and write the read
+        * command
+        */
+       command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
+                  (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
+                  (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
+                  (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
+
+       IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
+
+       /*
+        * Check every 10 usec to see if the address cycle
+        * completed. The MDI Command bit will clear when the
+        * operation is complete
+        */
+       for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
+               usec_delay(10);
+
+               command = IXGBE_READ_REG(hw, IXGBE_MSCA);
+               if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
+                       break;
+       }
+
+       if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
+               ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
+               return IXGBE_ERR_PHY;
+       }
+
+       /*
+        * Read operation is complete.  Get the data
+        * from MSRWD
+        */
+       data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
+       data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
+       *phy_data = (u16)(data);
+
+       return IXGBE_SUCCESS;
+}
+
 /**
  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
+ *  using the SWFW lock - this function is needed in most cases
  *  @hw: pointer to hardware structure
  *  @reg_addr: 32 bit address of PHY register to read
  *  @phy_data: Pointer to read data from PHY register
@@ -317,10 +399,7 @@ out:
 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
                               u32 device_type, u16 *phy_data)
 {
-       u32 command;
-       u32 i;
-       u32 data;
-       s32 status = IXGBE_SUCCESS;
+       s32 status;
        u16 gssr;
 
        DEBUGFUNC("ixgbe_read_phy_reg_generic");
@@ -330,85 +409,94 @@ s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
        else
                gssr = IXGBE_GSSR_PHY0_SM;
 
-       if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
+       if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
+               status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
+                                               phy_data);
+               hw->mac.ops.release_swfw_sync(hw, gssr);
+       } else {
                status = IXGBE_ERR_SWFW_SYNC;
+       }
 
-       if (status == IXGBE_SUCCESS) {
-               /* Setup and write the address cycle command */
-               command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
-                          (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
-                          (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
-                          (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
+       return status;
+}
 
-               IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
+/**
+ *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
+ *  without SWFW lock
+ *  @hw: pointer to hardware structure
+ *  @reg_addr: 32 bit PHY register to write
+ *  @device_type: 5 bit device type
+ *  @phy_data: Data to write to the PHY register
+ **/
+s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
+                               u32 device_type, u16 phy_data)
+{
+       u32 i, command;
 
-               /*
-                * Check every 10 usec to see if the address cycle completed.
-                * The MDI Command bit will clear when the operation is
-                * complete
-                */
-               for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
-                       usec_delay(10);
+       /* Put the data in the MDI single read and write data register*/
+       IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 
-                       command = IXGBE_READ_REG(hw, IXGBE_MSCA);
+       /* Setup and write the address cycle command */
+       command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
+                  (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
+                  (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
+                  (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 
-                       if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
-                               break;
-               }
+       IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 
-               if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
-                       DEBUGOUT("PHY address command did not complete.\n");
-                       status = IXGBE_ERR_PHY;
-               }
+       /*
+        * Check every 10 usec to see if the address cycle completed.
+        * The MDI Command bit will clear when the operation is
+        * complete
+        */
+       for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
+               usec_delay(10);
 
-               if (status == IXGBE_SUCCESS) {
-                       /*
-                        * Address cycle complete, setup and write the read
-                        * command
-                        */
-                       command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
-                                  (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
-                                  (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
-                                  (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
-
-                       IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
-
-                       /*
-                        * Check every 10 usec to see if the address cycle
-                        * completed. The MDI Command bit will clear when the
-                        * operation is complete
-                        */
-                       for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
-                               usec_delay(10);
-
-                               command = IXGBE_READ_REG(hw, IXGBE_MSCA);
-
-                               if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
-                                       break;
-                       }
+               command = IXGBE_READ_REG(hw, IXGBE_MSCA);
+               if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
+                       break;
+       }
 
-                       if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
-                               DEBUGOUT("PHY read command didn't complete\n");
-                               status = IXGBE_ERR_PHY;
-                       } else {
-                               /*
-                                * Read operation is complete.  Get the data
-                                * from MSRWD
-                                */
-                               data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
-                               data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
-                               *phy_data = (u16)(data);
-                       }
-               }
+       if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
+               ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
+               return IXGBE_ERR_PHY;
+       }
 
-               hw->mac.ops.release_swfw_sync(hw, gssr);
+       /*
+        * Address cycle complete, setup and write the write
+        * command
+        */
+       command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
+                  (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
+                  (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
+                  (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
+
+       IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
+
+       /*
+        * Check every 10 usec to see if the address cycle
+        * completed. The MDI Command bit will clear when the
+        * operation is complete
+        */
+       for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
+               usec_delay(10);
+
+               command = IXGBE_READ_REG(hw, IXGBE_MSCA);
+               if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
+                       break;
        }
 
-       return status;
+       if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
+               ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
+               return IXGBE_ERR_PHY;
+       }
+
+       return IXGBE_SUCCESS;
 }
 
 /**
  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
+ *  using SWFW lock- this function is needed in most cases
  *  @hw: pointer to hardware structure
  *  @reg_addr: 32 bit PHY register to write
  *  @device_type: 5 bit device type
@@ -417,9 +505,7 @@ s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
                                u32 device_type, u16 phy_data)
 {
-       u32 command;
-       u32 i;
-       s32 status = IXGBE_SUCCESS;
+       s32 status;
        u16 gssr;
 
        DEBUGFUNC("ixgbe_write_phy_reg_generic");
@@ -429,73 +515,12 @@ s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
        else
                gssr = IXGBE_GSSR_PHY0_SM;
 
-       if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
-               status = IXGBE_ERR_SWFW_SYNC;
-
-       if (status == IXGBE_SUCCESS) {
-               /* Put the data in the MDI single read and write data register*/
-               IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
-
-               /* Setup and write the address cycle command */
-               command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
-                          (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
-                          (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
-                          (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
-
-               IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
-
-               /*
-                * Check every 10 usec to see if the address cycle completed.
-                * The MDI Command bit will clear when the operation is
-                * complete
-                */
-               for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
-                       usec_delay(10);
-
-                       command = IXGBE_READ_REG(hw, IXGBE_MSCA);
-
-                       if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
-                               break;
-               }
-
-               if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
-                       DEBUGOUT("PHY address cmd didn't complete\n");
-                       status = IXGBE_ERR_PHY;
-               }
-
-               if (status == IXGBE_SUCCESS) {
-                       /*
-                        * Address cycle complete, setup and write the write
-                        * command
-                        */
-                       command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
-                                  (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
-                                  (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
-                                  (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
-
-                       IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
-
-                       /*
-                        * Check every 10 usec to see if the address cycle
-                        * completed. The MDI Command bit will clear when the
-                        * operation is complete
-                        */
-                       for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
-                               usec_delay(10);
-
-                               command = IXGBE_READ_REG(hw, IXGBE_MSCA);
-
-                               if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
-                                       break;
-                       }
-
-                       if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
-                               DEBUGOUT("PHY address cmd didn't complete\n");
-                               status = IXGBE_ERR_PHY;
-                       }
-               }
-
+       if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
+               status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
+                                                phy_data);
                hw->mac.ops.release_swfw_sync(hw, gssr);
+       } else {
+               status = IXGBE_ERR_SWFW_SYNC;
        }
 
        return status;

diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.h
index dfcd2ba..67c02b4 100644 (file)
--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.h
+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.h
@@ -106,6 +106,10 @@ enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
+s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
+                          u16 *phy_data);
+s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
+                           u16 phy_data);
 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
                               u32 device_type, u16 *phy_data);
 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,

diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
index 11fa5c9..88be058 100644 (file)
--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
@@ -3107,6 +3107,8 @@ struct ixgbe_phy_operations {
        s32 (*reset)(struct ixgbe_hw *);
        s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
        s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
+       s32 (*read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *);
+       s32 (*write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16);
        s32 (*setup_link)(struct ixgbe_hw *);
        s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool);
        s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);