uint8_t tx_pkt_nb_segs = 1; /**< Number of segments in TXONLY packets */
uint16_t nb_pkt_per_burst = DEF_PKT_BURST; /**< Number of packets per burst. */
-uint16_t mb_mempool_cache = DEF_PKT_BURST; /**< Size of mbuf mempool cache. */
+uint16_t mb_mempool_cache = DEF_MBUF_CACHE; /**< Size of mbuf mempool cache. */
/* current configuration is in DCB or not,0 means it is not in DCB mode */
uint8_t dcb_config = 0;
*/
#define RX_PTHRESH 8 /**< Default value of RX prefetch threshold register. */
#define RX_HTHRESH 8 /**< Default value of RX host threshold register. */
-#define RX_WTHRESH 4 /**< Default value of RX write-back threshold register. */
+#define RX_WTHRESH 0 /**< Default value of RX write-back threshold register. */
-#define TX_PTHRESH 36 /**< Default value of TX prefetch threshold register. */
+#define TX_PTHRESH 32 /**< Default value of TX prefetch threshold register. */
#define TX_HTHRESH 0 /**< Default value of TX host threshold register. */
#define TX_WTHRESH 0 /**< Default value of TX write-back threshold register. */
#define MAX_PKT_BURST 512
#define DEF_PKT_BURST 32
+#define DEF_MBUF_CACHE 250
+
#define CACHE_LINE_SIZE_ROUNDUP(size) \
(CACHE_LINE_SIZE * ((size + CACHE_LINE_SIZE - 1) / CACHE_LINE_SIZE))