#include <rte_devargs.h>
#include <rte_memcpy.h>
#include <rte_ethdev_driver.h>
+#include <rte_mbuf_dyn.h>
#include <rte_fslmc.h>
#include <fslmc_vfio.h>
struct rte_fslmc_bus rte_fslmc_bus;
uint8_t dpaa2_virt_mode;
+#define DPAA2_SEQN_DYNFIELD_NAME "dpaa2_seqn_dynfield"
+int dpaa2_seqn_dynfield_offset = -1;
+
uint32_t
rte_fslmc_get_device_count(enum rte_dpaa2_dev_type device_type)
{
struct rte_dpaa2_device *dev;
struct rte_dpaa2_driver *drv;
+ static const struct rte_mbuf_dynfield dpaa2_seqn_dynfield_desc = {
+ .name = DPAA2_SEQN_DYNFIELD_NAME,
+ .size = sizeof(dpaa2_seqn_t),
+ .align = __alignof__(dpaa2_seqn_t),
+ };
+
if (TAILQ_EMPTY(&rte_fslmc_bus.device_list))
return 0;
+ dpaa2_seqn_dynfield_offset =
+ rte_mbuf_dynfield_register(&dpaa2_seqn_dynfield_desc);
+ if (dpaa2_seqn_dynfield_offset < 0) {
+ DPAA2_BUS_ERR("Failed to register mbuf field for dpaa sequence number");
+ return 0;
+ }
+
ret = fslmc_vfio_setup_group();
if (ret) {
DPAA2_BUS_ERR("Unable to setup VFIO %d", ret);
#include <rte_bus.h>
#include <rte_tailq.h>
#include <rte_devargs.h>
+#include <rte_mbuf.h>
+#include <rte_mbuf_dyn.h>
#include <fslmc_vfio.h>
#define FSLMC_OBJECT_MAX_LEN 32 /**< Length of each device on bus */
+#define DPAA2_INVALID_MBUF_SEQN 0
+
+typedef uint32_t dpaa2_seqn_t;
+extern int dpaa2_seqn_dynfield_offset;
+
+/**
+ * @warning
+ * @b EXPERIMENTAL: this API may change without prior notice
+ *
+ * Read dpaa2 sequence number from mbuf.
+ *
+ * @param mbuf Structure to read from.
+ * @return pointer to dpaa2 sequence number.
+ */
+__rte_experimental
+static inline dpaa2_seqn_t *
+dpaa2_seqn(struct rte_mbuf *mbuf)
+{
+ return RTE_MBUF_DYNFIELD(mbuf, dpaa2_seqn_dynfield_offset,
+ dpaa2_seqn_t *);
+}
/** Device driver supports link state interrupt */
#define RTE_DPAA2_DRV_INTR_LSC 0x0008
dpaa2_free_eq_descriptors;
dpaa2_get_mcp_ptr;
dpaa2_io_portal;
+ dpaa2_seqn_dynfield_offset;
dpaa2_svr_family;
dpaa2_virt_mode;
dpbp_disable;
dpaa2_eqcr_size : nb_ops;
for (loop = 0; loop < frames_to_send; loop++) {
- if ((*ops)->sym->m_src->seqn) {
- uint8_t dqrr_index = (*ops)->sym->m_src->seqn - 1;
-
- flags[loop] = QBMAN_ENQUEUE_FLAG_DCA | dqrr_index;
- DPAA2_PER_LCORE_DQRR_SIZE--;
- DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dqrr_index);
- (*ops)->sym->m_src->seqn = DPAA2_INVALID_MBUF_SEQN;
+ if (*dpaa2_seqn((*ops)->sym->m_src)) {
+ uint8_t dqrr_index =
+ *dpaa2_seqn((*ops)->sym->m_src) - 1;
+
+ flags[loop] = QBMAN_ENQUEUE_FLAG_DCA | dqrr_index;
+ DPAA2_PER_LCORE_DQRR_SIZE--;
+ DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dqrr_index);
+ *dpaa2_seqn((*ops)->sym->m_src) =
+ DPAA2_INVALID_MBUF_SEQN;
}
/*Clear the unused FD fields before sending*/
ev->event_ptr = sec_fd_to_mbuf(fd);
dqrr_index = qbman_get_dqrr_idx(dq);
- crypto_op->sym->m_src->seqn = dqrr_index + 1;
+ *dpaa2_seqn(crypto_op->sym->m_src) = dqrr_index + 1;
DPAA2_PER_LCORE_DQRR_SIZE++;
DPAA2_PER_LCORE_DQRR_HELD |= 1 << dqrr_index;
DPAA2_PER_LCORE_DQRR_MBUF(dqrr_index) = crypto_op->sym->m_src;
qbman_eq_desc_set_response(&eqdesc[loop], 0, 0);
if (event->sched_type == RTE_SCHED_TYPE_ATOMIC
- && event->mbuf->seqn) {
- uint8_t dqrr_index = event->mbuf->seqn - 1;
+ && *dpaa2_seqn(event->mbuf)) {
+ uint8_t dqrr_index =
+ *dpaa2_seqn(event->mbuf) - 1;
qbman_eq_desc_set_dca(&eqdesc[loop], 1,
dqrr_index, 0);
rte_memcpy(ev, ev_temp, sizeof(struct rte_event));
rte_free(ev_temp);
- ev->mbuf->seqn = dqrr_index + 1;
+ *dpaa2_seqn(ev->mbuf) = dqrr_index + 1;
DPAA2_PER_LCORE_DQRR_SIZE++;
DPAA2_PER_LCORE_DQRR_HELD |= 1 << dqrr_index;
DPAA2_PER_LCORE_DQRR_MBUF(dqrr_index) = ev->mbuf;
if (DPAA2_PER_LCORE_DQRR_HELD & (1 << i)) {
qbman_swp_dqrr_idx_consume(swp, i);
DPAA2_PER_LCORE_DQRR_SIZE--;
- DPAA2_PER_LCORE_DQRR_MBUF(i)->seqn =
+ *dpaa2_seqn(DPAA2_PER_LCORE_DQRR_MBUF(i)) =
DPAA2_INVALID_MBUF_SEQN;
}
i++;
#include <rte_random.h>
#include <rte_bus_vdev.h>
#include <rte_test.h>
+#include <rte_fslmc.h>
#include "dpaa2_eventdev.h"
#include "dpaa2_eventdev_logs.h"
valid_event = rte_event_dequeue_burst(evdev, port, &ev, 1, 0);
RTE_TEST_ASSERT_SUCCESS(valid_event,
- "Unexpected valid event=%d", ev.mbuf->seqn);
+ "Unexpected valid event=%d",
+ *dpaa2_seqn(ev.mbuf));
}
return 0;
}
#define DPAA2_MAX_BUF_POOLS 8
-#define DPAA2_INVALID_MBUF_SEQN 0
-
struct buf_pool_cfg {
void *addr;
/**< The address from where DPAA2 will carve out the buffers */
ev->mbuf = eth_fd_to_mbuf(fd, rxq->eth_data->port_id);
dqrr_index = qbman_get_dqrr_idx(dq);
- ev->mbuf->seqn = dqrr_index + 1;
+ *dpaa2_seqn(ev->mbuf) = dqrr_index + 1;
DPAA2_PER_LCORE_DQRR_SIZE++;
DPAA2_PER_LCORE_DQRR_HELD |= 1 << dqrr_index;
DPAA2_PER_LCORE_DQRR_MBUF(dqrr_index) = ev->mbuf;
ev->mbuf = eth_fd_to_mbuf(fd, rxq->eth_data->port_id);
- ev->mbuf->seqn = DPAA2_ENQUEUE_FLAG_ORP;
- ev->mbuf->seqn |= qbman_result_DQ_odpid(dq) << DPAA2_EQCR_OPRID_SHIFT;
- ev->mbuf->seqn |= qbman_result_DQ_seqnum(dq) << DPAA2_EQCR_SEQNUM_SHIFT;
+ *dpaa2_seqn(ev->mbuf) = DPAA2_ENQUEUE_FLAG_ORP;
+ *dpaa2_seqn(ev->mbuf) |= qbman_result_DQ_odpid(dq) << DPAA2_EQCR_OPRID_SHIFT;
+ *dpaa2_seqn(ev->mbuf) |= qbman_result_DQ_seqnum(dq) << DPAA2_EQCR_SEQNUM_SHIFT;
qbman_swp_dqrr_consume(swp, dq);
}
dpaa2_eqcr_size : nb_pkts;
for (loop = 0; loop < frames_to_send; loop++) {
- if ((*bufs)->seqn) {
- uint8_t dqrr_index = (*bufs)->seqn - 1;
+ if (*dpaa2_seqn(*bufs)) {
+ uint8_t dqrr_index = *dpaa2_seqn(*bufs) - 1;
flags[loop] = QBMAN_ENQUEUE_FLAG_DCA |
dqrr_index;
DPAA2_PER_LCORE_DQRR_SIZE--;
DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dqrr_index);
- (*bufs)->seqn = DPAA2_INVALID_MBUF_SEQN;
+ *dpaa2_seqn(*bufs) = DPAA2_INVALID_MBUF_SEQN;
}
if (likely(RTE_MBUF_DIRECT(*bufs))) {
qbman_eq_desc_set_fq(eqdesc, dpaa2_q->fqid);
- if (m->seqn & DPAA2_ENQUEUE_FLAG_ORP) {
- orpid = (m->seqn & DPAA2_EQCR_OPRID_MASK) >>
+ if (*dpaa2_seqn(m) & DPAA2_ENQUEUE_FLAG_ORP) {
+ orpid = (*dpaa2_seqn(m) & DPAA2_EQCR_OPRID_MASK) >>
DPAA2_EQCR_OPRID_SHIFT;
- seqnum = (m->seqn & DPAA2_EQCR_SEQNUM_MASK) >>
+ seqnum = (*dpaa2_seqn(m) & DPAA2_EQCR_SEQNUM_MASK) >>
DPAA2_EQCR_SEQNUM_SHIFT;
if (!priv->en_loose_ordered) {
qbman_eq_desc_set_orp(eqdesc, 0, orpid, seqnum, 0);
}
} else {
- dq_idx = m->seqn - 1;
+ dq_idx = *dpaa2_seqn(m) - 1;
qbman_eq_desc_set_dca(eqdesc, 1, dq_idx, 0);
DPAA2_PER_LCORE_DQRR_SIZE--;
DPAA2_PER_LCORE_DQRR_HELD &= ~(1 << dq_idx);
}
- m->seqn = DPAA2_INVALID_MBUF_SEQN;
+ *dpaa2_seqn(m) = DPAA2_INVALID_MBUF_SEQN;
}
/* Callback to handle sending ordered packets through WRIOP based interface */
dpaa2_eqcr_size : nb_pkts;
if (!priv->en_loose_ordered) {
- if ((*bufs)->seqn & DPAA2_ENQUEUE_FLAG_ORP) {
+ if (*dpaa2_seqn(*bufs) & DPAA2_ENQUEUE_FLAG_ORP) {
num_free_eq_desc = dpaa2_free_eq_descriptors();
if (num_free_eq_desc < frames_to_send)
frames_to_send = num_free_eq_desc;
/*Prepare enqueue descriptor*/
qbman_eq_desc_clear(&eqdesc[loop]);
- if ((*bufs)->seqn) {
+ if (*dpaa2_seqn(*bufs)) {
/* Use only queue 0 for Tx in case of atomic/
* ordered packets as packets can get unordered
* when being tranmitted out from the interface