net/iavf: fix performance with writeback policy

The iavf driver was trying to use writeback on ITR, but was
never setting an ITR, so it didn't work. This caused performance
to be limited due to too much PCIe traffic and partial writes
during most benchmarking workloads.
Set the ITR during queue setup, which can be checked at runtime
by reading register 0x2800. Setting the value to 2us allows
for generally good streaming packet performance while keeping
latency down.

Fixes: d6bde6b5eae9 ("net/avf: enable Rx interrupt")
Cc: stable@dpdk.org
Reported-by: Brian Johnson <brian.johnson@intel.com>
Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>

diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c
index 92dd141..d12a236 100644 (file)
--- a/drivers/net/iavf/iavf_ethdev.c
+++ b/drivers/net/iavf/iavf_ethdev.c
@@ -474,10 +474,19 @@ static int iavf_config_rx_queues_irqs(struct rte_eth_dev *dev,
                    VIRTCHNL_VF_OFFLOAD_WB_ON_ITR) {
                        /* If WB_ON_ITR supports, enable it */
                        vf->msix_base = IAVF_RX_VEC_START;
+                       /* Set the ITR for index zero, to 2us to make sure that
+                        * we leave time for aggregation to occur, but don't
+                        * increase latency dramatically.
+                        */
                        IAVF_WRITE_REG(hw,
                                       IAVF_VFINT_DYN_CTLN1(vf->msix_base - 1),
-                                      IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK |
-                                      IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK);
+                                      (0 << IAVF_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
+                                      IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK |
+                                      (2UL << IAVF_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
+                       /* debug - check for success! the return value
+                        * should be 2, offset is 0x2800
+                        */
+                       /* IAVF_READ_REG(hw, IAVF_VFINT_ITRN1(0, 0)); */
                } else {
                        /* If no WB_ON_ITR offload flags, need to set
                         * interrupt for descriptor write back.