net/ena/base: prefetch cache with intention to write
authorMichal Krawczyk <mk@semihalf.com>
Tue, 11 May 2021 06:45:44 +0000 (08:45 +0200)
committerFerruh Yigit <ferruh.yigit@intel.com>
Tue, 11 May 2021 13:00:44 +0000 (15:00 +0200)
As in the v20.11 rte_prefetch0_write API was added, it should be used
in the platform file for the definition of the macro prefetchw, instead
of using simply prefetch0.

Signed-off-by: Michal Krawczyk <mk@semihalf.com>
Reviewed-by: Igor Chauskin <igorch@amazon.com>
Reviewed-by: Amit Bernstein <amitbern@amazon.com>
drivers/net/ena/base/ena_plat_dpdk.h

index ddf54f0..9d1426d 100644 (file)
@@ -291,7 +291,7 @@ extern rte_atomic32_t ena_alloc_cnt;
 #define might_sleep()
 
 #define prefetch(x) rte_prefetch0(x)
-#define prefetchw(x) prefetch(x)
+#define prefetchw(x) rte_prefetch0_write(x)
 
 #define lower_32_bits(x) ((uint32_t)(x))
 #define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16))