net/mlx5: fix eCPRI common header endianness

The input header of a RTE flow item is with network byte order. In
the host with little endian, the bit field order are the same as the
byte order.
When checking the eCPRI message type, the wrong field will be selected.
Fixing to use correct field.

Fixes: daa38a8924a0 ("net/mlx5: add flow translation of eCPRI header")
Cc: stable@dpdk.org
Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index d7641e9..b1928a0 100644 (file)
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -7808,6 +7808,7 @@ flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
        struct mlx5_priv *priv = dev->data->dev_private;
        const struct rte_flow_item_ecpri *ecpri_m = item->mask;
        const struct rte_flow_item_ecpri *ecpri_v = item->spec;
+       struct rte_ecpri_common_hdr common;
        void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
                                     misc_parameters_4);
        void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
@@ -7848,7 +7849,8 @@ flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
         * Some wildcard rules only matching type field should be supported.
         */
        if (ecpri_m->hdr.dummy[0]) {
-               switch (ecpri_v->hdr.common.type) {
+               common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
+               switch (common.type) {
                case RTE_ECPRI_MSG_TYPE_IQ_DATA:
                case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
                case RTE_ECPRI_MSG_TYPE_DLY_MSR: