config: rename option for C11 memory model

Keep only single config option RTE_USE_C11_MEM_MODEL for C11 memory
model, so all modules can leverage C11 atomic extension by enable this
option.

Signed-off-by: Phil Yang <phil.yang@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
Acked-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 94cca49..4b23b39 100644 (file)
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -53,7 +53,7 @@ flags_cavium = [
        ['RTE_MAX_NUMA_NODES', 2],
        ['RTE_MAX_LCORE', 96],
        ['RTE_MAX_VFIO_GROUPS', 128],
-       ['RTE_RING_USE_C11_MEM_MODEL', false]]
+       ['RTE_USE_C11_MEM_MODEL', false]]
 flags_dpaa = [
        ['RTE_MACHINE', '"dpaa"'],
        ['RTE_CACHE_LINE_SIZE', 64],

diff --git a/config/common_armv8a_linuxapp b/config/common_armv8a_linuxapp
index 111c005..ad88a37 100644 (file)
--- a/config/common_armv8a_linuxapp
+++ b/config/common_armv8a_linuxapp
@@ -17,6 +17,8 @@ CONFIG_RTE_FORCE_INTRINSICS=y
 # to address minimum DMA alignment across all arm64 implementations.
 CONFIG_RTE_CACHE_LINE_SIZE=128
 
+CONFIG_RTE_USE_C11_MEM_MODEL=y
+
 # Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest)
 # to determine the best threshold in code. Refer to notes in source file
 # (lib/librte_eal/common/include/arch/arm/rte_memcpy_64.h) for more info.
@@ -29,8 +31,6 @@ CONFIG_RTE_ARCH_ARM64_MEMCPY=n
 #CONFIG_RTE_ARM64_MEMCPY_ALIGN_MASK=0xF
 #CONFIG_RTE_ARM64_MEMCPY_STRICT_ALIGN=n
 
-CONFIG_RTE_RING_USE_C11_MEM_MODEL=y
-
 CONFIG_RTE_LIBRTE_FM10K_PMD=n
 CONFIG_RTE_LIBRTE_SFC_EFX_PMD=n
 CONFIG_RTE_LIBRTE_AVP_PMD=n

diff --git a/config/common_base b/config/common_base
index be7365e..38beaab 100644 (file)
--- a/config/common_base
+++ b/config/common_base
@@ -55,6 +55,11 @@ CONFIG_RTE_MAJOR_ABI=
 #
 CONFIG_RTE_CACHE_LINE_SIZE=64
 
+#
+# Memory model
+#
+CONFIG_RTE_USE_C11_MEM_MODEL=n
+
 #
 # Compile Environment Abstraction Layer
 #
@@ -698,7 +703,6 @@ CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV=y
 # Compile librte_ring
 #
 CONFIG_RTE_LIBRTE_RING=y
-CONFIG_RTE_RING_USE_C11_MEM_MODEL=n
 
 #
 # Compile librte_mempool

diff --git a/config/defconfig_arm64-thunderx-linuxapp-gcc b/config/defconfig_arm64-thunderx-linuxapp-gcc
index 2bed66c..fd160aa 100644 (file)
--- a/config/defconfig_arm64-thunderx-linuxapp-gcc
+++ b/config/defconfig_arm64-thunderx-linuxapp-gcc
@@ -7,10 +7,10 @@
 CONFIG_RTE_MACHINE="thunderx"
 
 CONFIG_RTE_CACHE_LINE_SIZE=128
+CONFIG_RTE_USE_C11_MEM_MODEL=n
 CONFIG_RTE_MAX_NUMA_NODES=2
 CONFIG_RTE_MAX_LCORE=96
 CONFIG_RTE_MAX_VFIO_GROUPS=128
-CONFIG_RTE_RING_USE_C11_MEM_MODEL=n
 
 #
 # Compile PMD for octeontx sso event device

diff --git a/lib/librte_ring/rte_ring.h b/lib/librte_ring/rte_ring.h
index 7a731d0..af5444a 100644 (file)
--- a/lib/librte_ring/rte_ring.h
+++ b/lib/librte_ring/rte_ring.h
@@ -303,11 +303,11 @@ void rte_ring_dump(FILE *f, const struct rte_ring *r);
  * There are 2 choices for the users
  * 1.use rmb() memory barrier
  * 2.use one-direcion load_acquire/store_release barrier,defined by
- * CONFIG_RTE_RING_USE_C11_MEM_MODEL=y
+ * CONFIG_RTE_USE_C11_MEM_MODEL=y
  * It depends on performance test results.
  * By default, move common functions to rte_ring_generic.h
  */
-#ifdef RTE_RING_USE_C11_MEM_MODEL
+#ifdef RTE_USE_C11_MEM_MODEL
 #include "rte_ring_c11_mem.h"
 #else
 #include "rte_ring_generic.h"