]> git.droids-corp.org - dpdk.git/commitdiff
net/sfc/base: support different Rx descriptor sizes
authorIgor Romanov <igor.romanov@oktetlabs.ru>
Thu, 7 Feb 2019 16:29:24 +0000 (16:29 +0000)
committerFerruh Yigit <ferruh.yigit@intel.com>
Fri, 8 Feb 2019 10:35:41 +0000 (11:35 +0100)
For consistency with the size of Tx descriptors, the size of Rx
descriptors should be a part of NIC config, not a macro that is
common for all NIC families.

Signed-off-by: Igor Romanov <igor.romanov@oktetlabs.ru>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
drivers/net/sfc/base/ef10_impl.h
drivers/net/sfc/base/ef10_rx.c
drivers/net/sfc/base/efx.h
drivers/net/sfc/base/efx_rx.c
drivers/net/sfc/base/hunt_nic.c
drivers/net/sfc/base/medford2_nic.c
drivers/net/sfc/base/medford_nic.c
drivers/net/sfc/base/siena_impl.h
drivers/net/sfc/base/siena_nic.c

index 0116bc91cae8dba3eabf414220b61180279b6195..11c61d9e61c2e1f7995f3049d0014dd24862e107 100644 (file)
@@ -19,6 +19,7 @@ extern "C" {
 
 #define        EF10_TXQ_MINNDESCS      512
 
+#define        EF10_RXQ_DESC_SIZE      (sizeof (efx_qword_t))
 #define        EF10_TXQ_DESC_SIZE      (sizeof (efx_qword_t))
 
 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
index f2b72571afa39bb0feb9d359d820387ea0a37d15..23b80d78f5fa68467dbd2dcb8b34f420a1333bf5 100644 (file)
@@ -31,7 +31,7 @@ efx_mcdi_init_rxq(
        efx_mcdi_req_t req;
        EFX_MCDI_DECLARE_BUF(payload, MC_CMD_INIT_RXQ_V3_IN_LEN,
                MC_CMD_INIT_RXQ_V3_OUT_LEN);
-       int npages = EFX_RXQ_NBUFS(ndescs);
+       int npages = efx_rxq_nbufs(enp, ndescs);
        int i;
        efx_qword_t *dma_addr;
        uint64_t addr;
@@ -41,7 +41,8 @@ efx_mcdi_init_rxq(
 
        EFSYS_ASSERT3U(ndescs, <=, encp->enc_rxq_max_ndescs);
 
-       if ((esmp == NULL) || (EFSYS_MEM_SIZE(esmp) < EFX_RXQ_SIZE(ndescs))) {
+       if ((esmp == NULL) ||
+           (EFSYS_MEM_SIZE(esmp) < efx_rxq_size(enp, ndescs))) {
                rc = EINVAL;
                goto fail1;
        }
index 506bdb5e1e31140a8722a9e27421af179d7fb66b..101bb4cd210b8cb6dfded20ae549e6873480a3e2 100644 (file)
@@ -1284,6 +1284,7 @@ typedef struct efx_nic_cfg_s {
        uint32_t                enc_evq_timer_quantum_ns;
        uint32_t                enc_evq_timer_max_us;
        uint32_t                enc_clk_mult;
+       uint32_t                enc_rx_desc_size;
        uint32_t                enc_tx_desc_size;
        uint32_t                enc_rx_prefix_size;
        uint32_t                enc_rx_buf_align_start;
@@ -2478,8 +2479,28 @@ efx_pseudo_hdr_pkt_length_get(
 #define        EFX_RXQ_MAXNDESCS               4096
 #define        EFX_RXQ_MINNDESCS               512
 
+/*
+ * This macro is deprecated and will be removed.
+ * Use the function efx_rxq_size() instead.
+ */
 #define        EFX_RXQ_SIZE(_ndescs)           ((_ndescs) * sizeof (efx_qword_t))
+
+/*
+ * This macro is deprecated and will be removed.
+ * Use the function efx_rxq_nbufs() instead.
+ */
 #define        EFX_RXQ_NBUFS(_ndescs)          (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
+
+extern __checkReturn   size_t
+efx_rxq_size(
+       __in    const efx_nic_t *enp,
+       __in    unsigned int ndescs);
+
+extern __checkReturn   unsigned int
+efx_rxq_nbufs(
+       __in    const efx_nic_t *enp,
+       __in    unsigned int ndescs);
+
 #define        EFX_RXQ_LIMIT(_ndescs)          ((_ndescs) - 16)
 
 typedef enum efx_rxq_type_e {
index 8910cd5f7ee01357e2ec620840abca07edbc68b5..c0d73812879637b053235afa06aa56d8e940ef9d 100644 (file)
@@ -766,6 +766,24 @@ fail1:
        return (rc);
 }
 
+       __checkReturn   size_t
+efx_rxq_size(
+       __in    const efx_nic_t *enp,
+       __in    unsigned int ndescs)
+{
+       const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
+
+       return (ndescs * encp->enc_rx_desc_size);
+}
+
+       __checkReturn   unsigned int
+efx_rxq_nbufs(
+       __in    const efx_nic_t *enp,
+       __in    unsigned int ndescs)
+{
+       return (efx_rxq_size(enp, ndescs) / EFX_BUF_SIZE);
+}
+
                        void
 efx_rx_qenable(
        __in            efx_rxq_t *erp)
index b4fc3cc9efec3422fd5217d6d07d2f635834b4f0..2fb54d85a1b2eea17d16b37fed15bf009b43f519 100644 (file)
@@ -186,6 +186,7 @@ hunt_board_cfg(
        /* Checksums for TSO sends can be incorrect on Huntington. */
        encp->enc_bug61297_workaround = B_TRUE;
 
+       encp->enc_rx_desc_size = EF10_RXQ_DESC_SIZE;
        encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE;
 
        /* Alignment for receive packet DMA buffers */
index 9cfc5077c994164eb7159bb76dabc2ee45bf6c75..7d0c8004767b8c4de6ecdc43cebcbe36f5241c2f 100644 (file)
@@ -101,6 +101,7 @@ medford2_board_cfg(
        encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
                    FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
 
+       encp->enc_rx_desc_size = EF10_RXQ_DESC_SIZE;
        encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE;
 
        /* Alignment for receive packet DMA buffers */
index 3f2c5b877c716b4a42f8fe6aca8983d55dd280ca..fd711a96f7e6dff4e6b82ee5fe9ce310b38a862b 100644 (file)
@@ -99,6 +99,7 @@ medford_board_cfg(
        encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
                    FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
 
+       encp->enc_rx_desc_size = EF10_RXQ_DESC_SIZE;
        encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE;
 
        /* Alignment for receive packet DMA buffers */
index 6f07b1ec7cf2e9a08d6d76599e5d331ccd3d53b7..0689600257c9e444f7fda21380608f06733d4678 100644 (file)
@@ -34,6 +34,7 @@ extern "C" {
 #define        SIENA_RXQ_MAXNDESCS     4096
 #define        SIENA_RXQ_MINNDESCS     512
 
+#define        SIENA_RXQ_DESC_SIZE     (sizeof (efx_qword_t))
 #define        SIENA_TXQ_DESC_SIZE     (sizeof (efx_qword_t))
 
 #define        SIENA_NVRAM_CHUNK 0x80
index 987a32d2f193d971d3b1780679b1ccbba216110b..894cf81443c54b4943d7dbaba5493dd032b3041f 100644 (file)
@@ -104,6 +104,7 @@ siena_board_cfg(
        encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
                FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
 
+       encp->enc_rx_desc_size = SIENA_RXQ_DESC_SIZE;
        encp->enc_tx_desc_size = SIENA_TXQ_DESC_SIZE;
 
        /* When hash header insertion is enabled, Siena inserts 16 bytes */