#define TXGBE_IVARMISC 0x0004FC
#define TXGBE_IVARMISC_VEC(v) LS(v, 0, 0x7)
#define TXGBE_IVARMISC_VLD MS(7, 0x1)
+#define TXGBE_PX_INTA 0x000110
#define TXGBE_ICR(i) (0x000120 + (i) * 4) /* 0-1 */
#define TXGBE_ICR_MASK MS(0, 0xFFFFFFFF)
#define TXGBE_ICS(i) (0x000130 + (i) * 4) /* 0-1 */
static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
static int txgbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev);
static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
-static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
+static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev,
+ struct rte_intr_handle *handle);
static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
struct rte_intr_handle *handle);
static void txgbe_dev_interrupt_handler(void *param);
* - On failure, a negative value.
*/
static int
-txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
+txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev,
+ struct rte_intr_handle *intr_handle)
{
uint32_t eicr;
struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
+ if (intr_handle->type != RTE_INTR_HANDLE_UIO &&
+ intr_handle->type != RTE_INTR_HANDLE_VFIO_MSIX)
+ wr32(hw, TXGBE_PX_INTA, 1);
+
/* clear all cause mask */
txgbe_disable_intr(hw);
{
struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
- txgbe_dev_interrupt_get_status(dev);
+ txgbe_dev_interrupt_get_status(dev, dev->intr_handle);
txgbe_dev_interrupt_action(dev, dev->intr_handle);
}