]> git.droids-corp.org - dpdk.git/commitdiff
net/ngbe: support autoneg on/off for external PHY SFI mode
authorJiawen Wu <jiawenwu@trustnetic.com>
Wed, 22 Jun 2022 06:56:12 +0000 (14:56 +0800)
committerFerruh Yigit <ferruh.yigit@xilinx.com>
Wed, 22 Jun 2022 10:32:41 +0000 (12:32 +0200)
Add support for external PHY to switch autoneg on/off on their SFI mode.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
doc/guides/rel_notes/release_22_07.rst
drivers/net/ngbe/base/ngbe_phy_mvl.c
drivers/net/ngbe/base/ngbe_phy_yt.c
drivers/net/ngbe/base/ngbe_phy_yt.h

index ddf6c35c76c53924a9d7dbc49797335df42de873..f79451a3323d30687cc41be4a2262021c7e9252a 100644 (file)
@@ -177,6 +177,7 @@ New Features
 
   * Added support for yt8531s PHY.
   * Added support for OEM subsystem vendor ID.
+  * Added autoneg on/off for external PHY SFI mode.
 
 * **Updated Wangxun txgbe driver.**
 
index c5256359ed79dc82e3f5b467998cf33c7b099e5b..8746a72eb353ead67249b5c3cd88b0e18821c0af 100644 (file)
@@ -203,6 +203,10 @@ s32 ngbe_setup_phy_link_mvl(struct ngbe_hw *hw, u32 speed,
                           MVL_PHY_1000BASET_HALF);
                value_r9 |= value;
                hw->phy.write_reg(hw, MVL_PHY_1000BASET, 0, value_r9);
+
+               value = MVL_CTRL_RESTART_AN | MVL_CTRL_ANE |
+                       MVL_CTRL_RESET | MVL_CTRL_DUPLEX;
+               ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value);
        } else {
                hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;
 
@@ -210,10 +214,16 @@ s32 ngbe_setup_phy_link_mvl(struct ngbe_hw *hw, u32 speed,
                value &= ~(MVL_PHY_1000BASEX_HALF | MVL_PHY_1000BASEX_FULL);
                value |= MVL_PHY_1000BASEX_FULL;
                hw->phy.write_reg(hw, MVL_ANA, 0, value);
-       }
 
-       value = MVL_CTRL_RESTART_AN | MVL_CTRL_ANE | MVL_CTRL_RESET;
-       ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value);
+               if (hw->mac.autoneg)
+                       value = MVL_CTRL_RESTART_AN | MVL_CTRL_ANE |
+                               MVL_CTRL_RESET | MVL_CTRL_DUPLEX |
+                               MVL_CTRL_SPEED_SELECT1;
+               else
+                       value = MVL_CTRL_RESET | MVL_CTRL_DUPLEX |
+                               MVL_CTRL_SPEED_SELECT1;
+               ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value);
+       }
 
 skip_an:
        hw->phy.set_phy_power(hw, true);
index 9dd2b2264f94f4369f0aa31e83aeec9e55619de0..bc1921e68ab98a7b4172525f5c1d84b3168aa422 100644 (file)
@@ -205,8 +205,26 @@ skip_an:
                        YT_CHIP_SW_RST;
                ngbe_write_phy_reg_ext_yt(hw, YT_CHIP, 0, value);
 
+               ngbe_read_phy_reg_sds_ext_yt(hw, YT_AUTO, 0, &value);
+               value &= ~YT_AUTO_SENSING;
+               ngbe_write_phy_reg_sds_ext_yt(hw, YT_AUTO, 0, value);
+
+               ngbe_read_phy_reg_ext_yt(hw, YT_MISC, 0, &value);
+               value |= YT_MISC_RESV;
+               ngbe_write_phy_reg_ext_yt(hw, YT_MISC, 0, value);
+
+               ngbe_read_phy_reg_ext_yt(hw, YT_CHIP, 0, &value);
+               value &= ~YT_CHIP_SW_RST;
+               ngbe_write_phy_reg_ext_yt(hw, YT_CHIP, 0, value);
+
                /* software reset */
-               ngbe_write_phy_reg_sds_ext_yt(hw, 0x0, 0, 0x9140);
+               if (hw->mac.autoneg)
+                       value = YT_BCR_RESET | YT_BCR_ANE | YT_BCR_RESTART_AN |
+                               YT_BCR_DUPLEX | YT_BCR_SPEED_SELECT1;
+               else
+                       value = YT_BCR_RESET | YT_BCR_DUPLEX |
+                               YT_BCR_SPEED_SELECT1;
+               hw->phy.write_reg(hw, YT_BCR, 0, value);
 
                hw->phy.set_phy_power(hw, true);
        } else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(2)) {
index 06e8f77261fc48ecd244541b6738daecf18e0062..ddf992e79ab1a1611745bf23743482a7ed98762e 100644 (file)
 #define   YT_RGMII_CONF2_LINKUP                MS16(4, 0x1)
 #define YT_MISC                                0xA006
 #define   YT_MISC_FIBER_PRIO           MS16(8, 0x1) /* 0 for UTP */
+#define   YT_MISC_RESV                 MS16(0, 0x1)
+
+/* SDS EXT */
+#define YT_AUTO                                0xA5
+#define   YT_AUTO_SENSING              MS16(15, 0x1)
 
 /* MII common registers in UTP and SDS */
 #define YT_BCR                         0x0