ixgbe/base: dma coalescing

Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
[Thomas: split patch]

diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c
index 8a6f8c4..4feb2de 100644 (file)
--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c
+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c
@@ -1042,6 +1042,43 @@ s32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw)
                                IXGBE_NOT_IMPLEMENTED);
 }
 
+/**
+ *  ixgbe_dmac_config - Configure DMA Coalescing registers.
+ *  @hw: pointer to hardware structure
+ *
+ *  Configure DMA coalescing. If enabling dmac, dmac is activated.
+ *  When disabling dmac, dmac enable dmac bit is cleared.
+ **/
+s32 ixgbe_dmac_config(struct ixgbe_hw *hw)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw),
+                               IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_dmac_update_tcs - Configure DMA Coalescing registers.
+ *  @hw: pointer to hardware structure
+ *
+ *  Disables dmac, updates per TC settings, and then enable dmac.
+ **/
+s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw),
+                               IXGBE_NOT_IMPLEMENTED);
+}
+
+/**
+ *  ixgbe_dmac_config_tcs - Configure DMA Coalescing registers.
+ *  @hw: pointer to hardware structure
+ *
+ *  Configure DMA coalescing threshold per TC and set high priority bit for
+ *  FCOE TC. The dmac enable bit must be cleared before configuring.
+ **/
+s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw)
+{
+       return ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw),
+                               IXGBE_NOT_IMPLEMENTED);
+}
 
 
 /**

diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h
index 2013764..14c753d 100644 (file)
--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h
+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h
@@ -179,6 +179,9 @@ void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask);
 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,
                         u16 *wwpn_prefix);
 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs);
+s32 ixgbe_dmac_config(struct ixgbe_hw *hw);
+s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw);
+s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw);
 void ixgbe_disable_rx(struct ixgbe_hw *hw);
 void ixgbe_enable_rx(struct ixgbe_hw *hw);
 

diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
index 9176a95..29a05a5 100644 (file)
--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
@@ -515,6 +515,41 @@ struct ixgbe_thermal_sensor_data {
 #define IXGBE_TDPT2TCCR(_i)    (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
 #define IXGBE_TDPT2TCSR(_i)    (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
 
+/* Power Management */
+/* DMA Coalescing configuration */
+struct ixgbe_dmac_config {
+       u16     watchdog_timer; /* usec units */
+       bool    fcoe_en;
+       u32     link_speed;
+       u8      fcoe_tc;
+       u8      num_tcs;
+};
+
+/*
+ * DMA Coalescing threshold Rx PB TC[n] value in Kilobyte by link speed.
+ * DMACRXT = 10Gbps = 10,000 bits / usec = 1250 bytes / usec 70 * 1250 ==
+ * 87500 bytes [85KB]
+ */
+#define IXGBE_DMACRXT_10G              0x55
+#define IXGBE_DMACRXT_1G               0x09
+#define IXGBE_DMACRXT_100M             0x01
+
+/* DMA Coalescing registers */
+#define IXGBE_DMCMNGTH                 0x15F20 /* Management Threshold */
+#define IXGBE_DMACR                    0x02400 /* Control register */
+#define IXGBE_DMCTH(_i)                        (0x03300 + ((_i) * 4)) /* 8 of these */
+#define IXGBE_DMCTLX                   0x02404 /* Time to Lx request */
+/* DMA Coalescing register fields */
+#define IXGBE_DMCMNGTH_DMCMNGTH_MASK   0x000FFFF0 /* Mng Threshold mask */
+#define IXGBE_DMCMNGTH_DMCMNGTH_SHIFT  4 /* Management Threshold shift */
+#define IXGBE_DMACR_DMACWT_MASK                0x0000FFFF /* Watchdog Timer mask */
+#define IXGBE_DMACR_HIGH_PRI_TC_MASK   0x00FF0000
+#define IXGBE_DMACR_HIGH_PRI_TC_SHIFT  16
+#define IXGBE_DMACR_EN_MNG_IND         0x10000000 /* Enable Mng Indications */
+#define IXGBE_DMACR_LX_COAL_IND                0x40000000 /* Lx Coalescing indicate */
+#define IXGBE_DMACR_DMAC_EN            0x80000000 /* DMA Coalescing Enable */
+#define IXGBE_DMCTH_DMACRXT_MASK       0x000001FF /* Receive Threshold mask */
+#define IXGBE_DMCTLX_TTLX_MASK         0x00000FFF /* Time to Lx request mask */
 
 
 /* Security Control Registers */
@@ -3270,6 +3305,7 @@ struct ixgbe_mac_info {
        u8 flags;
        struct ixgbe_thermal_sensor_data  thermal_sensor_data;
        bool thermal_sensor_enabled;
+       struct ixgbe_dmac_config dmac_config;
        bool set_lben;
 };