raw/octeontx2_dma: add device close operation

Send message to PF to stop DMA queue when device close is
called from application.
Defined the required data structures to support enqueue and
dequeue APIs.

Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>

diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c
index 224c5e5..f9c330d 100644 (file)
--- a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c
+++ b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c
@@ -41,6 +41,34 @@ dma_engine_enb_dis(struct dpi_vf_s *dpivf, const bool enb)
        return DPI_DMA_QUEUE_SUCCESS;
 }
 
+/* Free DMA Queue instruction buffers, and send close notification to PF */
+static inline int
+dma_queue_finish(struct dpi_vf_s *dpivf)
+{
+       uint32_t timeout = 0, sleep = 1;
+       uint64_t reg = 0ULL;
+
+       /* Wait for SADDR to become idle */
+       reg = otx2_read64(dpivf->vf_bar0 + DPI_VDMA_SADDR);
+       while (!(reg & BIT_ULL(DPI_VDMA_SADDR_REQ_IDLE))) {
+               rte_delay_ms(sleep);
+               timeout++;
+               if (timeout >= DPI_QFINISH_TIMEOUT) {
+                       otx2_dpi_dbg("Timeout!!! Closing Forcibly");
+                       break;
+               }
+               reg = otx2_read64(dpivf->vf_bar0 + DPI_VDMA_SADDR);
+       }
+
+       if (otx2_dpi_queue_close(dpivf->vf_id) < 0)
+               return -EACCES;
+
+       rte_mempool_put(dpivf->chunk_pool, dpivf->base_ptr);
+       dpivf->vf_bar0 = (uintptr_t)NULL;
+
+       return DPI_DMA_QUEUE_SUCCESS;
+}
+
 static int
 otx2_dpi_rawdev_configure(const struct rte_rawdev *dev, rte_rawdev_obj_t config)
 {
@@ -140,6 +168,7 @@ otx2_dpi_rawdev_remove(struct rte_pci_device *pci_dev)
 {
        char name[RTE_RAWDEV_NAME_MAX_LEN];
        struct rte_rawdev *rawdev;
+       struct dpi_vf_s *dpivf;
 
        if (pci_dev == NULL) {
                otx2_dpi_dbg("Invalid pci_dev of the device!");
@@ -157,6 +186,10 @@ otx2_dpi_rawdev_remove(struct rte_pci_device *pci_dev)
                return -EINVAL;
        }
 
+       dpivf = (struct dpi_vf_s *)rawdev->dev_private;
+       dma_engine_enb_dis(dpivf, false);
+       dma_queue_finish(dpivf);
+
        /* rte_rawdev_close is called by pmd_release */
        return rte_rawdev_pmd_release(rawdev);
 }

diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h
index 918ae72..f59bab9 100644 (file)
--- a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h
+++ b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h
@@ -31,6 +31,32 @@
 #define DPI_QUEUE_STOP         0x0
 #define DPI_QUEUE_START                0x1
 
+#define DPI_VDMA_SADDR_REQ_IDLE        63
+#define DPI_MAX_POINTER                15
+#define STRM_INC(s)    ((s)->tail = ((s)->tail + 1) % (s)->max_cnt)
+#define DPI_QFINISH_TIMEOUT    (10 * 1000)
+
+/* DPI Transfer Type, pointer type in DPI_DMA_INSTR_HDR_S[XTYPE] */
+#define DPI_XTYPE_OUTBOUND      (0)
+#define DPI_XTYPE_INBOUND       (1)
+#define DPI_XTYPE_INTERNAL_ONLY (2)
+#define DPI_XTYPE_EXTERNAL_ONLY (3)
+#define DPI_XTYPE_MASK         0x3
+#define DPI_HDR_PT_ZBW_CA      0x0
+#define DPI_HDR_PT_ZBW_NC      0x1
+#define DPI_HDR_PT_WQP         0x2
+#define DPI_HDR_PT_WQP_NOSTATUS        0x0
+#define DPI_HDR_PT_WQP_STATUSCA        0x1
+#define DPI_HDR_PT_WQP_STATUSNC        0x3
+#define DPI_HDR_PT_CNT         0x3
+#define DPI_HDR_PT_MASK                0x3
+#define DPI_W0_TT_MASK         0x3
+#define DPI_W0_GRP_MASK                0x3FF
+/* Set Completion data to 0xFF when request submitted,
+ * upon successful request completion engine reset to completion status
+ */
+#define DPI_REQ_CDATA          0xFF
+
 struct dpi_vf_s {
        struct rte_pci_device *dev;
        uint8_t state;
@@ -56,6 +82,113 @@ enum dpi_dma_queue_result_e {
        DPI_DMA_QUEUE_INVALID_PARAM = -2,
 };
 
+struct dpi_dma_req_compl_s {
+       uint64_t cdata;
+       void (*compl_cb)(void *dev, void *arg);
+       void *cb_data;
+};
+
+union dpi_dma_ptr_u {
+       uint64_t u[2];
+       struct dpi_dma_s {
+               uint64_t length:16;
+               uint64_t reserved:44;
+               uint64_t bed:1; /* Big-Endian */
+               uint64_t alloc_l2:1;
+               uint64_t full_write:1;
+               uint64_t invert:1;
+               uint64_t ptr;
+       } s;
+};
+
+struct dpi_dma_buf_ptr_s {
+       union dpi_dma_ptr_u *rptr[DPI_MAX_POINTER]; /* Read From pointer list */
+       union dpi_dma_ptr_u *wptr[DPI_MAX_POINTER]; /* Write to pointer list */
+       uint8_t rptr_cnt;
+       uint8_t wptr_cnt;
+       struct dpi_dma_req_compl_s *comp_ptr;
+};
+
+struct dpi_cring_data_s {
+       struct dpi_dma_req_compl_s **compl_data;
+       uint16_t max_cnt;
+       uint16_t head;
+       uint16_t tail;
+};
+
+struct dpi_dma_queue_ctx_s {
+       uint16_t xtype:2;
+
+       /* Completion pointer type */
+       uint16_t pt:2;
+
+       /* Completion updated using WQE */
+       uint16_t tt:2;
+       uint16_t grp:10;
+       uint32_t tag;
+
+       /* Valid only for Outbound only mode */
+       uint16_t aura:12;
+       uint16_t csel:1;
+       uint16_t ca:1;
+       uint16_t fi:1;
+       uint16_t ii:1;
+       uint16_t fl:1;
+
+       uint16_t pvfe:1;
+       uint16_t dealloce:1;
+       uint16_t req_type:2;
+       uint16_t use_lock:1;
+       uint16_t deallocv;
+
+       struct dpi_cring_data_s *c_ring;
+};
+
+/* DPI DMA Instruction Header Format */
+union dpi_dma_instr_hdr_u {
+       uint64_t u[4];
+
+       struct dpi_dma_instr_hdr_s_s {
+               uint64_t tag:32;
+               uint64_t tt:2;
+               uint64_t grp:10;
+               uint64_t reserved_44_47:4;
+               uint64_t nfst:4;
+               uint64_t reserved_52_53:2;
+               uint64_t nlst:4;
+               uint64_t reserved_58_63:6;
+               /* Word 0 - End */
+
+               uint64_t aura:12;
+               uint64_t reserved_76_79:4;
+               uint64_t deallocv:16;
+               uint64_t dealloce:1;
+               uint64_t pvfe:1;
+               uint64_t reserved_98_99:2;
+               uint64_t pt:2;
+               uint64_t reserved_102_103:2;
+               uint64_t fl:1;
+               uint64_t ii:1;
+               uint64_t fi:1;
+               uint64_t ca:1;
+               uint64_t csel:1;
+               uint64_t reserved_109_111:3;
+               uint64_t xtype:2;
+               uint64_t reserved_114_119:6;
+               uint64_t fport:2;
+               uint64_t reserved_122_123:2;
+               uint64_t lport:2;
+               uint64_t reserved_126_127:2;
+               /* Word 1 - End */
+
+               uint64_t ptr:64;
+               /* Word 2 - End */
+
+               uint64_t reserved_192_255:64;
+               /* Word 3 - End */
+       } s;
+};
+
 int otx2_dpi_queue_open(uint16_t vf_id, uint32_t size, uint32_t gaura);
 int otx2_dpi_queue_close(uint16_t vf_id);