common/mlx5: add HCA capabilities for AES-XTS crypto
authorDekel Peled <dekelp@nvidia.com>
Tue, 4 May 2021 17:54:49 +0000 (20:54 +0300)
committerThomas Monjalon <thomas@monjalon.net>
Tue, 4 May 2021 20:41:39 +0000 (22:41 +0200)
Update the PRM structure and HCA capabilities reading, to include
relevant capabilities for AES-XTS crypto.

Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
drivers/common/mlx5/mlx5_devx_cmds.c
drivers/common/mlx5/mlx5_devx_cmds.h
drivers/common/mlx5/mlx5_prm.h

index 8af2773..68bb6f9 100644 (file)
@@ -771,6 +771,9 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
                MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled);
        attr->umr_modify_entity_size_disabled =
                MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled);
+       attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto);
+       if (attr->crypto)
+               attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts);
        if (attr->qos.sup) {
                MLX5_SET(query_hca_cap_in, in, op_mod,
                         MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
index eee8fee..c0e6fab 100644 (file)
@@ -136,6 +136,8 @@ struct mlx5_hca_attr {
        uint32_t qp_ts_format:2;
        uint32_t regex:1;
        uint32_t reg_c_preserve:1;
+       uint32_t crypto:1; /* Crypto engine is supported. */
+       uint32_t aes_xts:1; /* AES-XTS crypto is supported. */
        uint32_t regexp_num_of_engines;
        uint32_t log_max_ft_sampler_num:8;
        uint32_t geneve_tlv_opt;
index a5a9c17..158d486 100644 (file)
@@ -1427,7 +1427,10 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8 sq_ts_format[0x2];
        u8 rq_ts_format[0x2];
        u8 reserved_at_444[0x1C];
-       u8 reserved_at_460[0x10];
+       u8 reserved_at_460[0x8];
+       u8 aes_xts[0x1];
+       u8 crypto[0x1];
+       u8 reserved_at_46a[0x6];
        u8 max_num_eqs[0x10];
        u8 reserved_at_480[0x3];
        u8 log_max_l2_table[0x5];