net/sfc/base: move legacy board config to ef10 NIC board cfg

Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>

diff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c
index ce99d09..5f4357b 100644 (file)
--- a/drivers/net/sfc/base/ef10_nic.c
+++ b/drivers/net/sfc/base/ef10_nic.c
@@ -1548,6 +1548,7 @@ ef10_nic_board_cfg(
        const efx_nic_ops_t *enop = enp->en_enop;
        efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
        efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
+       uint32_t board_type = 0;
        uint32_t port;
        uint32_t pf;
        uint32_t vf;
@@ -1605,13 +1606,28 @@ ef10_nic_board_cfg(
 
        EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
 
+       /* Board configuration (legacy) */
+       rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
+       if (rc != 0) {
+               /* Unprivileged functions may not be able to read board cfg */
+               if (rc == EACCES)
+                       board_type = 0;
+               else
+                       goto fail5;
+       }
+
+       encp->enc_board_type = board_type;
+       encp->enc_clk_mult = 1; /* not used for EF10 */
+
        /* Get remaining controller-specific board config */
        if ((rc = enop->eno_board_cfg(enp)) != 0)
                if (rc != EACCES)
-                       goto fail5;
+                       goto fail6;
 
        return (0);
 
+fail6:
+       EFSYS_PROBE(fail6);
 fail5:
        EFSYS_PROBE(fail5);
 fail4:

diff --git a/drivers/net/sfc/base/hunt_nic.c b/drivers/net/sfc/base/hunt_nic.c
index 13f769c..58c2d13 100644 (file)
--- a/drivers/net/sfc/base/hunt_nic.c
+++ b/drivers/net/sfc/base/hunt_nic.c
@@ -77,7 +77,6 @@ hunt_board_cfg(
        __in            efx_nic_t *enp)
 {
        efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
-       uint32_t board_type = 0;
        ef10_link_state_t els;
        efx_port_t *epp = &(enp->en_port);
        uint32_t mask;
@@ -97,26 +96,13 @@ hunt_board_cfg(
        EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K  == 8192);
        encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
 
-       /* Board configuration */
-       rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
-       if (rc != 0) {
-               /* Unprivileged functions may not be able to read board cfg */
-               if (rc == EACCES)
-                       board_type = 0;
-               else
-                       goto fail1;
-       }
-
-       encp->enc_board_type = board_type;
-       encp->enc_clk_mult = 1; /* not used for Huntington */
-
        /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
        if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
-               goto fail2;
+               goto fail1;
 
        /* Obtain the default PHY advertised capabilities */
        if ((rc = ef10_phy_get_link(enp, &els)) != 0)
-               goto fail3;
+               goto fail2;
        epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
        epp->ep_adv_cap_mask = els.els_adv_cap_mask;
 
@@ -147,7 +133,7 @@ hunt_board_cfg(
        else if ((rc == ENOTSUP) || (rc == ENOENT))
                encp->enc_bug35388_workaround = B_FALSE;
        else
-               goto fail4;
+               goto fail3;
 
        /*
         * If the bug41750 workaround is enabled, then do not test interrupts,
@@ -166,7 +152,7 @@ hunt_board_cfg(
        } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
                encp->enc_bug41750_workaround = B_FALSE;
        } else {
-               goto fail5;
+               goto fail4;
        }
        if (EFX_PCI_FUNCTION_IS_VF(encp)) {
                /* Interrupt testing does not work for VFs. See bug50084. */
@@ -204,12 +190,12 @@ hunt_board_cfg(
        } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
                encp->enc_bug26807_workaround = B_FALSE;
        } else {
-               goto fail6;
+               goto fail5;
        }
 
        /* Get clock frequencies (in MHz). */
        if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
-               goto fail7;
+               goto fail6;
 
        /*
         * The Huntington timer quantum is 1536 sysclk cycles, documented for
@@ -228,7 +214,7 @@ hunt_board_cfg(
 
        /* Check capabilities of running datapath firmware */
        if ((rc = ef10_get_datapath_caps(enp)) != 0)
-               goto fail8;
+               goto fail7;
 
        /* Alignment for receive packet DMA buffers */
        encp->enc_rx_buf_align_start = 1;
@@ -278,13 +264,13 @@ hunt_board_cfg(
         * can result in time-of-check/time-of-use bugs.
         */
        if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
-               goto fail9;
+               goto fail8;
        encp->enc_privilege_mask = mask;
 
        /* Get interrupt vector limits */
        if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
                if (EFX_PCI_FUNCTION_IS_PF(encp))
-                       goto fail10;
+                       goto fail9;
 
                /* Ignore error (cannot query vector limits from a VF). */
                base = 0;
@@ -300,7 +286,7 @@ hunt_board_cfg(
        encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
 
        if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
-               goto fail11;
+               goto fail10;
        encp->enc_required_pcie_bandwidth_mbps = bandwidth;
 
        /* All Huntington devices have a PCIe Gen3, 8 lane connector */
@@ -308,8 +294,6 @@ hunt_board_cfg(
 
        return (0);
 
-fail11:
-       EFSYS_PROBE(fail11);
 fail10:
        EFSYS_PROBE(fail10);
 fail9:

diff --git a/drivers/net/sfc/base/medford2_nic.c b/drivers/net/sfc/base/medford2_nic.c
index 1fbc71e..2bd3d83 100644 (file)
--- a/drivers/net/sfc/base/medford2_nic.c
+++ b/drivers/net/sfc/base/medford2_nic.c
@@ -49,7 +49,6 @@ medford2_board_cfg(
        __in            efx_nic_t *enp)
 {
        efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
-       uint32_t board_type = 0;
        ef10_link_state_t els;
        efx_port_t *epp = &(enp->en_port);
        uint32_t mask;
@@ -73,26 +72,13 @@ medford2_board_cfg(
        encp->enc_vi_window_shift = vi_window_shift;
 
 
-       /* Board configuration */
-       rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
-       if (rc != 0) {
-               /* Unprivileged functions may not be able to read board cfg */
-               if (rc == EACCES)
-                       board_type = 0;
-               else
-                       goto fail2;
-       }
-
-       encp->enc_board_type = board_type;
-       encp->enc_clk_mult = 1; /* not used for Medford2 */
-
        /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
        if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
-               goto fail3;
+               goto fail2;
 
        /* Obtain the default PHY advertised capabilities */
        if ((rc = ef10_phy_get_link(enp, &els)) != 0)
-               goto fail4;
+               goto fail3;
        epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
        epp->ep_adv_cap_mask = els.els_adv_cap_mask;
 
@@ -136,11 +122,11 @@ medford2_board_cfg(
        else if ((rc == ENOTSUP) || (rc == ENOENT))
                encp->enc_bug61265_workaround = B_FALSE;
        else
-               goto fail5;
+               goto fail4;
 
        /* Get clock frequencies (in MHz). */
        if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
-               goto fail6;
+               goto fail5;
 
        /*
         * The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for
@@ -152,7 +138,7 @@ medford2_board_cfg(
 
        /* Check capabilities of running datapath firmware */
        if ((rc = ef10_get_datapath_caps(enp)) != 0)
-               goto fail7;
+               goto fail6;
 
        /* Alignment for receive packet DMA buffers */
        encp->enc_rx_buf_align_start = 1;
@@ -160,7 +146,7 @@ medford2_board_cfg(
        /* Get the RX DMA end padding alignment configuration */
        if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
                if (rc != EACCES)
-                       goto fail8;
+                       goto fail7;
 
                /* Assume largest tail padding size supported by hardware */
                end_padding = 256;
@@ -212,13 +198,13 @@ medford2_board_cfg(
         * can result in time-of-check/time-of-use bugs.
         */
        if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
-               goto fail9;
+               goto fail8;
        encp->enc_privilege_mask = mask;
 
        /* Get interrupt vector limits */
        if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
                if (EFX_PCI_FUNCTION_IS_PF(encp))
-                       goto fail10;
+                       goto fail9;
 
                /* Ignore error (cannot query vector limits from a VF). */
                base = 0;
@@ -241,14 +227,12 @@ medford2_board_cfg(
 
        rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
        if (rc != 0)
-               goto fail11;
+               goto fail10;
        encp->enc_required_pcie_bandwidth_mbps = bandwidth;
        encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
 
        return (0);
 
-fail11:
-       EFSYS_PROBE(fail11);
 fail10:
        EFSYS_PROBE(fail10);
 fail9:

diff --git a/drivers/net/sfc/base/medford_nic.c b/drivers/net/sfc/base/medford_nic.c
index ede77f8..7840c33 100644 (file)
--- a/drivers/net/sfc/base/medford_nic.c
+++ b/drivers/net/sfc/base/medford_nic.c
@@ -47,7 +47,6 @@ medford_board_cfg(
        __in            efx_nic_t *enp)
 {
        efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
-       uint32_t board_type = 0;
        ef10_link_state_t els;
        efx_port_t *epp = &(enp->en_port);
        uint32_t mask;
@@ -72,26 +71,13 @@ medford_board_cfg(
        EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K  == 8192);
        encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
 
-       /* Board configuration */
-       rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
-       if (rc != 0) {
-               /* Unprivileged functions may not be able to read board cfg */
-               if (rc == EACCES)
-                       board_type = 0;
-               else
-                       goto fail1;
-       }
-
-       encp->enc_board_type = board_type;
-       encp->enc_clk_mult = 1; /* not used for Medford */
-
        /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
        if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
-               goto fail2;
+               goto fail1;
 
        /* Obtain the default PHY advertised capabilities */
        if ((rc = ef10_phy_get_link(enp, &els)) != 0)
-               goto fail3;
+               goto fail2;
        epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
        epp->ep_adv_cap_mask = els.els_adv_cap_mask;
 
@@ -135,11 +121,11 @@ medford_board_cfg(
        else if ((rc == ENOTSUP) || (rc == ENOENT))
                encp->enc_bug61265_workaround = B_FALSE;
        else
-               goto fail4;
+               goto fail3;
 
        /* Get clock frequencies (in MHz). */
        if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
-               goto fail5;
+               goto fail4;
 
        /*
         * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
@@ -151,7 +137,7 @@ medford_board_cfg(
 
        /* Check capabilities of running datapath firmware */
        if ((rc = ef10_get_datapath_caps(enp)) != 0)
-               goto fail6;
+               goto fail5;
 
        /* Alignment for receive packet DMA buffers */
        encp->enc_rx_buf_align_start = 1;
@@ -159,7 +145,7 @@ medford_board_cfg(
        /* Get the RX DMA end padding alignment configuration */
        if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
                if (rc != EACCES)
-                       goto fail7;
+                       goto fail6;
 
                /* Assume largest tail padding size supported by hardware */
                end_padding = 256;
@@ -211,13 +197,13 @@ medford_board_cfg(
         * can result in time-of-check/time-of-use bugs.
         */
        if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
-               goto fail8;
+               goto fail7;
        encp->enc_privilege_mask = mask;
 
        /* Get interrupt vector limits */
        if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
                if (EFX_PCI_FUNCTION_IS_PF(encp))
-                       goto fail9;
+                       goto fail8;
 
                /* Ignore error (cannot query vector limits from a VF). */
                base = 0;
@@ -240,14 +226,12 @@ medford_board_cfg(
 
        rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
        if (rc != 0)
-               goto fail10;
+               goto fail9;
        encp->enc_required_pcie_bandwidth_mbps = bandwidth;
        encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
 
        return (0);
 
-fail10:
-       EFSYS_PROBE(fail10);
 fail9:
        EFSYS_PROBE(fail9);
 fail8: