net/i40e: fix Tx descriptor status api

The Tx descriptor status api was not behaving as expected. This API is
used to inspect the content of the descriptors in the Tx ring to
determine the length of the Tx queue.

Since the software advances the tail pointer and the hardware advances
the head pointer, the Tx queue is located before txq->tx_tail in the
ring. Therefore, a call to rte_eth_tx_descriptor_status(..., offset=20)
should inspect the 20th descriptor before the tail, not after.

As before, we still need to take care about only checking descriptors
that have the RS bit.

Additionally, we can avoid an access to the ring if offset is greater or
equal to nb_tx_desc - nb_tx_free.

Fixes: 68a43d1bb023 ("net/i40e: implement descriptor status API")
Signed-off-by: Olivier Matz <olivier.matz@6wind.com>
Signed-off-by: Didier Pallard <didier.pallard@6wind.com>

diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c
index 6032d554162eba1a6763aba4768126bb16a58600..a1dde1180dfbf36c25adf9b741fd5f7ddc05e867 100644 (file)
--- a/drivers/net/i40e/i40e_rxtx.c
+++ b/drivers/net/i40e/i40e_rxtx.c
@@ -2026,22 +2026,39 @@ i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
        struct i40e_tx_queue *txq = tx_queue;
        volatile uint64_t *status;
        uint64_t mask, expect;
-       uint32_t desc;
+       int32_t desc, dd;
 
        if (unlikely(offset >= txq->nb_tx_desc))
                return -EINVAL;
+       if (offset >= txq->nb_tx_desc - txq->nb_tx_free)
+               return RTE_ETH_TX_DESC_DONE;
+
+       desc = txq->tx_tail - offset - 1;
+       if (desc < 0)
+               desc += txq->nb_tx_desc;
 
-       desc = txq->tx_tail + offset;
-       /* go to next desc that has the RS bit */
-       desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
-               txq->tx_rs_thresh;
-       if (desc >= txq->nb_tx_desc) {
-               desc -= txq->nb_tx_desc;
-               if (desc >= txq->nb_tx_desc)
-                       desc -= txq->nb_tx_desc;
+       /* offset is too small, no other way than reading PCI reg */
+       if (unlikely(offset < txq->tx_rs_thresh)) {
+               int16_t tx_head, queue_size;
+               tx_head = I40E_READ_REG(I40E_VSI_TO_HW(txq->vsi),
+                                       I40E_QTX_HEAD(txq->reg_idx));
+               queue_size = txq->tx_tail - tx_head;
+               if (queue_size < 0)
+                       queue_size += txq->nb_tx_desc;
+               return queue_size > offset ? RTE_ETH_TX_DESC_FULL :
+                       RTE_ETH_TX_DESC_DONE;
        }
 
-       status = &txq->tx_ring[desc].cmd_type_offset_bsz;
+       /* index of the dd bit to look at */
+       dd = (desc / txq->tx_rs_thresh + 1) * txq->tx_rs_thresh - 1;
+
+       /* In full featured mode, RS bit is only set in the last descriptor */
+       /* of a multisegments packet */
+       if (!((txq->offloads == 0) &&
+             (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)))
+               dd = txq->sw_ring[dd].last_id;
+
+       status = &txq->tx_ring[dd].cmd_type_offset_bsz;
        mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
        expect = rte_cpu_to_le_64(
                I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);