dpdk.git
3 years agonet/nfp: remove compile time log
Ferruh Yigit [Tue, 18 May 2021 10:41:15 +0000 (11:41 +0100)]
net/nfp: remove compile time log

Logging should be converted to dynamic log.

Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
Reviewed-by: Heinrich Kuhn <heinrich.kuhn@netronome.com>
3 years agonet/ice: fix bandwidth config size in memory copy
Ting Xu [Tue, 27 Jul 2021 10:55:08 +0000 (18:55 +0800)]
net/ice: fix bandwidth config size in memory copy

The memory size of bandwidth config parameters is not set correctly in
memory copy process, which leads to the wrong values. This patch fixed
the size to the correct value.

Fixes: 3a6bfc37eaf4 ("net/ice: support QoS config VF bandwidth in DCF")
Cc: stable@dpdk.org
Signed-off-by: Ting Xu <ting.xu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
3 years agonet/ice: fix max entry number for ACL normal priority
Simei Su [Wed, 28 Jul 2021 02:24:29 +0000 (10:24 +0800)]
net/ice: fix max entry number for ACL normal priority

For ACL, there are three entry priorities: LOW, NORMAL, HIGH.
Low priority starts from the highest index, 25% of total entries;
Normal priority starts from the highest index, 50% of total entries;
High priority starts from the lowest index, 25% of total entries.

Each TCAM block has 512 entries of 40 bits. Currently, there is a
scenario in which multiple TCAM blocks are cascaded. It means the
total entries are 512. The default priority is NORMAL, so the max
entry is 256, not 512. This patch changes the max entry number for
NORMAL priority.

Fixes: 40d466fa9f76 ("net/ice: support ACL filter in DCF")
Cc: stable@dpdk.org
Signed-off-by: Simei Su <simei.su@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
3 years agonet/ice/base: increase maximum TCAM/PTG per profile
Qi Zhang [Tue, 10 Aug 2021 02:51:40 +0000 (10:51 +0800)]
net/ice/base: increase maximum TCAM/PTG per profile

For GTPoGRE protocol in AVF FDIR/RSS, the number of associated PTGs
of one Profile may exceed the defined ICE_MAX_PTG_PER_PROFILE and
ICE_MAX_TCAM_PER_PROFILE. In those cases, some PTGs may be missed,
and therefore, the related and received packets will not have hash
values. Thus, this patch updated the ICE_MAX_PTG_PER_PROFILE and
ICE_MAX_TCAM_PER_PROFILE to a larger number 64.

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: fix typo in comment
Qi Zhang [Tue, 10 Aug 2021 02:51:39 +0000 (10:51 +0800)]
net/ice/base: fix typo in comment

Correct spelling of word data instead of date.

Fixes: 453d087ccaff ("net/ice/base: add common functions")
Cc: stable@dpdk.org
Signed-off-by: Kevin Scott <kevin.c.scott@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: rename and add setter for unicast MAC flag
Qi Zhang [Tue, 10 Aug 2021 02:51:38 +0000 (10:51 +0800)]
net/ice/base: rename and add setter for unicast MAC flag

Rename ucast_shared to umac_shared, as "umac" is a more widely
used shorthand for "unicast MAC".

Also add a helper function to set this flag. This helper is
expected to be called by core drivers.

Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: support flow director for GTPU UL/DL with QFI
Qi Zhang [Tue, 10 Aug 2021 02:51:37 +0000 (10:51 +0800)]
net/ice/base: support flow director for GTPU UL/DL with QFI

Enable Flow Director filtering for GTPU UL/DL QFI field matching.

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: enable jumbo frame during HW init
Qi Zhang [Tue, 10 Aug 2021 02:51:36 +0000 (10:51 +0800)]
net/ice/base: enable jumbo frame during HW init

Call ice_aq_set_mac_cfg in ice_hw_init to enable jumbo frame support.

Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: support RSS for IPv4/L4 checksum
Qi Zhang [Tue, 10 Aug 2021 02:51:35 +0000 (10:51 +0800)]
net/ice/base: support RSS for IPv4/L4 checksum

The IPv4/TCP/UDP/SCTP header checksum fields are defined in this
patch and can be used as RSS input sets.

Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: support flow director for GTPoGRE
Qi Zhang [Tue, 10 Aug 2021 02:51:34 +0000 (10:51 +0800)]
net/ice/base: support flow director for GTPoGRE

Enable Flow Director filtering for GTPoGRE inner/outer fields
matching.

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: enable NVM update reset capabilities
Qi Zhang [Tue, 10 Aug 2021 02:51:33 +0000 (10:51 +0800)]
net/ice/base: enable NVM update reset capabilities

Add logic to parse capabilities relating to the firmware update reset
requirements. This includes both capability 0x76, which informs the
driver if the firmware can sometimes skip PCIe resets, and 0x77, which
informs the driver if the firmware might potentially restrict EMP
resets.

For capability 0x76, if the number is 1, the firmware will report the
required reset level for a given update as part of its response to the
last command sent to program the NVM bank. (Otherwise, if the firmware
does not support this capability then it will always send a 0 in the
field of the response).

For capability 0x77, if the number is 1, the firmware will report when
EMP reset is available as part of the response to the command for
switching flash banks. (Otherwise, if the firmware does not support this
capability, it will always send a 0 in the field of the response
message).

These capabilities are required to implement immediate firmware
activation. If the capabilities are set, software can read the response
data and determine what reset level is required to activate the firmware
image. If only an EMP reset is required, and if the EMP reset is not
restricted by firmware, then the driver can issue an EMP reset to
immediately activate the new firmware.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: support RSS for GTPoGRE
Qi Zhang [Tue, 10 Aug 2021 02:51:32 +0000 (10:51 +0800)]
net/ice/base: support RSS for GTPoGRE

Support RSS for GTPoGRE inner fields hash.

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: support flow director for GTPU EH inner IPv6
Qi Zhang [Tue, 10 Aug 2021 02:51:31 +0000 (10:51 +0800)]
net/ice/base: support flow director for GTPU EH inner IPv6

Support FDIR filtering for IPV4_GTPU_EH_IPV6 with inner
IPV6/UDP/TCP fields matching.

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: support RSS for GRE tunnel
Qi Zhang [Tue, 10 Aug 2021 02:51:30 +0000 (10:51 +0800)]
net/ice/base: support RSS for GRE tunnel

Support RSS of inner headers for GRE tunnel packet.

Signed-off-by: Wenjun Wu <wenjun1.wu@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: support flow director for GRE tunnel
Qi Zhang [Tue, 10 Aug 2021 02:51:29 +0000 (10:51 +0800)]
net/ice/base: support flow director for GRE tunnel

Support IPV4_GRE and IPV6_GRE with inner IPV4/IPV6/UDP/TCP for
FDIR.

Signed-off-by: Wenjun Wu <wenjun1.wu@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: support TC nodes PIR configuration
Qi Zhang [Tue, 10 Aug 2021 02:51:28 +0000 (10:51 +0800)]
net/ice/base: support TC nodes PIR configuration

TC nodes CIR configuration is not supported. In order to configure PIR,
the corresponding adminq command should not include the flag for CIR.
Since the TC node info has this flag by default, it is supposed to delete
this flag for TC nodes before sending the adminq command.

Signed-off-by: Ting Xu <ting.xu@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: refine MAC rule adding
Qi Zhang [Tue, 10 Aug 2021 02:51:27 +0000 (10:51 +0800)]
net/ice/base: refine MAC rule adding

Move replay_pre_init function to interface.
Add further MAC rules, despite unicast address is already on list.

Signed-off-by: Marcin Domagala <marcinx.domagala@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: add new AQ description
Qi Zhang [Tue, 10 Aug 2021 02:51:26 +0000 (10:51 +0800)]
net/ice/base: add new AQ description

Add ice_aqc_sw_gpio struct to ice_aq_desc
This change allows us to do SW_GPIO AQ cmd transactions
over ice_aq_send_cmd() interface.

Signed-off-by: Siddaraju DH <siddaraju.dh@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: implement firmware debug dump
Qi Zhang [Tue, 10 Aug 2021 02:51:25 +0000 (10:51 +0800)]
net/ice/base: implement firmware debug dump

Basic implementation of FW Debug Dump.

Signed-off-by: Marcin Domagala <marcinx.domagala@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: add E810T check function
Qi Zhang [Tue, 10 Aug 2021 02:51:24 +0000 (10:51 +0800)]
net/ice/base: add E810T check function

Add function ice_is_e810t() to be able to distinguish if hardware is
E810T based or not.

Signed-off-by: Michal Michalik <michal.michalik@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: support starting PHY in bypass mode
Qi Zhang [Tue, 10 Aug 2021 02:51:23 +0000 (10:51 +0800)]
net/ice/base: support starting PHY in bypass mode

After starting the timestamping block, hardware begins calculating
precise offsets through a process of vernier calibration. This process
measures the effective phase offset of the various internal clocks used
in the PHY.

Once hardware completes these measurements, the P_REG_TX_OV_STATUS and
P_REG_RX_OV_STATUS registers are updated to indicate that the hardware
offset measurements are done.

This process does not happen immediately, but requires that at least one
packet be sent or received in order for the offset in that direction to
be calculated.

This poses a problem in some setups, because software expects the first
packet sent to be timestamped. This most often occurs if the clock time
is set by an application during startup. This set time command triggers
a PHY restart. Because of this, the timestamping block is reset, and
timestamps are not enabled until vernier calibration is complete. Since
this process won't complete until at least one packet is sent through
the PHY, timestamps of the very first packet sent will not be obtained.

This can result in the application failing due to missing timestamps.

To avoid this, allow starting the PHY in bypass mode. This mode enables
timestamps immediately, and skips adding the precise offset measurement.
This reduces the accuracy of the timestamp slightly, but ensures that we
get a reasonable value for the first packet.

The driver can continue monitoring the P_REG_TX_OV_STATUS and
P_REG_RX_OV_STATUS registers and exit bypass mode once the total
calibration is completed. In this way, once calibration is complete, the
timestamps will have the precise offset, but we do not break
applications which expect to be able to timestamp immediately.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: clarify comments on checking PFC mode
Qi Zhang [Tue, 10 Aug 2021 02:51:22 +0000 (10:51 +0800)]
net/ice/base: clarify comments on checking PFC mode

Rework the comment around checking PFC mode to make it clear why we are
checking the mode after sending the command.

Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: implement Vernier calibration for E822
Qi Zhang [Tue, 10 Aug 2021 02:51:21 +0000 (10:51 +0800)]
net/ice/base: implement Vernier calibration for E822

Move the implementation of Vernier calibration from Linux core ice_ptp.c
into the shared ice_ptp_hw.c file.

This implementation was recently refactored in Linux, so the move should
be verbatim with the latest Linux code that we had implemented.

This includes a new constant table with pre-determined values based on
link speed, new functions to aide in reading the multi-register values
from the PHY, functions to program the PAR/PCS conversion ratios, and
the UIX conversion ratios, functions to program the total Tx and Rx
offset after vernier calibration in the hardware completes, and finally
a function to start and stop the PHY timestamping block.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: print human-friendly PHY types
Qi Zhang [Tue, 10 Aug 2021 02:51:20 +0000 (10:51 +0800)]
net/ice/base: print human-friendly PHY types

Add functions to print PHY types in human-friendly form

Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: add accessors to get/set time reference
Qi Zhang [Tue, 10 Aug 2021 02:51:19 +0000 (10:51 +0800)]
net/ice/base: add accessors to get/set time reference

The E822 device clock might come from a variety of different sources,
called TIME_REFs. The firmware reports the current TIME_REF as part of
its function capabilities, which the driver caches when it loads.

Add an accessor function to look up the current TIME_REF from the
capabilities. This reduces line length significantly and also avoids
a tight coupling to the capabilities structure.

In some cases, TIME_REF might change at run time. This can occur in the
event that the CGU registers are updated. When this happens, its
possible that the capabilities structure can be out of date until the
capabilities are re-read.

Add a setter function to update the TIME_REF when this occurs. The
driver can call this function after updating the CGU to ensure that the
TIME_REF in the capabilities structure is up to date, without needing to
re-read the entire capabilities from firmware.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: add clock initialization function
Qi Zhang [Tue, 10 Aug 2021 02:51:18 +0000 (10:51 +0800)]
net/ice/base: add clock initialization function

Before the device PTP hardware clock can be initialized, some steps must
be taken by the driver. This includes writing some registers and
initializing the PHY.

Some of these steps are distinct depending on the device type (E810 or
E822). Additionally, a future change will introduce more steps for E822
devices to program the Clock Generation Unit.

Introduce ice_ptp_init_phc as well as device-specific sub-functions for
e810 and e822 devices.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: add timestamp masks
Qi Zhang [Tue, 10 Aug 2021 02:51:17 +0000 (10:51 +0800)]
net/ice/base: add timestamp masks

Adding macros for shift and masking of the lower timestamp work in the
Rx flex descriptor. The LSB of the timestamp-low word indicates the
validity of the timestamp while the rest 7 bits contain the timestamp.

Signed-off-by: Vignesh Sridhar <vignesh.sridhar@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: change dummy packets with VLAN
Qi Zhang [Tue, 10 Aug 2021 02:51:16 +0000 (10:51 +0800)]
net/ice/base: change dummy packets with VLAN

Ethertype was traded as VLAN tpid in dummy packets with VLAN.
This led to a problem when user wanted to add filter for VLAN and
ethertype.

Change ice_vlan_hdr to reflect correct order of VLAN fields in
packets (VLAN tpid, VLAN id). Correct all dummy packets with VLAN.
Move VLAN fields before ethertype and change offsets. Leave values
from dummy packets unchanged as they fit to new VLAN layout.

Order of offsets in ice_prot_ext_tbl_entry for VLAN protocol should
reflect order of fields in ice_vlan_hdr. However, hardware doesn't
support matching on all tpid. This should be done by matching on
packet flags. There is no FV word with protocol for VLAN and offset
2. Because of that, adding vlan tpid with not zero mask will lead
to error in creating recipe.

Signed-off-by: Michal Swiatkowski <michal.swiatkowski@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: add ethertype IPv6 check for dummy packet
Qi Zhang [Tue, 10 Aug 2021 02:51:15 +0000 (10:51 +0800)]
net/ice/base: add ethertype IPv6 check for dummy packet

In order to support switch rule for ethertype filter
with ipv6 ethertype id, it has to check ethertype and
then find a proper dummy packet. There was a silent
assumption that packet is ipv4, unless src or dst ipv6
address is specified in a flow.

Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: add functions for device clock control
Qi Zhang [Tue, 10 Aug 2021 02:51:14 +0000 (10:51 +0800)]
net/ice/base: add functions for device clock control

The ice hardware supports exposing a hardware clock for high precision
timestamping. This is primarily intended for accelerating the Precision
Time Protocol.

Add several low level functions intended to be used as the basis for
enabling the device clock, and ensuring that the port timers are
synchronized properly.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: add IEEE 1588 capability probing
Qi Zhang [Tue, 10 Aug 2021 02:51:13 +0000 (10:51 +0800)]
net/ice/base: add IEEE 1588 capability probing

Parse 1588 timesync capability during device capability probing.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/i40e: fix clang warning on non-x86
Ruifeng Wang [Fri, 30 Jul 2021 09:32:58 +0000 (17:32 +0800)]
net/i40e: fix clang warning on non-x86

Build on aarch64 with clang-10 has warning:
i40e_rxtx.c:3228:1:
warning: unused function 'get_avx_supported' [-Wunused-function]

The function is used in x86 specific path. Moved it into ifdef
to fix build on non-x86.

Fixes: c30751afc360 ("net/i40e: fix data path selection in secondary process")
Cc: stable@dpdk.org
Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
3 years agonet/ice: fix priority of DCF switch rule
Wenjun Wu [Mon, 2 Aug 2021 07:25:17 +0000 (15:25 +0800)]
net/ice: fix priority of DCF switch rule

This patch fixes the reversed priority of DCF switch rule. Priority 0
and 1 are supported, and priority 0 should be the highest priority.

Fixes: 2321e34c23b3 ("net/ice: support flow priority for DCF switch filter")
Cc: stable@dpdk.org
Signed-off-by: Wenjun Wu <wenjun1.wu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
3 years agonet/i40e: reduce L1 cache misses in NEON Rx
Feifei Wang [Fri, 23 Jul 2021 03:10:49 +0000 (11:10 +0800)]
net/i40e: reduce L1 cache misses in NEON Rx

For N1 platform, packet mbuf load and descs load are hot spots to limit
the performance for "desc_to_ptype_v" and "desc_to_olflags_v" functions
in i40e rx NEON path. This is because packet mbuf and descs are evicted
from l1d-cache to l2d-cache.

To reduce l1d-cache-misses and improve the performance, change the code
order and move "desc_to_ptype_v" and "desc_to_olflags_v" functions
forward to the location, where packet mbuf and descs are just loaded.

Test Result:
dpdk:21.08-rc1
gcc-9
For n1sdp, the patch improves the performance by 1.8%.
For thunderx2, no performance changes.

Signed-off-by: Feifei Wang <feifei.wang2@arm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
3 years agonet/i40e: increase readability in NEON Rx
Feifei Wang [Fri, 23 Jul 2021 03:10:48 +0000 (11:10 +0800)]
net/i40e: increase readability in NEON Rx

Rearrange the code in logical order for better readability and
maintenance convenience in Rx NEON path.

No performance change with this patch in arm platform.

Suggested-by: Joyce Kong <joyce.kong@arm.com>
Signed-off-by: Feifei Wang <feifei.wang2@arm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
3 years agodrivers/net: fix vector Rx comments
Feifei Wang [Fri, 23 Jul 2021 03:10:47 +0000 (11:10 +0800)]
drivers/net: fix vector Rx comments

For the loop to process packets in Rx vector path, some notes for the
code are wrong, fix these errors.

Fixes: 7092be8437bd ("fm10k: add vector Rx")
Fixes: c3def6a8724c ("net/i40e: implement vector PMD for altivec")
Fixes: ae0eb310f253 ("net/i40e: implement vector PMD for ARM")
Fixes: 9ed94e5bb04e ("i40e: add vector Rx")
Fixes: 319c421f3890 ("net/avf: enable SSE Rx Tx")
Fixes: 1162f5a0ef31 ("net/iavf: support flexible Rx descriptor in SSE path")
Fixes: c68a52b8b38c ("net/ice: support vector SSE in Rx")
Fixes: cf4b4708a88a ("ixgbe: improve slow-path perf with vector scattered Rx")
Cc: stable@dpdk.org
Suggested-by: Ruifeng Wang <ruifeng.wang@arm.com>
Signed-off-by: Feifei Wang <feifei.wang2@arm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
3 years agodrivers/net: fix typo in vector Rx comment
Feifei Wang [Fri, 23 Jul 2021 03:10:46 +0000 (11:10 +0800)]
drivers/net: fix typo in vector Rx comment

In Rx vec path, for extracting and recording EOP bit, comment has
redundant "count" word, removing it.

Fixes: 7092be8437bd ("fm10k: add vector Rx")
Fixes: c3def6a8724c ("net/i40e: implement vector PMD for altivec")
Fixes: ae0eb310f253 ("net/i40e: implement vector PMD for ARM")
Fixes: 9ed94e5bb04e ("i40e: add vector Rx")
Fixes: 319c421f3890 ("net/avf: enable SSE Rx Tx")
Fixes: 1162f5a0ef31 ("net/iavf: support flexible Rx descriptor in SSE path")
Fixes: c68a52b8b38c ("net/ice: support vector SSE in Rx")
Fixes: cf4b4708a88a ("ixgbe: improve slow-path perf with vector scattered Rx")
Cc: stable@dpdk.org
Signed-off-by: Feifei Wang <feifei.wang2@arm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
3 years agobuild: fix install from any directory with Meson 0.55
Dmitry Kozlyuk [Tue, 10 Aug 2021 23:03:22 +0000 (02:03 +0300)]
build: fix install from any directory with Meson 0.55

Install command on Windows for Meson >= 0.55.0 referenced the script
by a plain string, assuming the build directory to be directly under
the source tree root.
This resulted in an error when the assumption did not hold:

    c:\python\python.exe: can't open file
    '../buildtools/symlink-drivers-solibs.py':
    [Errno 2] No such file or directory

Use files() to make a valid script path for any build directory.

Fixes: cd27047dbee1 ("build: support drivers symlink on Windows")
Cc: stable@dpdk.org
Signed-off-by: Dmitry Kozlyuk <dmitry.kozliuk@gmail.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Nick Connolly <nick.connolly@mayadata.io>
3 years agodrivers: remove warning with Meson 0.59
Jerin Jacob [Fri, 30 Jul 2021 07:35:48 +0000 (13:05 +0530)]
drivers: remove warning with Meson 0.59

Since meson 0.59.0 version, the extract_all_objects() API
need to pass explicit boolean value.

To remove the following warning[1], added explicit `true` for
extract_all_objects() use in codebase whever there is
no argument.

[1]
WARNING: extract_all_objects called without setting recursive
keyword argument. Meson currently defaults to
non-recursive to maintain backward compatibility but
the default will be changed in the future.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
3 years agoexamples/performance-thread: fix build with clang 12.0.1
Jerin Jacob [Mon, 16 Aug 2021 13:19:14 +0000 (18:49 +0530)]
examples/performance-thread: fix build with clang 12.0.1

In clang 12.0.1 version, the use of pthread_yield() is deprecated,
use sched_yield() instead.

log:
    examples/performance-thread/pthread_shim/main.c:75:9: warning:
    'pthread_yield' is deprecated: pthread_yield is deprecated,
    use sched_yield instead [-Wdeprecated-declarations]

Bugzilla ID: 745
Fixes: 433ba6228f9a ("examples/performance-thread: add pthread_shim app")
Cc: stable@dpdk.org
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Tested-by: Ali Alnubani <alialnu@nvidia.com>
3 years agoversion: 21.11-rc0
Thomas Monjalon [Sun, 8 Aug 2021 19:26:58 +0000 (21:26 +0200)]
version: 21.11-rc0

Start a new release cycle with empty release notes.

The ABI version becomes 22.0.
The map files are updated to the new ABI major number (22).
The ABI exceptions are dropped and CI ABI checks are disabled because
compatibility is not preserved.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Ferruh Yigit <ferruh.yigit@intel.com>
Acked-by: David Marchand <david.marchand@redhat.com>
3 years agoversion: 21.08.0
Thomas Monjalon [Sun, 8 Aug 2021 15:23:21 +0000 (17:23 +0200)]
version: 21.08.0

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
3 years agodoc: announce changes in IPsec xform structure
Radu Nicolau [Thu, 5 Aug 2021 10:20:55 +0000 (11:20 +0100)]
doc: announce changes in IPsec xform structure

Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
3 years agodoc: announce change in IPsec SA structure
Radu Nicolau [Thu, 5 Aug 2021 10:20:54 +0000 (11:20 +0100)]
doc: announce change in IPsec SA structure

Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
3 years agodoc: announce hiding crypto session structures
Akhil Goyal [Tue, 3 Aug 2021 12:01:12 +0000 (17:31 +0530)]
doc: announce hiding crypto session structures

The structures rte_cryptodev_sym_session and
rte_cryptodev_asym_session are not used by the
application directly. The application just need
an opaque pointer which it can attach to rte_crypto_op
while enqueue.
Hence, these structures can be internal to library
hidden from the user.

Signed-off-by: Akhil Goyal <gakhil@marvell.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agodoc: announce clarification of implicit filter by port
Andrew Rybchenko [Mon, 2 Aug 2021 19:57:23 +0000 (22:57 +0300)]
doc: announce clarification of implicit filter by port

Transfer flow rules may be applied to traffic entering switch from
many sources. There are flow API pattern items which allow to specify
ingress port match criteria explicitly, but it is not documented
if ethdev port used to create flow rule adds any implicit match
criteria and how it coexists with explicit ones.

These aspects should be documented and drivers and applications
which use it in a different way must be fixed.

Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Acked-by: Ori Kam <orika@nvidia.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
3 years agodoc: announce change in ethdev flow action port ID
Andrew Rybchenko [Mon, 2 Aug 2021 19:57:22 +0000 (22:57 +0300)]
doc: announce change in ethdev flow action port ID

By its very name, action PORT_ID means that packets hit an ethdev with the
given DPDK port ID. At least the current comments don't state the opposite.

However some drivers implement it in a different way and direct traffic to
the opposite end of the "wire" plugged to the given ethdev. For example in
the case of a VF representor traffic is redirected to the corresponding VF
itself rather than to the representor ethdev and OvS uses PORT_ID action
this way.

The documentation must be clarified and, likely, rte_flow_action_port_id
structure should be extended to support both meanings.

Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Acked-by: Ori Kam <orika@nvidia.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
3 years agodoc: announce moving ethdev actions to general modify
Ori Kam [Tue, 3 Aug 2021 08:57:54 +0000 (11:57 +0300)]
doc: announce moving ethdev actions to general modify

Currently there is a dedicated modify action for each
packet field that the application wants to change.
For example:
RTE_FLOW_ACTION_TYPE_SET_IPV4_DST to modify destination of IPv4.

A new action RTE_FLOW_ACTION_TYPE_MODIFY_FIELD added the ability
to use the same action to modify any field, in addition to be able to
modify the value based on different field and not just immediate value.

Signed-off-by: Ori Kam <orika@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
3 years agodoc: announce change to ethdev modify action data
Ori Kam [Tue, 3 Aug 2021 08:57:53 +0000 (11:57 +0300)]
doc: announce change to ethdev modify action data

In the current implementation,
the action rte_flow_action_modify_field is not well defined
for fields larger than 64 bits (for example IPv6 source)
In addition, the byte order is also not well defined.

Both of those issue should be fixed.

Signed-off-by: Ori Kam <orika@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Acked-by: Jerin Jacob <jerinj@marvell.com>
3 years agodoc: announce ethdev flag and field for shared queue
Xueming Li [Mon, 2 Aug 2021 13:10:55 +0000 (16:10 +0300)]
doc: announce ethdev flag and field for shared queue

To support shared Rx queue, this patch announces new offload flag
RTE_ETH_RX_OFFLOAD_SHARED_RXQ and new shared_group field to struct
rte_eth_rxconf in DPDK v21.11.

[1] mail list discussion:
https://mails.dpdk.org/archives/dev/2021-July/215575.html

Signed-off-by: Xueming Li <xuemingl@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Acked-by: Jerin Jacob <jerinj@marvell.com>
3 years agodoc: announce renaming of vhost operations struct
Maxime Coquelin [Fri, 30 Jul 2021 08:12:30 +0000 (10:12 +0200)]
doc: announce renaming of vhost operations struct

This patch announces the renaming of struct
vhost_device_ops to rte_vhost_device_ops in DPDK v21.11.

Signed-off-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Acked-by: Chenbo Xia <chenbo.xia@intel.com>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Acked-by: Adrian Moreno <amorenoz@redhat.com>
Acked-by: Marvin Liu <yong.liu@intel.com>
3 years agodoc: announce marking vDPA driver interface as internal
Maxime Coquelin [Fri, 30 Jul 2021 08:12:29 +0000 (10:12 +0200)]
doc: announce marking vDPA driver interface as internal

This patch announces the marking of all the vDPA driver APIs
as internal.

Signed-off-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Acked-by: Chenbo Xia <chenbo.xia@intel.com>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Acked-by: Marvin Liu <yong.liu@intel.com>
3 years agodoc: announce promoting some vhost API to stable
Chenbo Xia [Fri, 30 Jul 2021 08:19:25 +0000 (16:19 +0800)]
doc: announce promoting some vhost API to stable

This patch announces the experimental tag removal of 10 vhost APIs,
which have been experimental for more than 2 years.
All APIs could be made stable in DPDK 21.11.

Signed-off-by: Chenbo Xia <chenbo.xia@intel.com>
Acked-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
Acked-by: Marvin Liu <yong.liu@intel.com>
3 years agodoc: announce changes in IPsec SA config option struct
Archana Muniganti [Sat, 31 Jul 2021 17:44:28 +0000 (23:14 +0530)]
doc: announce changes in IPsec SA config option struct

Propose new fields to support offloads like
- IPsec inner checksum(L3/L4)
- IPsec tunnel header verification
- TSO
- etc
in the structure ``rte_security_ipsec_sa_options``.

Signed-off-by: Archana Muniganti <marchana@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Acked-by: Radu Nicolau <radu.nicolau@intel.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
3 years agodoc: announce changes in IPsec xform struct
Anoob Joseph [Tue, 3 Aug 2021 06:48:37 +0000 (12:18 +0530)]
doc: announce changes in IPsec xform struct

IPsec xform struct would be updated to include IPsec SA lifetime
configuration. The existing member 'esn_soft_limit' would only track
ESN. And as sequence number control is getting introduced,
'esn_soft_limit' may not indicate the number of packets processed.
Replace that with a new structure to cover all lifetime cases with
support for specifying both soft and hard lifetimes.

ESN control introduced by https://patches.dpdk.org/patch/95808/

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
3 years agodoc: announce changes in security session struct
Akhil Goyal [Tue, 3 Aug 2021 12:23:35 +0000 (17:53 +0530)]
doc: announce changes in security session struct

The structure rte_security_session is not directly used
by the application. The application just need an opaque
pointer to attached to the mbuf or rte_crypto_op while
enqueue. Hence, it can be hidden inside the library
and would prevent unnecessary indirection to the priv
session data in fastpath.

Signed-off-by: Akhil Goyal <gakhil@marvell.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
3 years agodoc: announce changes in crypto raw data vector
Hemant Agrawal [Thu, 5 Aug 2021 13:55:29 +0000 (19:25 +0530)]
doc: announce changes in crypto raw data vector

The current crypto raw data vectors need to be extended to support
out of place processing. It is proposed to add additional desl_sgl
to provide details for destination sgl.
The same is also extended to support rte_security usecases, where
we need total data length to know how much additional memory space
is available in buffer other than data length so that driver/HW
can write expanded size data after encryption.

Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
3 years agodoc: announce change in crypto adapter metadata
Shijith Thotton [Wed, 4 Aug 2021 18:14:20 +0000 (23:44 +0530)]
doc: announce change in crypto adapter metadata

In crypto adapter metadata, first 8 bytes of request info is a space
holder for response info. For better clarity, reserved field should be
removed from request info. New space for response info can be made by
changing type of event crypto metadata to structure from union.

Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
Acked-by: Jerin Jacob <jerinj@marvell.com>
3 years agodoc: announce removal of lcore state finished
Honnappa Nagarahalli [Fri, 30 Jul 2021 19:59:12 +0000 (14:59 -0500)]
doc: announce removal of lcore state finished

Lcore state FINISHED is used by the worker thread to indicate that
it has completed the assigned task. The state is changed to
WAIT by another thread after it observes the updated state. This
additional step is redundant. After this deprecation, the worker
thread will update the state to WAIT.

Signed-off-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
Acked-by: Feifei Wang <feifei.wang2@arm.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
3 years agodoc: update release notes for 21.08
John McNamara [Thu, 5 Aug 2021 21:57:13 +0000 (21:57 +0000)]
doc: update release notes for 21.08

Fix grammar, spelling and formatting of DPDK 21.08 release notes.

Signed-off-by: John McNamara <john.mcnamara@intel.com>
3 years agodoc: add known issue with mbuf segment
Thomas Monjalon [Wed, 4 Aug 2021 13:29:52 +0000 (15:29 +0200)]
doc: add known issue with mbuf segment

A bug with segmented packets has been discovered but the agreement
to apply the fix is not concluded at the time of DPDK 21.08 release.
This bug seems to be in DPDK for many years and should be fixed in 21.11.

Suggested-by: Olivier Matz <olivier.matz@6wind.com>
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Acked-by: Morten Brørup <mb@smartsharesystems.com>
3 years agodoc: announce changes to eventdev library
Pavan Nikhilesh [Mon, 2 Aug 2021 21:09:48 +0000 (02:39 +0530)]
doc: announce changes to eventdev library

Make driver layer as internal, remove unnecessary rte_ prefix for
structures and functions that are not a part of public API.
Promote experimental trace and vector APIs to stable.
Add reserved field to `rte_event_timer` structure.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>
Acked-by: Jay Jayatheerthan <jay.jayatheerthan@intel.com>
Acked-by: Abhinandan Gujjar <abhinandan.gujjar@intel.com>
3 years agonet/mlx5: fix build on Windows
Gregory Etelson [Thu, 5 Aug 2021 09:55:03 +0000 (12:55 +0300)]
net/mlx5: fix build on Windows

mlx5_dev_check_sibling_config() API was updated to allow newly
spawned port locate existing sibling devices.
PMD port initialization for Windows OS was not updated
for the new API prototype:

drivers/net/mlx5/windows/mlx5_os.c:457:50: error:
too few arguments to function call, expected 3, have 2
err = mlx5_dev_check_sibling_config(priv, config);

The patch fixes mlx5_dev_check_sibling_config call for Windows OS.

Fixes: e9d420dfc2d0 ("net/mlx5: fix find sibling devices")

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
3 years agoversion: 21.08-rc4
Thomas Monjalon [Wed, 4 Aug 2021 16:49:16 +0000 (18:49 +0200)]
version: 21.08-rc4

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
3 years agodoc: announce cryptodev operation struct changes
Anoob Joseph [Mon, 2 Aug 2021 11:11:24 +0000 (16:41 +0530)]
doc: announce cryptodev operation struct changes

One reserved byte in rte_crypto_op struct would be used to indicate
warnings and other information from the crypto/security operation. This
field will be used to communicate events such as soft expiry with IPsec
in lookaside mode.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
3 years agodoc: announce cryptodev driver interface as internal
Akhil Goyal [Tue, 3 Aug 2021 11:44:46 +0000 (17:14 +0530)]
doc: announce cryptodev driver interface as internal

The APIs which are internal to PMD and cryptodev library
can be marked as internal so that ABI checking do not
shout for changes in interfaces which are internal to DPDK.

Signed-off-by: Akhil Goyal <gakhil@marvell.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
3 years agonet: announce changes in IPv4 header access
Gregory Etelson [Mon, 2 Aug 2021 10:38:34 +0000 (13:38 +0300)]
net: announce changes in IPv4 header access

Announce changes to add 2 unions.
The first union will provide integral and bits access to version and IHL.
The second union will provide integral and bits access to fragment flags
and offset.

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
3 years agodoc: announce hiding interrupt handle structure
Harman Kalra [Mon, 2 Aug 2021 16:03:52 +0000 (21:33 +0530)]
doc: announce hiding interrupt handle structure

Moving struct rte_intr_handle as an internal structure to
avoid any ABI breakages in future. Since this structure defines
some static arrays and changing respective macros breaks the ABI.
Eg:
Currently RTE_MAX_RXTX_INTR_VEC_ID imposes a limit of maximum 512
MSI-X interrupts that can be defined for a PCI device, while PCI
specification allows maximum 2048 MSI-X interrupts that can be used.
If some PCI device requires more than 512 vectors, either change the
RTE_MAX_RXTX_INTR_VEC_ID limit or dynamically allocate based on
PCI device MSI-X size on probe time. Either way its an ABI breakage.

Discussion thread:
https://mails.dpdk.org/archives/dev/2021-March/202959.html

Signed-off-by: Harman Kalra <hkalra@marvell.com>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Acked-by: Chenbo Xia <chenbo.xia@intel.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
3 years agodoc: announce renaming of mbuf offload flags
Olivier Matz [Fri, 30 Jul 2021 15:57:01 +0000 (17:57 +0200)]
doc: announce renaming of mbuf offload flags

The mbuf offload flags do not match the DPDK namespace (they are
not prefixed by RTE_). Announce their rename in 21.11, and the
removal of the old names in 22.11.

A draft coccinelle script is provided to anticipate what the
renaming will be.

Signed-off-by: Olivier Matz <olivier.matz@6wind.com>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
3 years agodoc: add tested platforms with Mellanox NICs
Raslan Darawsheh [Wed, 4 Aug 2021 12:54:47 +0000 (15:54 +0300)]
doc: add tested platforms with Mellanox NICs

Add tested platforms with Mellanox NICs to the 21.08 release notes.

Signed-off-by: Raslan Darawsheh <rasland@nvidia.com>
3 years agodoc: add tested Intel platforms with Intel NICs
Yan Xia [Wed, 4 Aug 2021 14:20:24 +0000 (14:20 +0000)]
doc: add tested Intel platforms with Intel NICs

Add tested Intel platforms with Intel NICs to v21.08 release note.

Signed-off-by: Yan Xia <yanx.xia@intel.com>
3 years agopipeline: fix table statistics
Churchill Khangar [Mon, 2 Aug 2021 05:32:12 +0000 (11:02 +0530)]
pipeline: fix table statistics

This patch fixes the memcpy function call which was incorrect and led
to memory corruption for tables with more that just a few actions.

Fixes: 742b0a57f50e4 ("pipeline: add table statistics to SWX")
Cc: stable@dpdk.org
Signed-off-by: Churchill Khangar <churchill.khangar@intel.com>
Acked-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
3 years agodoc: add policy for promotion of experimental API
Ray Kinsella [Wed, 4 Aug 2021 09:34:31 +0000 (10:34 +0100)]
doc: add policy for promotion of experimental API

Clarifying the ABI policy on the promotion of experimental APIs to stable.
We have a fair number of APIs that have been experimental for more than
2 years. This policy amendment indicates that these APIs should be
promoted or removed, or should at least form a conversation between the
maintainer and original contributor.

Signed-off-by: Ray Kinsella <mdr@ashroe.eu>
Acked-by: Tyler Retzlaff <roretzla@linux.microsoft.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
3 years agodoc: update offload information for metering
Jiawei Wang [Tue, 3 Aug 2021 13:02:54 +0000 (16:02 +0300)]
doc: update offload information for metering

Update the Minimal SW and HW version offload support
information for ASO metering and metering hierarchy.

Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
Acked-by: Asaf Penso <asafp@nvidia.com>
3 years agodoc: limit FW support for mlx5 regex driver
Ori Kam [Tue, 3 Aug 2021 19:07:49 +0000 (22:07 +0300)]
doc: limit FW support for mlx5 regex driver

MLX5 RegEx is only supported with FW version XX.30.1004 or lower.

Signed-off-by: Ori Kam <orika@nvidia.com>
Acked-by: Asaf Penso <asafp@nvidia.com>
3 years agoapp/testpmd: fix IPv4 checksum
Gregory Etelson [Mon, 2 Aug 2021 18:13:16 +0000 (21:13 +0300)]
app/testpmd: fix IPv4 checksum

UDP protocol reserves 0 checksum value for special purposes.
Other protocols, like IPv4, TCP and SCTP must calculate checksum value
in software or offload checksum calculation to hardware.

If IPv4 TX checksum offload was off and header checksum was set to 0,
testpmd csum engine did not calculate checksum value for IPv4, TCP and
SCTP.

The patch always calculates IPv4, TCP and SCTP TX checksums if it is
not offloaded.

Bugzilla ID: 768
Fixes: b2a9e4a855d0 ("app/testpmd: fix Tx checksum calculation for tunnel")
Cc: stable@dpdk.org
Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
3 years agobus: clarify log for non-NUMA-aware devices
Dmitry Kozlyuk [Wed, 4 Aug 2021 08:03:01 +0000 (11:03 +0300)]
bus: clarify log for non-NUMA-aware devices

PCI, vmbus, and auxiliary drivers printed a warning
when NUMA node had been reported as (-1) or not reported by OS:

    EAL:   Invalid NUMA socket, default to 0

This message and its level might confuse users because the configuration
is valid and nothing happens that requires attention or intervention.
It was also printed without the device identification and with an indent
(PCI only), which is confusing unless DEBUG logging is on to print
the header message with the device name.

Reduce level to INFO, reword the message, and suppress it when there is
only one NUMA node because NUMA awareness does not matter in this case.
Also, remove the indent for PCI.

Fixes: f0e0e86aa35d ("pci: move NUMA node check from scan to probe")
Fixes: 831dba47bd36 ("bus/vmbus: add Hyper-V virtual bus support")
Fixes: 1afce3086cf4 ("bus/auxiliary: introduce auxiliary bus")
Cc: stable@dpdk.org
Signed-off-by: Dmitry Kozlyuk <dkozlyuk@nvidia.com>
Reviewed-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Reviewed-by: Xueming Li <xuemingl@nvidia.com>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
3 years agonet/mlx5: fix find sibling devices
Gregory Etelson [Tue, 3 Aug 2021 15:06:58 +0000 (18:06 +0300)]
net/mlx5: fix find sibling devices

The routine mlx5_eth_find_next() and related iterating macro
MLX5_ETH_FOREACH_DEV is used to iterate through sibling devices (all
representors share the same configuration and switching domain) on top
of specified root device.

The root device parameter was specified as NULL, and it caused
missing siblings in iteration during representor device probing,
causing:

1. allocating new domain_id for the device being probed.
2. discrepancy in representor configurations and potential overall
   driver malfunctions.

Fixes: 56bb3c84e982 ("net/mlx5: reduce PCI dependency")

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
3 years agonet/mlx5: fix domains detection in meter hierarchy
Shun Hao [Wed, 4 Aug 2021 07:26:47 +0000 (10:26 +0300)]
net/mlx5: fix domains detection in meter hierarchy

Meters in one hierarchy might support different domains. For
example, one meter may support ingress only, but the root meter
can support all the domains.

If the later meter in the meter hierarchy wrongly doesn't inherit
the first meter's domains, it will lead to invalid domain table
access.

Fix is when creating meter hierarchy, try to inherit the first meter
domains in the meter hierarchy.

Fixes: a3b7af90baba ("net/mlx5: validate meter action in policy")
Cc: stable@dpdk.org
Signed-off-by: Shun Hao <shunh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: fix meter flow counter translation
Shun Hao [Wed, 4 Aug 2021 07:26:46 +0000 (10:26 +0300)]
net/mlx5: fix meter flow counter translation

When a flow rule uses a meter without any modify packet action,
there will be an internal drop flow with meter counter created,
matching the same 5-tuple as the original flow.

In this case, the meter flow count action is wrongly reused as the
original flow counter, leading to wrong flow statistics.

Add a check in the count action translation to detect the meter case
and use the meter drop dedicated counter in the meter 5-tuple flow
only.

Fixes: f3191849f2c2 ("net/mlx5: support flow count action handle")
Cc: stable@dpdk.org
Signed-off-by: Shun Hao <shunh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: workaround drop action with old kernel
Suanming Mou [Mon, 2 Aug 2021 14:30:24 +0000 (17:30 +0300)]
net/mlx5: workaround drop action with old kernel

Currently, there are two types of drop action implementation
in the PMD. One is the DR (Direct Rules) dummy placeholder drop
action and another is the dedicated dummy queue drop action.
When creates flow on the root table with DR drop action, the
action will be converted to MLX5_IB_ATTR_CREATE_FLOW_FLAGS_DROP
Verbs attribute in rdma-core.

In some inbox systems, MLX5_IB_ATTR_CREATE_FLOW_FLAGS_DROP Verbs
attribute may not be supported in the kernel driver. Create flow
with drop action on the root table will be failed as it is not
supported. In this case, the dummy queue drop action should be
used instead of DR dummy placeholder drop action.

This commit adds the DR drop action support detect on the root
table. If MLX5_IB_ATTR_CREATE_FLOW_FLAGS_DROP Verbs is not
supported in the system, a dummy queue will be used as drop
action.

Fixes: da845ae9d7c1 ("net/mlx5: fix drop action for Direct Rules/Verbs")
Cc: stable@dpdk.org
Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: fix VXLAN VNI matching on ConnectX-5
Rongwei Liu [Mon, 2 Aug 2021 12:20:48 +0000 (15:20 +0300)]
net/mlx5: fix VXLAN VNI matching on ConnectX-5

In the recent update, the misc5 matcher was introduced to
match VxLAN header extra fields. However, ConnectX-5
doesn't support misc5 for the UDP ports different from
VXLAN's standard one (4789).

Need to fall back to the previous approach and use legacy
misc matcher if non-standard UDP port is recognized
in VxLAN flow.

Fixes: 630a587bfb37 ("net/mlx5: support matching on VXLAN reserved field")
Cc: stable@dpdk.org
Signed-off-by: Rongwei Liu <rongweil@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
3 years agonet/mlx5: fix port initialization of switch domain
Gregory Etelson [Mon, 2 Aug 2021 14:55:24 +0000 (17:55 +0300)]
net/mlx5: fix port initialization of switch domain

All active ports that belong to the same E-switch share domain_id
value.
Port initialization procedure searches through a database for existing
port with matching properties. New domain_id allocated if match was
not located. Otherwise, new port inherits existing domain_id.

Port initialization did not pass enough info to search procedure to
find existing matches. Therefore, each port was created with a private
domain_id value. As the result, port_id flow action failed because it
could not match ports in a rule to E-switch.

The patch adds dpdk_dev with port properties to device search.

Fixes: 56bb3c84e982 ("net/mlx5: reduce PCI dependency")

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
3 years agocompress/mlx5: fix compression level translation
Raja Zidane [Thu, 29 Jul 2021 14:11:08 +0000 (17:11 +0300)]
compress/mlx5: fix compression level translation

Compression Level is interpreted by each PMD differently.
However, lower numbers give faster compression
at the expense of compression ratio, while higher numbers
may give better compression ratios but are likely slower.
The level affects the block size, which affects performance,
the bigger the block, the faster the compression is.

The problem was that higher levels caused bigger blocks:
  size = min_block_size - 1 + level.

the solution is to reverse the above:
  size = max_block_size + 1 - level.

Fixes: 39a2c8715f8f ("compress/mlx5: add transformation operations")
Cc: stable@dpdk.org
Signed-off-by: Raja Zidane <rzidane@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agodoc: update matching versions in ice guide
Qi Zhang [Thu, 22 Jul 2021 01:51:01 +0000 (09:51 +0800)]
doc: update matching versions in ice guide

Add recommended matching list for ice PMD in DPDK 21.08.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
3 years agonet/bnxt: fix number of action records
Ajit Khaparde [Sat, 31 Jul 2021 04:39:21 +0000 (21:39 -0700)]
net/bnxt: fix number of action records

For Thor, the number of action records is being wrongly configured
to 128 because of incorrect definition of divider. This results in
an incorrect number of action records being negotiated with the FW.
Remove the divider from the templates and delete the logic which
uses the field in the resource manager logic.

Fixes: 3fe124d2536c ("net/bnxt: support Thor platform")
Cc: stable@dpdk.org
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Tested-by: Shuanglin Wang <shuanglin.wang@broadcom.com>
3 years agodoc: announce API changes for Windows compatibility
Dmitry Kozlyuk [Wed, 21 Jul 2021 19:55:57 +0000 (22:55 +0300)]
doc: announce API changes for Windows compatibility

Windows headers define `s_addr`, `min`, and `max` as macros.
If DPDK headers are included after Windows ones, DPDK structure
definitions containing fields with these names get broken (example 1),
as well as any usage of such fields (example 2). If DPDK headers
undefined these macros, it could break consumer code (example 3).
It is proposed to rename structure fields in DPDK, because Win32 headers
are used more widely than DPDK, as a general-purpose platform compared
to domain-specific kit, and are harder to fix because of that.
Exact new names are left for further discussion.

Example 1:

    /* in DPDK public header included after windows.h */
    struct rte_type {
        int min;    /* ERROR: `min` is a macro */
    };

Example 2:

    #include <rte_ether.h>
    #include <winsock2.h>
    struct rte_ether_hdr eh;
    eh.s_addr.addr_bytes[0] = 0;    /* ERROR: `addr_s` is a macro */

Example 3:

    #include <winsock2.h>
    #include <rte_ether.h>
    struct in_addr addr;
    addr.s_addr = 0;      /* ERROR: there is no `s_addr` field,
                             and `s_addr` macro is undefined by DPDK. */

Commit 6c068dbd9fea ("net: work around s_addr macro on Windows")
modified definition of `struct rte_ether_hdr` to avoid the issue.
However, the workaround assumes `#define s_addr S_addr.S_un`
in Windows headers, which is not a part of official API.
It also complicates the definition of `struct rte_ether_hdr`.

Signed-off-by: Dmitry Kozlyuk <dmitry.kozliuk@gmail.com>
Acked-by: Khoa To <khot@microsoft.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agodoc: announce extension of crypto data-unit length
Thomas Monjalon [Wed, 14 Apr 2021 20:15:43 +0000 (22:15 +0200)]
doc: announce extension of crypto data-unit length

The struct member dataunit_len is introduced in DPDK 21.05.
It is limited to 16 bits to fit a padding hole in 32-bit build.
This means the maximum data-unit length is 64 KB.
Some use cases may benefit of a bigger size as the proposed 32 bits.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agotest: quieten warning noise while forking
John Levon [Sun, 1 Aug 2021 17:53:25 +0000 (18:53 +0100)]
test: quieten warning noise while forking

When closing file descriptors post-fork, ignore "." and ".." directory
entries, so the test log doesn't have distracting errors like:

Error converting name fd 0 .:
Error converting name fd 0 ..:

Signed-off-by: John Levon <john.levon@nutanix.com>
3 years agoversion: 21.08-rc3
Thomas Monjalon [Sat, 31 Jul 2021 21:12:34 +0000 (23:12 +0200)]
version: 21.08-rc3

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
3 years agodoc: announce common prefix for ethdev
Ferruh Yigit [Wed, 30 Jun 2021 09:21:16 +0000 (10:21 +0100)]
doc: announce common prefix for ethdev

Announce adding 'RTE_ETH_' prefix to all public ethdev macros/enums on
v21.11.
Backward compatibility macros will be added on v21.11 and they will be
removed on v22.11.

Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Acked-by: Raslan Darawsheh <rasland@nvidia.com>
Acked-by: Tyler Retzlaff <roretzla@linux.microsoft.com>
3 years agodoc: announce removal of PCI bus ABI
Chenbo Xia [Tue, 1 Jun 2021 08:41:31 +0000 (16:41 +0800)]
doc: announce removal of PCI bus ABI

All ABIs in PCI bus driver, which are defined in rte_buc_pci.h,
will be removed and the header will be made internal.

Signed-off-by: Chenbo Xia <chenbo.xia@intel.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Ferruh Yigit <ferruh.yigit@intel.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
3 years agodoc: update atomic operation deprecation
Joyce Kong [Fri, 23 Jul 2021 09:49:43 +0000 (04:49 -0500)]
doc: update atomic operation deprecation

Update the incorrect description about atomic operations
with provided wrappers in deprecation doc[1].

[1]https://mails.dpdk.org/archives/dev/2021-July/213333.html

Fixes: 7518c5c4ae6a ("doc: announce adoption of C11 atomic operations semantics")
Cc: stable@dpdk.org
Signed-off-by: Joyce Kong <joyce.kong@arm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
3 years agodoc: remove old deprecation notice for sched
Jasvinder Singh [Mon, 14 Jun 2021 16:30:00 +0000 (17:30 +0100)]
doc: remove old deprecation notice for sched

APIs and data structures hasve been modified as per deprecation
note, so removing deprecation notice from the notes.

Fixes: 85f52aa422d6 ("sched: add pipe config params to subport struct")
Cc: stable@dpdk.org
Signed-off-by: Jasvinder Singh <jasvinder.singh@intel.com>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
3 years agotest: flush stdout after forking
John Levon [Mon, 26 Jul 2021 12:16:27 +0000 (13:16 +0100)]
test: flush stdout after forking

meson test was not capturing the intended output from the child
process; force a flush to ensure it reaches the test log.

Signed-off-by: John Levon <john.levon@nutanix.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
3 years agodoc: add Arm PMU build option in profiling guide
Jerin Jacob [Sun, 11 Jul 2021 07:58:21 +0000 (13:28 +0530)]
doc: add Arm PMU build option in profiling guide

Documented the role of RTE_ARM_EAL_RDTSC_USE_PMU to enable
PMU based rte_rdtsc().

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Ruifeng Wang <ruifeng.wang@arm.com>
3 years agodoc: fix spelling
Henry Nadeau [Thu, 29 Jul 2021 16:48:05 +0000 (12:48 -0400)]
doc: fix spelling

Spell checked and corrected documentation.
If there are any errors, or I have changed something that wasn't an error
please reach out to me so I can update the dictionary.

Cc: stable@dpdk.org
Signed-off-by: Henry Nadeau <hnadeau@iol.unh.edu>
3 years agodoc: use code snippets in sample app guides
Conor Fogarty [Fri, 16 Jul 2021 13:57:52 +0000 (13:57 +0000)]
doc: use code snippets in sample app guides

Currently the sample app user guides use hard coded code snippets,
this patch changes these to use literalinclude which will dynamically
update the snippets as changes are made to the code.
This was introduced in commit 413c75c33c40 ("doc: show how to include
code in guides"). Comments within the sample apps were updated to
accommodate this as part of this patch. This will help to ensure that
the code within the sample app user guides is up to date and not out
of sync with the actual code.

Signed-off-by: Conor Fogarty <conor.fogarty@intel.com>
Signed-off-by: Conor Walsh <conor.walsh@intel.com>
Acked-by: John McNamara <john.mcnamara@intel.com>
3 years agomaintainers: update for Marvell QLogic
Igor Russkikh [Tue, 27 Jul 2021 08:02:35 +0000 (10:02 +0200)]
maintainers: update for Marvell QLogic

Adding Marvell prefix for qlogic drivers.
Removing myself as I'm no longer responsible for qede driver

Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: Rasesh Mody <rmody@marvell.com>
Acked-by: Devendra Singh Rawat <dsinghrawat@marvell.com>
3 years agomaintainers: update for atlantic
Igor Russkikh [Tue, 27 Jul 2021 08:02:34 +0000 (10:02 +0200)]
maintainers: update for atlantic

Fixing ex-Aquantia email - it is now part of Marvell.
Removing Pavel Belous email - he is not in company now.
Adding Marvell tree to run this through.

Signed-off-by: Igor Russkikh <irusskikh@marvell.com>