vdpa/ifc: support vring update after device config
The device ready state in vhost lib is now defined as the state
that first queue pair is ready. And kick/callfd may be updated
by QEMU when ifc device is configured.
Although now ifc driver only supports one queue pair, it still
has to update callfd when working with QEMU. This patch fixes
this vring update problem by implementing the set_vring_state
callback.
Suggested-by: Maxime Coquelin <maxime.coquelin@redhat.com> Signed-off-by: Chenbo Xia <chenbo.xia@intel.com> Acked-by: Xiao Wang <xiao.w.wang@intel.com> Acked-by: Rosen Xu <rosen.xu@intel.com> Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Xueming Li [Tue, 28 Jul 2020 12:32:29 +0000 (12:32 +0000)]
vdpa/mlx5: fix event queue number query
Vdpa example failed on vq setup, the api to get event queue of specified
core failed.
Internal api devx_query_eqn expects index of event queue vectors, no
need to use cpu id. As the doorbell handling thread is per device, it's
sufficient to use default event queue.
This patch uses the default id(0) as event queue index.
Fixes: 8395927cdfaf ("vdpa/mlx5: prepare HW queues") Cc: stable@dpdk.org Signed-off-by: Xueming Li <xuemingl@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com> Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Xiao Wang [Tue, 28 Jul 2020 06:52:12 +0000 (14:52 +0800)]
net/virtio-user: fix status management
Apart from the virtio status, there should be also a network related
status for link status management, current implementation mixes up these
two statuses.
One issue caused by this mixup is when virtio-user running in server mode
and vhost as a client connects to it, a RARP packet will be generated by
virtio-user due to VIRTIO_NET_S_ANNOUNCE bit is detected in the "status"
in interrupt handler.
VIRTIO_NET_S_LINK_UP and VIRTIO_NET_S_ANNOUNCE should be managed by a
separated field. This patch adds a "net_status" field for this purpose.
Fixes: e9efa4d93821 ("net/virtio-user: add new virtual PCI driver") Cc: stable@dpdk.org Signed-off-by: Adrian Moreno <amorenoz@redhat.com> Signed-off-by: Xiao Wang <xiao.w.wang@intel.com> Reviewed-by: Chenbo Xia <chenbo.xia@intel.com> Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Xueming Li [Mon, 27 Jul 2020 14:29:53 +0000 (14:29 +0000)]
vdpa/mlx5: fix completion queue initialization
Vdpa device failed to initialize 2nd VQ during setup. From FW syndrome,
unsupported CQE size was specified in CQ initialization attributes.
The unsupported CQE size comes from uninitialized stack struct data, and
the struct has new fields defined recently which are not initialized in
vdpa code.
This patch initializes cq creation attributes with zero to avoid such
random data.
Fixes: 79a7e409a2f6 ("common/mlx5: prepare support of packet pacing") Signed-off-by: Xueming Li <xuemingl@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com> Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
The issue is relevant only for the timer event modes: 0 and 1.
When the HW finishes to consume a burst of the guest Rx descriptors,
it creates a CQE in the CQ.
When traffic stops, the mlx5 driver arms the CQ to get a notification
when a specific CQE index is created - the index to be armed is the
next CQE index which should be polled by the driver.
The mlx5 driver configured the kernel driver to send notification to
the guest callfd in the same time of the armed CQE event.
It means that the guest was notified only for each first CQE in a
poll cycle, so if the driver polled CQEs of all the virtio queue
available descriptors, the guest was not notified again for the rest
because there was no any new CQE to trigger the guest notification.
Hence, the Rx queues might be stuck when the guest didn't work with
poll mode.
Remove prior kernel notification, and do manual notification after CQ
polling.
Fixes: a9dd7275a149 ("vdpa/mlx5: optimize notification events") Signed-off-by: Matan Azrad <matan@mellanox.com> Acked-by: Xueming Li <xuemingl@mellanox.com> Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Update the docs, adding MCX621102AN-ADAT to the list of NICs supported
by MLX5 vDPA driver.
Suggested-by: William Tu <u9012063@gmail.com> Signed-off-by: Sergey Madaminov <sergey.madaminov@gmail.com> Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Patrick Fu [Thu, 23 Jul 2020 05:39:06 +0000 (13:39 +0800)]
vhost: fix async callback return type
The async copy device callbacks are used by async APIs to transfer data
and check completion status. Async APIs return the number of packets
successfully processed to the caller applications and no error
(negative) value is allowed for API return value. Thus, negative return
values from async device callbacks don't have meaningful usage, while
adding overhead in checking the return value validity. This patch change
the callback return values from "int" to "uint32_t" to get aligned with
async API definition.
Fixes: 78639d54563a ("vhost: introduce async enqueue registration API") Signed-off-by: Patrick Fu <patrick.fu@intel.com> Reviewed-by: Chenbo Xia <chenbo.xia@intel.com> Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Patrick Fu [Wed, 22 Jul 2020 15:01:52 +0000 (23:01 +0800)]
doc: describe async API in vhost guide
Update vhost guides to document vhost async APIs
Signed-off-by: Patrick Fu <patrick.fu@intel.com> Reviewed-by: Chenbo Xia <chenbo.xia@intel.com> Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
When dynamic flex parser feature is introduced, the support for misc
parameters 4 of flow table entry (FTE) match set is needed. The
structure of "mlx5_ifc_fte_match_param_bits" is extended with
"mlx5_ifc_fte_match_set_misc4_bits" at the end of it. The total size
of the FTE match set will be changed into 384 bytes from 320 bytes.
Low level user space driver (rdma-core) will have the validation of
the length of FTE match set. In the old release that no MISC4
supported in the rdma-core, and this will break the backward
compatibility, even if the MISC4 is not used in most cases, like
in vDPA driver.
In order not to break the compatibility old rdma-core, the length
adjustment needs to be done. In mlx5 vDPA driver, the lengths of
the matcher and value are both set to 320 without MISC4. There is
no need to change the structure definition, all bytes of the MISC4
will be discarded if it is not needed. Since the MISC4 parameter
is aligned with a 64B boundary and so does the whole FTE match set
parameter, there is no need to take any padding and alignment into
consideration when calculating the size.
Mike Baucom [Thu, 23 Jul 2020 11:56:37 +0000 (17:26 +0530)]
net/bnxt: add templates for search before alloc
Search before alloc allows reuse of constrained resources such as tcam,
encap, and source modifications. The new templates will search the
entry and alloc only if necessary.
net/bnxt: fix FW rule deletion on representor create
Truflow stack adds VFR to VF and VF to VFR conduits when VF
representor is created. However, in the ingress direction the
VF's fw rules conflict with Truflow rules, resulting in not hitting
the Truflow VFR rules. To fix this, fw is going to remove it’s
VF rules when vf representor is created in Truflow mode and will
restore the removed rules when vf representor is destroyed.
This patch invokes the vf representor alloc and free hwrm commands
as part of which fw will do the above mentioned actions.
Currently, the flow_ids of port_to_app/app_to_port & tx_cfa_action
for the first port are getting over-written by the second port because
these fields are stored in the ulp context which is common across the
ports.
This patch fixes the problem by having per port structure to store these
fields.
Fixes: 9f702636d7ba ("net/bnxt: add port default rules for ingress and egress") Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com> Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Mike Baucom [Thu, 23 Jul 2020 11:56:32 +0000 (17:26 +0530)]
net/bnxt: modify ULP mapper to use table search
Modified ulp mapper to use the new tf_search_tbl_entry API.
When search before allocation is requested, mapper calls
tc_search_tbl_entry with the alloc flag.
- On HIT, the result and table index is returned.
- On MISS, the table index is returned but the result is
created and the table entry is set.
- On REJECT, the flow request is rejected.
When a packet is looped back from VF to VFR, it is marked to identify
the VFR interface. However, this mark_id shouldn't be percolated up to
the OVS as it is internal to pmd.
This patch fixes it by skipping mark injection into mbuf if the packet
is received on VFR interface.
Fixes: 6dc83230b43b ("net/bnxt: support port representor data path") Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Signed-off-by: Sriharsha Basavapatna <sriharsha.basavapatna@broadcom.com> Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
Mike Baucom [Thu, 23 Jul 2020 11:56:23 +0000 (17:26 +0530)]
net/bnxt: modify ULP mapper to use TCAM search
Modified ulp mapper to use the new tf_search_tcam_entry API.
When search before allocation is requested, mapper calls
tc_search_tcam_entry with the alloc flag.
- On HIT, the result and tcam index is returned.
- On MISS, the tcam index is returned but the result is
created and the tcam entry is set.
- On REJECT, the flow request is rejected.
PARIF is handler to a partition of the physical port.
For the offload miss rules, the parif miss path needs to be
considered. The higher parif are reserved for handling this.
Add support to enable or disable the NAT global registers.
The NAT feature is enabled in hardware during initialization
and disabled at deinitialization of the application.
RXQ interrupts under Linux are based on the epoll mechanism. An
expected order of operations is as follows:
1. Call rte_eth_dev_rx_intr_enable(), to arm the CQ for receiving events
on data input.
2. Block on rte_epoll_wait() with an array of file descriptors
representing the CQ events. Upon data arrival the kernel will signal an
input event on the corresponding CQ fd.
3. Call rte_eth_dev_rx_intr_disable() after the event was received and
continue in polling mode. The mlx4 implementation of
rte_eth_dev_rx_intr_disable() is to get the CQ event and ack it.
In practice applications may wake up from rte_epoll_wait() due to
timeout with no event to ack but still call
rte_eth_dev_rx_intr_disable() unconditionally. In such cases the call
should return EAGAIN (since the file descriptors are non-blocked), as
opposed to EINVAL which indicates a real failure. In case of EAGAIN the
PMD should not warn on "unable to disable interrupt on rx queue".
Xiaoyun Wang [Sat, 25 Jul 2020 08:15:36 +0000 (16:15 +0800)]
net/hinic/base: avoid system time jump
Replace gettimeofday() with clock_gettime(CLOCK_MONOTONIC_RAW, &now),
the reason is same with
commit d08d304508a8 ("eal/linux: make alarm not affected by system time
jump")
Fixes: 81d53291a466 ("net/hinic/base: add various headers") Cc: stable@dpdk.org Signed-off-by: Xiaoyun Wang <cloud.wangxiaoyun@huawei.com>
Xiaoyun Wang [Sat, 25 Jul 2020 08:15:35 +0000 (16:15 +0800)]
net/hinic/base: modify VHD type for SDI
For ovs offload scenario, when fw processes the virtio header,
there is no need to offset; and for standard card scenarios,
fw does not care about the vhd_type parameter, so in order to
be compatible with these two scenarios, use 0 offset instead.
Signed-off-by: Xiaoyun Wang <cloud.wangxiaoyun@huawei.com>
Recent patch added creation of Rx CQ using DevX API.
The reading of events from DevX channel was not done correctly.
This patch fixes the event reading, using the correct data structure.
Cleanup after CQ creation, in case of error, is also updated.
Fixes: 08d1838f645a ("net/mlx5: implement CQ for Rx using DevX API") Signed-off-by: Dekel Peled <dekelp@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
A new symmetric RSS rule may force another asymmetric rule to be
symmetric, vice versa. The reason is due to the flow engine will
try to reuse the existing profile if the input set matches with the
new rule. The fix is to disable this optimization for RSS since we
are not at the situation as profile shortage.
Fixes: ddae0440353f ("net/ice/base: enable symmetric hash for RSS") Cc: stable@dpdk.org Signed-off-by: Qi Zhang <qi.z.zhang@intel.com> Tested-by: Nannan Lu <nannan.lu@intel.com> Acked-by: Jeff Guo <jia.guo@intel.com>
This patch enable i40e outer vlan strip on and off in QinQ
mode with mask bit of DEV_RX_OFFLOAD_QINQ_STRIP, users can
use "vlan set qinq_strip on 0" to enable or "vlan set
qinq_strip off 0" to disable i40e outer vlan strip when
try with testpmd app.
Fixes: 4861cde46116 ("i40e: new poll mode driver") Cc: stable@dpdk.org Signed-off-by: Wei Zhao <wei.zhao1@intel.com> Reviewed-by: Qiming Yang <qiming.yang@intel.com>
The ConnectX NICs can transfer data from the host memory with two
approaches: provide the pointer to the data buffer, or do data inline
- copy the data to the transmit descriptor (WQE) entirely or only the
part of data. In some configurations the NIC hardware requires the
minimal data to be inline in the descriptor to operate correctly. And
there is the special dynamic flag to hint PMD not to inline the data
(for example, if buffer is located on some other device - storage or
GPU) on per packet basis.
If there was a packet with length shorter than the minimal inline data
length requested by the NIC hardware and the no-inline hint was set
the PMD tried to inline the packet with minimal required length
instead of actual packet's one. This patch adds the missed length
check into no-inline hint handling branch.
The User Access Region is a special mechanism to provide direct
access to the hardware registers, and is the part of PCI address
space that is mapped to CPU virtual address. The mapping can be
performed with the type "Write-Combining" or "Non-Cached", and
these ones might be supported or not on different setups.
To prevent device probing failure the UAR allocation attempt
with alternative mapping type is performed. The datapath
takes the actual UAR mapping into account on queue creation.
There was another issue with NULL UAR base address.
OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
UAR base address if UAR was not the first object in the UAR page.
It caused the PMD failure and we should try to get another UAR
till we get the first one with non-NULL base address returned.
Fixes: fc4d4f732bbc ("net/mlx5: introduce shared UAR resource") Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Ori Kam <orika@mellanox.com>
Shougang Wang [Fri, 24 Jul 2020 09:38:34 +0000 (09:38 +0000)]
net/i40e: fix hash lookup table
The hash look up table (LUT) is managed by global register but it is not
initialized when RSS is disabled. Once user wants to enable RSS during
runtime, the LUT will not be initialized.
This patch fixes the issue by initializing the LUT whatever RSS enabled
or not.
Fixes: feaae285b342 ("net/i40e: support hash configuration in RSS flow") Cc: stable@dpdk.org Signed-off-by: Shougang Wang <shougangx.wang@intel.com> Tested-by: Xi Zhang <xix.zhang@intel.com> Acked-by: Jeff Guo <jia.guo@intel.com>
'port_id' storage size should be 'uint16_t', the API
'rte_pmd_dpaa_set_tx_loopback()' has it as 'uint8_t' but fixing it is an
ABI breakage, that is why planning the fix in v20.11 release where ABI
breakage is allowed.
There was an optimization work to prefetch all the CQEs before
their invalidation. It allowed us to speed up the mini-CQE
decompression process by preheating the cache in the vectorized
Rx routine.
Prefetching of the next mini-CQE, on the other hand, showed
no difference in the performance on x86 platform. So, that was
removed. Unfortunately this caused the performance drop on ARM.
Prefetch the mini-CQE as well as all the soon to be
invalidated CQEs to get both CQE and mini-CQE on the hot path.
Fixes: 28a4b96321a3 ("net/mlx5: prefetch CQEs for a faster decompression") Cc: stable@dpdk.org Signed-off-by: Alexander Kozyrev <akozyrev@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Michael Baum [Tue, 21 Jul 2020 12:04:37 +0000 (12:04 +0000)]
net/mlx5: fix unnecessary init in mark conversion
The flow_dv_convert_action_mark function defines an array of
field_modify_info structures and initializes the first entity.
In the first entity id field, it initializes to 0, even though its type
is an enum that has no value of 0.
In fact, the function does not use this id field before assigning the
appropriate register id into it, so the initialization is unnecessary.
Moreover, this initialization is int into enum, and it would be better
not to create a type conflict for no reason.
Wait for the first entity initialization until the appropriate register
id is already known.
Fixes: 55deee1715f0 ("net/mlx5: extend flow mark support") Cc: stable@dpdk.org Signed-off-by: Michael Baum <michaelba@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
Michael Baum [Tue, 21 Jul 2020 12:03:38 +0000 (12:03 +0000)]
net/mlx5: optimize critical section in device free
When PMD releases shared IB device context, It locks the
mlx5_ibv_list_mutex lock throughout the function so that it does not
happen while removing a device from the list, another process will try
to insert another device into it.
On the other hand, having removed the device from the list even if it
has not yet released all of its resources, it should not care about
other processes and can release the lock.
However, the PMD does not release the lock even though it can, and
performs a number of operations, some of which include sleep and may be
long.
To improve this, shorten the lock time to the minimum necessary.
Signed-off-by: Michael Baum <michaelba@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
Michael Baum [Tue, 21 Jul 2020 12:01:09 +0000 (12:01 +0000)]
net/mlx4: optimize stack memory size in probe
The mlx4_pci_probe function sets a pointer to the mlx4_priv structure,
and during that function fills its fields one by one with relevant
values.
It wants to put a value in the intr_handle field that has all its fields
zero except 2. To do so, it initializes a local struct rte_intr_handle
type variable and updates it only 2 fields and assigns it into the
appropriate field. However, it initializes a very large structure on the
stack while not at all certain that this place exists and in any case it
is very wasteful.
Reset all fields directly to the pointer by memset, then format the 2
fields to the relevant values.
Fixes: 63c2f23c852a ("net/mlx4: use a single interrupt handle") Cc: stable@dpdk.org Signed-off-by: Michael Baum <michaelba@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
Michael Baum [Tue, 21 Jul 2020 12:00:04 +0000 (12:00 +0000)]
net/mlx5: remove ineffective increment in hairpin split
The flow_hairpin_split function defines a pointer called addr that
points to the list of items.
When the function wants to progress in the list, it adds the size of an
item to the pointer.
At the end of the function, it precedes the pointer one more time even
though it is not used afterwards. In fact, this line is unaffected and
the operation of the function would have been no different without it.
Remove the line where the pointer is preceded unnecessarily.
Michael Baum [Tue, 21 Jul 2020 11:59:04 +0000 (11:59 +0000)]
net/mlx5: fix crash in NVGRE item translation
The flow_dv_translate_item_nvgre function add NVGRE item to matcher and
to the value.
It defines a pointer named nvrge_m that receives the item's mask into
it, and then copies some of it to the matcher.
Before copying, it checks for mask validation, and in case the mask is
NULL the function gives it a pointer to rte_flow_item_nvgre_mask.
However, the function calls from the vni mask's field before the check,
and if there is no mask, it actually does dereference to the NULL
pointer and indeed the program crashes with segfault.
Move the call from the vni field to post-validation.
Fixes: cd18e1b72f73 ("net/mlx5: fix build on Arm") Cc: stable@dpdk.org Signed-off-by: Michael Baum <michaelba@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
Michael Baum [Tue, 21 Jul 2020 11:57:21 +0000 (11:57 +0000)]
net/mlx5: fix initialization of steering registers
The mlx5_flow_action_copy_mreg structure contains a field called src
type enum modify_reg, similarly the mlx5_rte_flow_item_tag field
contains a field called id type enum modify_reg.
The enum modify_reg variable represents different registers in the
system and it also has a field called REG_NONE whose value is 0 which
means that the register does not exist.
The flow_mreg_add_copy_action function sets a variable of struct
mlx5_flow_action_copy_mreg type, and initializes the src field to be 0.
Similarly the flow_create_split_metadata function sets a variable of
struct mlx5_rte_flow_item_tag type and initializes the id field to be 0.
In both functions, they initialize a enum modify_reg type variable with
an int type value while modify_reg has an appropriate field for that
value (REG_NONE).
Replace assigning 0 with REG_NONE in both functions.
Fixes: dd3c774f6ffb ("net/mlx5: add metadata register copy table") Fixes: 71e254bc0294 ("net/mlx5: split Rx flows to provide metadata copy") Cc: stable@dpdk.org Signed-off-by: Michael Baum <michaelba@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
Currently, the counter query requires the counter ID should start
with 4 aligned. In none-batch mode, the counter pool might have the
chance to get the counter ID not 4 aligned. In this case, the counter
should be skipped, or the query will be failed.
Skip the counter with ID not 4 aligned as the first counter in the
none-batch count pool to avoid invalid counter query. Once having
new min_dcs ID in the poll less than the skipped counters, the
skipped counters will be returned to the pool free list to use.
Currently, when allocate the counter or counter based age from group 0,
counter and age may share the same counter dcs ID range. Both age and
pure counter need to sync up with each other's container to check if
the ID range exists and update the min_dcs.
It comes two disadvantages:
1. If the ID range is shared, this counter range will be queried twice
both from age and pure counter container in 1s.
2. The same range counter check between the two container makes the
counter allocate sync min_dcs time to time with extra min_dcs
updating.
This patch avoid the same ID range to be shared when allocate the new
pool. If the same ID range exists in other container, just add the
counter to the other container until get new range which saves the
min_dcs sync up time to time.
When Rx/Tx queue was being created with DevX the allocated
doorbell record size was only uint64_t. That was definitely
less than size of CPU cacheline and it might have happened the
doorbell records attached to different queues handled by
different cores were allocated within same cacheline. It might
have caused the contention on doorbell record writing.
This patch extends the allocated memory size for doorbell
record to cacheline size.
RXQ interrupts under Linux are based on the epoll mechanism. An expected
order of operations is as follows:
1. Call rte_eth_dev_rx_intr_enable(), to arm the CQ for receiving events
on data input.
2. Block on rte_epoll_wait() with an array of file descriptors
representing the CQ events. Upon data arrival the kernel will signal
an input event on the corresponding CQ fd.
3. Call rte_eth_dev_rx_intr_disable() after the event was received and
continue in polling mode. The mlx5 implementation of
rte_eth_dev_rx_intr_disable() is to get the CQ event and ack it.
In practice applications may wake up from rte_epoll_wait() due to
timeout with no event to ack but still call
rte_eth_dev_rx_intr_disable() unconditionally. In such cases the call
should return EAGAIN (since the file descriptors are non-blocked), as
opposed to EINVAL which indicates a real failure. In case of EAGAIN the
PMD should not warn on "Unable to disable interrupt on Rx queue".
This commit fixes a earlier commit where the returned value 0 from
function devx_get_event() - was considered an error.
Following the new RegEx class.
There is a need to create a dedicated test application in order to
validate this class and PMD.
Unlike net device this application loads data from a file.
This commit introduces the new RegEx test app.
The basic app flow:
1. Configure the RegEx device to use one queue, and set the rule
database, using precompiled file.
2. Allocate mbufs based on the requested number of jobs, each job will
i get one mbuf.
3. Enqueue as much as possible jobs.
4. Dequeue jobs.
5. if the number of dequeue jobs < requested number of jobs job to step
Signed-off-by: Ori Kam <orika@mellanox.com> Signed-off-by: Yuval Avnery <yuvalav@mellanox.com>
When enqueueing a buffer the PMD check if there is room
in its send queue (SQ).
The current implementation did not take into account that
queue indices are wrapping around, which may result in
consumer index (sq->ci) can have bigger value than than
the producer index (sq->pi).
Fixes: 4d4e245ad637 ("regex/mlx5: support enqueue") Signed-off-by: Yuval Avnery <yuvalav@mellanox.com> Acked-by: Ori Kam <orika@mellanox.com>
David Coyle [Tue, 21 Jul 2020 14:56:48 +0000 (15:56 +0100)]
app/crypto-perf: support security protocol in PMDCC mode
This patch adds support for DOCSIS and PDCP security protocols to the
pmd-cyclecount mode of the crypto performance tool. Adding this support
involves freeing the correct session type (i.e. security or cryptodev
session) when the test ends, depending on the op_type specified.
Signed-off-by: David Coyle <david.coyle@intel.com> Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
Ruifeng Wang [Tue, 28 Jul 2020 09:24:04 +0000 (17:24 +0800)]
crypto/armv8: remove debug option
Typo in debug log switch macro caused debug log cannot be enabled.
Since no log used in data path, remove the debug option entirely
and have logs always enabled.
Resolved compilation error when debug log is enabled:
rte_armv8_pmd.c: In function ‘process_armv8_chained_op’:
rte_armv8_pmd.c:633:22: error: expected ‘)’ before ‘crypto_func’
ARMV8_CRYPTO_ASSERT(crypto_func != NULL);
^
Fixes: 169ca3db550c ("crypto/armv8: add PMD optimized for ARMv8 processors") Cc: stable@dpdk.org Reported-by: David Marchand <david.marchand@redhat.com> Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com> Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
The structure cpt_request_info needs only 8 byte alignment.
This patch replaces __rte_cache_aligned of cpt_request_info
with __rte_aligned(8) and removes __rte_aligned(8) in
cpt_meta_info structure.
Fixes: fab634eb87ca ("crypto/octeontx2: support security session data path") Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com> Acked-by: Anoob Joseph <anoobj@marvell.com>
David Coyle [Tue, 21 Jul 2020 14:47:18 +0000 (15:47 +0100)]
crypto/qat: fix DOCSIS performance
DOCSIS protocol performance in the downlink direction can be improved
significantly in the QAT SYM PMD, especially for larger packets, by
pre-processing all CRC generations in a batch before building and
enqueuing any requests to the HW. This patch adds this optimization.
Fixes: 6f0ef237404b ("crypto/qat: support DOCSIS protocol") Signed-off-by: David Coyle <david.coyle@intel.com> Acked-by: Fiona Trahe <fiona.trahe@intel.com>
David Coyle [Mon, 20 Jul 2020 12:16:21 +0000 (13:16 +0100)]
crypto/aesni-mb: improve security instance setup
This patch makes some improvements to the security instance setup for
the AESNI-MB PMD, as follows:
- fix potential memory leak where the security instance was not freed if
an error occurred later in the device creation
- tidy-up security instance initialization code by moving it all,
including enabling the RTE_CRYPTODEV_FF_SECURITY feature, into one
'#ifdef AESNI_MB_DOCSIS_SEC_ENABLED' block
Fixes: fda5216fba55 ("crypto/aesni_mb: support DOCSIS protocol") Signed-off-by: David Coyle <david.coyle@intel.com> Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
David Coyle [Mon, 20 Jul 2020 12:16:20 +0000 (13:16 +0100)]
crypto/qat: improve security instance setup
This patch makes some improvements to the security instance setup for
the QAT SYM PMD, as follows:
- fix potential memory leak where the security instance was not freed if
an error occurred later in the device creation
- tidy-up security instance initialization code by moving it all,
including enabling the RTE_CRYPTODEV_FF_SECURITY feature, into one
'#ifdef RTE_LIBRTE_SECURITY' block
Fixes: 6f0ef237404b ("crypto/qat: support DOCSIS protocol") Signed-off-by: David Coyle <david.coyle@intel.com> Acked-by: Fiona Trahe <fiona.trahe@intel.com>
common/mlx5: remove class check from class drivers
Now that mlx5_pci PMD checks for enabled classes and performs
probe(), remove() of associated classes, individual class driver
does not need to check if other driver is enabled.
common/mlx5: introduce layer for multiple class drivers
Add generic mlx5 PCI PMD layer as part of existing common_mlx5
module. This enables multiple classes (net, regex, vdpa) PMDs
to be supported at same time.
mlx5 PCI Device supports multiple classes of devices such as net, vdpa,
and/or regex.
To support these multiple classes, change mlx5_class to a
bitmap values so that if users asks to enable multiple of them, all
supported classes can be parsed.
git.droids-corp.org / dpdk.git / log