Michael Baum [Wed, 3 Nov 2021 18:35:13 +0000 (20:35 +0200)]
common/mlx5: fix post doorbell barrier
The rdma-core library can map doorbell register in two ways, depending
on the environment variable "MLX5_SHUT_UP_BF":
- as regular cached memory, the variable is either missing or set to
zero. This type of mapping may cause the significant doorbell
register writing latency and requires an explicit memory write
barrier to mitigate this issue and prevent write combining.
- as non-cached memory, the variable is present and set to not "0"
value. This type of mapping may cause performance impact under
heavy loading conditions but the explicit write memory barrier is
not required and it may improve core performance.
The UAR creation function maps a doorbell in one of the above ways
according to the system. In run time, it always adds an explicit memory
barrier after writing to.
In cases where the doorbell was mapped as non-cached memory, the
explicit memory barrier is unnecessary and may impair performance.
The commit [1] solved this problem for a Tx queue. In run time, it
checks the mapping type and provides the memory barrier after writing to
a Tx doorbell register if it is needed. The mapping type is extracted
directly from the uar_mmap_offset field in the queue properties.
This patch shares this code between the drivers and extends the above
solution for each of them.
[1] commit 8409a28573d3
("net/mlx5: control transmit doorbell register mapping")
Michael Baum [Wed, 3 Nov 2021 18:35:12 +0000 (20:35 +0200)]
net/mlx5: remove duplicated reference of Tx doorbell
The Tx doorbell has different virtual addresses per process.
The secondary process takes the UAR physical page ID of the primary and
mmap it to its own virtual address.
The primary doorbell references were saved in two shared memory
locations: the TxQ structure and a dedicated doorbell array.
Remove the doorbell reference from the TxQ structure and move the
primary processes to take the UAR information from the primary doorbell
array.
Michael Baum [Wed, 3 Nov 2021 18:35:11 +0000 (20:35 +0200)]
common/mlx5: fix doorbell mapping configuration
UAR mapping type can be affected by the devarg tx_db_nc, which can cause
setting the environment variable MLX5_SHUT_UP_BF.
So, the MLX5_SHUT_UP_BF value and the UAR mapping parameter affect the
UAR cache mode.
Wrongly, the devarg was considered for the MLX5_SHUT_UP_BF but not for
the UAR mapping parameter in all the drivers except the net.
Take the tx_db_nc devarg into account for all the drivers.
Depending on kernel capabilities and rdma-core version the mapping of
UAR (User Access Region) of desired memory caching type (non-cached or
write combining) might fail. The PMD implements the flexible strategy
of UAR mapping, alternating the type of caching to succeed.
During this process the failure diagnostics messages are emitted.
These messages are merely diagnostics ones and the logging level should
be adjusted to DEBUG.
Michael Baum [Wed, 3 Nov 2021 18:35:09 +0000 (20:35 +0200)]
common/mlx5: remove unreachable branch in UAR allocation
The User Access Region (UAR) provides access to the hardware resources
like Doorbell Register from userspace.
It means the resources should be mapped by the kernel to some virtual
address range. There two types of memory mapping are supported by mlx5
kernel driver:
MLX5DV_UAR_ALLOC_TYPE_NC - non-cached, all writes promoted directly to
hardware.
MLX5DV_UAR_ALLOC_TYPE_BF - "BlueFlame", all writes might be cached by
CPU, and will be flushed to hardware
explicitly with memory barriers.
The supported mapping types depend on the platform (x86/ARM/etc), kernel
version, driver version, virtualization environment (hypervisor), etc.
In UAR allocation, if the system supports the allocation with non-cached
mapping, the first attempt is performed with MLX5DV_UAR_ALLOC_TYPE_NC.
Then, if this fails, the next attempt is done with
MLX5DV_UAR_ALLOC_TYPE_BF.
However, the function adds a condition for the case where the first
attempt was performed with MLX5DV_UAR_ALLOC_TYPE_BF, a condition that is
unattainable since the first attempt was always performed with
MLX5DV_UAR_ALLOC_TYPE_NC.
Michael Baum [Wed, 3 Nov 2021 18:35:08 +0000 (20:35 +0200)]
crypto/mlx5: fix login release in probing and removal
The probe function creates DevX object named login and saves pointer to
it in priv structure.
The remove function releases first the priv structure and then releases
the login object.
However, the pointer to login object is field of priv structure, which
is invalid.
Release the login object and then release the priv structure.
Michael Baum [Wed, 3 Nov 2021 10:17:07 +0000 (12:17 +0200)]
common/mlx5: make multi-process MR management port-agnostic
In the multi-process mechanism, there are things that the secondary
process does not perform itself but asks the primary process to perform
for it.
There is a special API for communication between the processes that
receives parameters necessary for the specific action required as well
as a special structure called mp_id that contains the port number of the
processes through which the initial process finds the relevant ETH
device for the processes.
One of the operations performed through this mechanism is the creation
of a memory region, where the secondary process sends the virtual
address as a parameter and the mp_id structure with the port number
inside it.
However, once the memory area management is shared between the drivers
and either port number or ETH device is no longer relevant to them, it
seems unnecessary to continue communicating between the processes
through the mp_id variable.
In this patch we will remove the use of the above structure for all MR
management, and add to the specific parameter of operations a pointer to
the common device that contains everything needed to create/register MR.
Michael Baum [Wed, 3 Nov 2021 10:17:06 +0000 (12:17 +0200)]
common/mlx5: remove redundant parameter in MR search
Memory region management has recently been shared between drivers,
including the search for caches in the data plane.
The initial search in the local linear cache of the queue, usually
yields a result and one should not continue searching in the next level
caches.
The function that searches in the local cache gets the pointer to a
device as a parameter, that is not necessary for its operation
but for subsequent searches (which, as mentioned, usually do not
happen).
Transferring the device to a function and maintaining it, takes some
time and causes some impact on performance.
Add the pointer to the device as a field of the mr_ctrl structure. The
field will be updated during control path and will be used only when
needed in the search.
Michael Baum [Wed, 3 Nov 2021 10:17:05 +0000 (12:17 +0200)]
common/mlx5: fix MR search inlining
Memory region management has recently been shared between drivers,
including the search for caches in the data plane.
The initial search in the local linear cache of the queue,
usually yields a result and one should not continue searching
in the next layer caches.
Prior to cache sharing the local linear cache lookup function
was defined with "static inline" attributes,
those were missed in routine commoditizing step
and this caused performance degradation.
David Marchand [Fri, 5 Nov 2021 13:30:17 +0000 (14:30 +0100)]
app/testpmd: remove unneeded dependency on meter lib
testpmd depends on ethdev, which itself depends on meter.
No need for an explicit dependency, since no testpmd code directly calls
in the meter library.
Signed-off-by: David Marchand <david.marchand@redhat.com> Acked-by: Bruce Richardson <bruce.richardson@intel.com> Acked-by: Ferruh Yigit <ferruh.yigit@intel.com>
Gregory Etelson [Tue, 26 Oct 2021 15:20:00 +0000 (18:20 +0300)]
app/testpmd: fix flex item flush
Testpmd provides 2 sets of flex item create and destroy functions
One for hosts with JSON library. These functions parse
flex item configuration stored in JSON file and create or destroy
flex item object. The second functions set is for hosts without JSON
library for compilation compatibility.
On hosts without JSON library, current implementation issues
"no JSON library" notification on port close.
The notification was triggered by port destructors that include
flex items flush routine.
The patch introduces single implementation for testpmd
flex item destroy.
Bing Zhao [Fri, 5 Nov 2021 15:30:39 +0000 (17:30 +0200)]
net/mlx5: check delay drop settings in kernel driver
The delay drop is the common feature managed on per device basis
and the kernel driver is responsible one for the initialization and
rearming.
By default, the timeout value is set to activate the delay drop when
the driver is loaded.
A private flag "dropless_rq" is used to control the rearming. Only
when it is on, the rearming will be handled once received a timeout
event. Or else, the delay drop will be deactivated after the first
timeout occurs and all the Rx queues won't have this feature.
The PMD is trying to query this flag and warn the application when
some queues are created with delay drop but the flag is off.
Bing Zhao [Fri, 5 Nov 2021 15:30:38 +0000 (17:30 +0200)]
net/mlx5: support Rx queue delay drop
For the Ethernet RQs, if there all receiving descriptors are
exhausted, the packets being received will be dropped. This behavior
prevents slow or malicious software entities at the host from
affecting the network. While for hairpin cases, even if there is no
software involved during the packet forwarding from Rx to Tx side,
some hiccup in the hardware or back pressure from Tx side may still
cause the descriptors to be exhausted. In certain scenarios it may be
preferred to configure the device to avoid such packet drops,
assuming the posting of descriptors will resume shortly.
To support this, a new devarg "delay_drop" is introduced. By default,
the delay drop is enabled for hairpin Rx queues and disabled for
standard Rx queues. This value is used as a bit mask:
- bit 0: enablement of standard Rx queue
- bit 1: enablement of hairpin Rx queue
And this attribute will be applied to all Rx queues of a device.
The "rq_delay_drop" capability in the HCA_CAP is checked before
creating any queue. If the hardware capabilities do not support
this delay drop, all the Rx queues will still be created without
this attribute, and the devarg setting will be ignored even if it
is specified explicitly. A warning log is used to notify the
application when this occurs.
Jie Wang [Fri, 5 Nov 2021 03:37:05 +0000 (11:37 +0800)]
net/i40e: fix forward outer IPv6 VXLAN
Testpmd forwards packets in checksum mode that it need to calculate
the checksum of each layer's protocol. Then it will fill flags and
header length into mbuf.
In process_outer_cksums, HW calculates the outer checksum if
tx_offloads contains outer UDP checksum otherwise SW calculates
the outer checksum.
When tx_offloads contains outer UDP checksum or outer IPv4 checksum,
mbuf will be filled with correct header length.
This patch added outer UDP checksum in tx_offload_capa and
I40E_TX_OFFLOAD_MASK, when we set csum hw outer-udp on that the
engine can forward outer IPv6 VXLAN packets.
Fixes: 7497d3e2f777 ("net/i40e: convert to new Tx offloads API") Cc: stable@dpdk.org Signed-off-by: Jie Wang <jie1x.wang@intel.com> Acked-by: Beilei Xing <beilei.xing@intel.com>
When receive packet, mlx5 PMD saves mbuf port number from
RxQ data.
To support shared RxQ, save port number into RQ context as user index.
Received packet resolve port number from CQE user index which derived
from RQ context.
Legacy Verbs API doesn't support RQ user index setting, still read from
RxQ port number.
Signed-off-by: Xueming Li <xuemingl@nvidia.com> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Xueming Li [Thu, 4 Nov 2021 12:33:19 +0000 (20:33 +0800)]
net/mlx5: support shared Rx queue
This patch introduces shared RxQ. All shared Rx queues with same group
and queue ID share the same rxq_ctrl. Rxq_ctrl and rxq_data are shared,
all queues from different member port share same WQ and CQ, essentially
one Rx WQ, mbufs are filled into this singleton WQ.
Shared rxq_data is set into device Rx queues of all member ports as
RxQ object, used for receiving packets. Polling queue of any member
ports returns packets of any member, mbuf->port is used to identify
source port.
Signed-off-by: Xueming Li <xuemingl@nvidia.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Xueming Li [Thu, 4 Nov 2021 12:33:14 +0000 (20:33 +0800)]
net/mlx5: move Rx queue reference count
Rx queue reference count is counter of RQ, used to count reference to RQ
object. To prepare for shared Rx queue, this patch moves it from
rxq_ctrl to Rx queue private data.
Signed-off-by: Xueming Li <xuemingl@nvidia.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Xueming Li [Thu, 4 Nov 2021 12:33:13 +0000 (20:33 +0800)]
net/mlx5: split Rx queue into shareable and private
To prepare shared Rx queue, splits RxQ data into shareable and private.
Struct mlx5_rxq_priv is per queue data.
Struct mlx5_rxq_ctrl is shared queue resources and data.
Signed-off-by: Xueming Li <xuemingl@nvidia.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Xueming Li [Thu, 4 Nov 2021 12:33:10 +0000 (20:33 +0800)]
common/mlx5: support receive memory pool
The hardware Receive Memory Pool (RMP) object holds the destination for
incoming packets/messages that are routed to the RMP through RQs. RMP
enables sharing of memory across multiple Receive Queues. Multiple
Receive Queues can be attached to the same RMP and consume memory
from that shared poll. When using RMPs, completions are reported to the
CQ pointed to by the RQ, user index that set in RQ creation time is
carried to completion entry.
This patch enables RMP based RQ, RMP is created when mlx5_devx_rq.rmp is
set.
Signed-off-by: Xueming Li <xuemingl@nvidia.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Xueming Li [Thu, 4 Nov 2021 12:33:09 +0000 (20:33 +0800)]
common/mlx5: support basic receive memory pool
The hardware Receive Memory Pool (RMP) object holds the destination for
incoming packets/messages that are routed to the RMP through RQs. RMP
enables sharing of memory across multiple Receive Queues. Multiple
Receive Queues can be attached to the same RMP and consume memory
from that shared poll. When using RMPs, completions are reported to the
CQ pointed to by the RQ, and this Completion Queue can be shared as
well.
This patch adds DevX supports of PRM RMP object.
Signed-off-by: Xueming Li <xuemingl@nvidia.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Xueming Li [Thu, 4 Nov 2021 12:33:07 +0000 (20:33 +0800)]
common/mlx5: introduce user index field in completion
On ConnectX devices the completion entry provides the dedicated 24-bit
field, that is filled up with some static value assigned at the
Receiving Queue creation moment. This patch declares this field. This is
a preparation step for supporting shared RQs and the field is supposed
to provide actual port index while handling the shared receiving
queue(s).
Signed-off-by: Xueming Li <xuemingl@nvidia.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
net/mlx5: translate flex item pattern into matcher
The matcher is an steering engine entity that represents
the flow pattern to hardware to match. It order to
provide match on the flex item pattern the appropriate
matcher fields should be configured with values and masks
accordingly.
The flex item related matcher fields is an array of eight
32-bit fields to match with data captured by sample registers
of configured flex parser. One packet field, presented in
item pattern can be split between several sample registers,
and multiple fields can be combined together into single
sample register to optimize hardware resources usage
(number os sample registers is limited), depending on field
modes, widths and offsets. Actual mapping is complicated
and controlled by special translation data, built by PMD
on flex item creation.
RTE Flow flex item configuration should be translated
into actual hardware settings:
- translate header length and next protocol field samplings
- translate data field sampling, the similar fields with the
same mode and matching related parameters are relocated
and grouped to be covered with minimal amount of hardware
sampling registers (each register can cover arbitrary
neighbour 32 bits (aligned to byte boundary) in the packet
and we can combine the fields with smaller lengths or
segments of bigger fields)
- input and output links translation
- preparing data for parsing flex item pattern on flow creation
Gregory Etelson [Tue, 2 Nov 2021 08:53:43 +0000 (10:53 +0200)]
net/mlx5: add flex parser DevX object management
The DevX flex parsers can be shared between representors
within the same IB context. We should put the flex parser
objects into the shared list and engage the standard
mlx5_list_xxx API to manage ones.
This patch is a preparation step of implementing
flex item feature in driver and it provides:
- external entry point routines for flex item
creation/deletion
- flex item objects management over the ports.
The flex item object keeps information about
the item created over the port - reference counter
to track whether item is in use by some active
flows and the pointer to underlying shared DevX
object, providing all the data needed to translate
the flow flex pattern into matcher fields according
hardware configuration.
There is not too many flex items supposed to be
created on the port, the design is optimized
rather for flow insertion rate than memory savings.
To handle eCPRI protocol in the flows the mlx5 PMD engages
flex parser hardware feature. While we were implementing
eCPRI support we anticipated the flex parser usage extension,
and all related variables were named accordingly, containing
flex syllabus. Now we are preparing to introduce more common
approach of flex item, in order to avoid naming conflicts
and improve the code readability the eCPRI infrastructure
related variables are renamed as preparation step.
Later, once we have the new flex item implemented, we could
consider to refactor the eCPRI protocol support to move on
common flex item basis.
Gregory Etelson [Tue, 2 Nov 2021 08:53:39 +0000 (10:53 +0200)]
common/mlx5: extend flex parser capabilities
MLX5 PARSE_GRAPH_NODE is the main data structure used by the Flex
Parser when a new parsing protocol is defined. While software
creates PARSE_GRAPH_NODE object for a new protocol, it must
verify that configuration parameters it uses comply with
hardware limits.
The patch queries hardware PARSE_GRAPH_NODE capabilities and
stores ones in PMD internal configuration structure:
- query capabilities from parse_graph_node attribute page
- query max_num_prog_sample_field capability from HCA page 2
Somnath Kotur [Wed, 3 Nov 2021 16:04:32 +0000 (21:34 +0530)]
net/bnxt: fix scalar Rx datapath on Thor
The patch introduced by
commit 657c2a7f1dd4 ("net/bnxt: create aggregation rings when needed")
ended up shortening the return code path from the function thereby
resulting in not executing the line of code at the end of the function
that was resetting the next consumer index to 0.
This would result in an application crash when error recovery or other
port stop/start scenarios were invoked on Thor which is what this
commit 61cd4384fabf ("net/bnxt: fix crash after port stop/start")
was addressing.
Fix it by moving the resetting line of code before the return path
in the case when aggregation rings are not used (default case).
Jay Ding [Wed, 3 Nov 2021 00:52:51 +0000 (17:52 -0700)]
net/bnxt: use enum for bank ID
Instead of integer, using enum tf_sram_bank_id for bank
id in tf_set_sram_policy_parms.
Add index check against the allocation of the meter
instance for meter drop count because there is no
reason to access it if the corresponding meter
entry is not allocated.
Signed-off-by: Jay Ding <jay.ding@broadcom.com> Reviewed-by: Steve Rempe <steve.rempe@broadcom.com> Reviewed-by: Farah Smith <farah.smith@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
net/bnxt: check mismatch of control and physical port
During the parsing of the ingress port ignore for a flow, added
check to match the control port and the physical port that is configured
to be ignored. If they do not match then the configuration to setup the
svif ignore shall fail.
Mike Baucom [Wed, 3 Nov 2021 00:52:49 +0000 (17:52 -0700)]
net/bnxt: remove 2 slice wildcard entries
Remove 2-slice wildcard entries for scale.
The type-5 wildcard IPv6 flows are removed in order to increase
the scale for app-id=3.
The app no longer supports 2-slice wildcard entries.
Signed-off-by: Mike Baucom <michael.baucom@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
When the VF representor interface is created, the VF pair relationship
is established between the VF and it is representor. If the pair
already exists then the pair needs to be deleted before allocation.
This could happen if the application is abruptly killed and restarted.
If the deletion of an existing VF rep is not done then hw pipeline is
not cleaned and a new allocation shall leave the hw in inconsistent
state.
Added support for socket direct feature. This feature
allows to ignore the incoming interface and use other fields
in the packet to identify the flow and forward.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Some of the error level log messages are made debug level messages.
When Truflow is not enabled then Truflow init error messages are
moved to debug level instead.
net/bnxt: remove devargs option for stats accumulation
The accumulation of flow counters is not determined by the application
device arguments anymore. Instead it is now dictated by the platform
capabilities whether to do software based accumulation or not.
Shahaji Bhosle [Wed, 3 Nov 2021 00:52:40 +0000 (17:52 -0700)]
net/bnxt: increase flow scale for Thor
* Updated defines and data types to allow 256 VFRs.
* Increased the encap record cache to support 256 to 4K entries. So
VxLAN connections can be scaled to 4K entries.
Farah Smith [Wed, 3 Nov 2021 00:52:35 +0000 (17:52 -0700)]
net/bnxt: support clear on read
Add clear on read stats support for Thor. Currently, the
flow stats are not cleared after they are read from the FW.
This patch adds support for clear on read. Since clear on
read support is added for flow stats in Thor, the flow
accumulation is enabled on Thor as well.
Update driver to read the multi root capability and ignore
PCI address check while creating ulp session when multi root
capability is enabled in the hardware. DPDK HSI version updated
from 1.10.2.44 to 1.10.2.68.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com> Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Mike Baucom <michael.baucom@broadcom.com> Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
net/bnxt: support NAT for dest IP and port combination
* Added support for NAT action for destination IP and port
combination for Thor devices.
* Consolidated the encapsulation and NAT entries for scaling flows
with NAT actions.
Extend Eventdev API to allow for event devices which require various
forms of internal processing to happen, even when events are not
enqueued to or dequeued from a port.
Signed-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com> Acked-by: Jerin Jacob <jerinj@marvell.com> Tested-by: Richard Eklycke <richard.eklycke@ericsson.com> Tested-by: Liron Himi <lironh@marvell.com>
Pavan Nikhilesh [Wed, 3 Nov 2021 00:52:12 +0000 (06:22 +0530)]
event/cnxk: reduce workslot memory consumption
SSO group base addresses are always are always contiguous we
need not store all the base addresses in workslot memory, instead
just store the base address and compute the group address offset
when required.
Pavan Nikhilesh [Wed, 3 Nov 2021 00:52:11 +0000 (06:22 +0530)]
event/cnxk: fix packet Tx overflow
The transmit loop incorrectly assumes that nb_mbufs is always
a multiple of 4 when transmitting an event vector. The max
size of the vector might not be reached and pushed out early
due to timeout.
Fixes: 761a321acf91 ("event/cnxk: support vectorized Tx event fast path") Cc: stable@dpdk.org Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
This patch adds new api ``rte_event_eth_rx_adapter_queue_stats_get`` to
retrieve queue stats. The queue stats are in the format
``struct rte_event_eth_rx_adapter_queue_stats``.
For resetting the queue stats,
``rte_event_eth_rx_adapter_queue_stats_reset`` api is added.
The adapter stats_get and stats_reset apis are also updated to
handle queue level event buffer use case.
Signed-off-by: Naga Harish K S V <s.v.naga.harish.k@intel.com> Acked-by: Jay Jayatheerthan <jay.jayatheerthan@intel.com>
Fan Zhang [Thu, 4 Nov 2021 10:34:57 +0000 (10:34 +0000)]
crypto/qat: add gen-specific implementation
This patch replaces the mixed QAT symmetric and asymmetric
support implementation by separate files with shared or
individual implementation for specific QAT generation.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com> Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com> Signed-off-by: Kai Ji <kai.ji@intel.com> Acked-by: Ciara Power <ciara.power@intel.com>
Fan Zhang [Thu, 4 Nov 2021 10:34:56 +0000 (10:34 +0000)]
crypto/qat: define gen-specific structs and functions
This patch adds the symmetric and asymmetric crypto data
structure and function prototypes for different QAT
generations.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com> Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com> Signed-off-by: Kai Ji <kai.ji@intel.com> Acked-by: Ciara Power <ciara.power@intel.com>
Fan Zhang [Thu, 4 Nov 2021 10:34:55 +0000 (10:34 +0000)]
crypto/qat: unify device private data structure
This patch unifies the QAT symmetric and asymmetric device
private data structures and functions.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com> Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com> Signed-off-by: Kai Ji <kai.ji@intel.com> Acked-by: Ciara Power <ciara.power@intel.com>
Fan Zhang [Thu, 4 Nov 2021 10:34:54 +0000 (10:34 +0000)]
compress/qat: add gen-specific implementation
This patch replaces the mixed QAT compression support
implementation by separate files with shared or individual
implementation for specific QAT generation.
Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com> Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com> Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com> Signed-off-by: Kai Ji <kai.ji@intel.com> Acked-by: Ciara Power <ciara.power@intel.com>
Fan Zhang [Thu, 4 Nov 2021 10:34:53 +0000 (10:34 +0000)]
compress/qat: define gen-specific structs and functions
This patch adds the compression data structure and function
prototypes for different QAT generations.
Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com> Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com> Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com> Signed-off-by: Kai Ji <kai.ji@intel.com> Acked-by: Ciara Power <ciara.power@intel.com>
Fan Zhang [Thu, 4 Nov 2021 10:34:52 +0000 (10:34 +0000)]
common/qat: add gen-specific queue implementation
This patch replaces the mixed QAT queue pair configuration
implementation by separate files with shared or individual
implementation for specific QAT generation.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com> Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com> Signed-off-by: Kai Ji <kai.ji@intel.com> Signed-off-by: Przemyslaw Zegan <przemyslawx.zegan@intel.com> Acked-by: Ciara Power <ciara.power@intel.com>
This patch replaces the mixed QAT device configuration
implementation by separate files with shared or
individual implementation for specific QAT generation.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com> Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com> Signed-off-by: Kai Ji <kai.ji@intel.com> Acked-by: Ciara Power <ciara.power@intel.com>
Fan Zhang [Thu, 4 Nov 2021 10:34:49 +0000 (10:34 +0000)]
common/qat: define gen-specific structs and functions
This patch adds the data structure and function prototypes for
different QAT generations.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com> Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com> Signed-off-by: Kai Ji <kai.ji@intel.com> Acked-by: Ciara Power <ciara.power@intel.com>
git.droids-corp.org / dpdk.git / log