Shreyansh Jain [Wed, 18 Jan 2017 14:05:17 +0000 (19:35 +0530)]
bus: introduce bus abstraction
This patch introduces the rte_bus abstraction for EAL.
The model is:
- One or more devices are connected to a Bus
- Drivers are running instances which manage one or more devices
- Bus is responsible for identifying devices (and interrupt propogation)
- Driver is responsible for initializing the device
This patch adds a 'rte_bus' base class which would be extended for
specific implementations. It also introduces Bus registration and
deregistration functions.
Zbigniew Bodek [Wed, 18 Jan 2017 20:02:01 +0000 (21:02 +0100)]
app/test: add ARMv8 crypto tests and test vectors
Introduce unit tests for ARMv8 crypto PMD.
Add test vectors for short cases such as 160 bytes.
These test cases are ARMv8 specific since the code provides
different processing paths for different input data sizes.
User can validate correctness of algorithms' implementation using:
* cryptodev_sw_armv8_autotest
For performance test one can use:
* cryptodev_sw_armv8_perftest
Signed-off-by: Zbigniew Bodek <zbigniew.bodek@caviumnetworks.com> Reviewed-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Zbigniew Bodek [Wed, 18 Jan 2017 20:01:57 +0000 (21:01 +0100)]
cryptodev: introduce ARM-specific feature flags
Add two new feature flags:
* RTE_CRYPTODEV_FF_CPU_NEON
represents ARM NEON (TM) instructions
* RTE_CRYPTODEV_FF_CPU_ARM_CE
represents ARM crypto extensions
Add them to both cryptodev library, documentation and relevant
PMD driver for ARMv8.
Signed-off-by: Zbigniew Bodek <zbigniew.bodek@caviumnetworks.com>
Zbigniew Bodek [Wed, 18 Jan 2017 20:01:54 +0000 (21:01 +0100)]
crypto/armv8: add PMD optimized for ARMv8 processors
This patch introduces crypto poll mode driver
using ARMv8 cryptographic extensions.
CPU compatibility with this driver is detected in
run-time and virtual crypto device will not be
created if CPU doesn't provide:
AES, SHA1, SHA2 and NEON.
This PMD is optimized to provide performance boost
for chained crypto operations processing,
such as encryption + HMAC generation,
decryption + HMAC validation. In particular,
cipher only or hash only operations are
not provided.
The driver currently supports AES-128-CBC
in combination with: SHA256 HMAC and SHA1 HMAC
and relies on the external armv8_crypto library:
https://github.com/caviumnetworks/armv8_crypto
Build ARMv8 crypto PMD if compiling for ARM64
and CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO option
is enable in the configuration file.
ARMV8_CRYPTO_LIB_PATH environment variable will
point to the appropriate library directory.
Signed-off-by: Zbigniew Bodek <zbigniew.bodek@caviumnetworks.com> Reviewed-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Pablo de Lara [Wed, 18 Jan 2017 17:31:00 +0000 (17:31 +0000)]
doc: add ZUC to crypto matrices
When ZUC PMD was added, it was not added in the
Crypto Device Supported Functionality Matrices.
This commit adds a column in all the matrices, plus
the ZUC EEA3/EIA3 algorithms.
Fixes: cf7685d68f00 ("crypto/zuc: add driver for ZUC library") Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Piotr Azarewicz [Tue, 17 Jan 2017 11:19:18 +0000 (12:19 +0100)]
crypto/aesni_gcm: migrate from MB library to ISA-L
Current Cryptodev AES-NI GCM PMD is implemented using Multi Buffer
Crypto library.This patch reimplement the device using ISA-L Crypto
library: https://github.com/01org/isa-l_crypto.
The migration entailed the following additional support for:
* GMAC algorithm.
* 256-bit cipher key.
* Session-less mode.
* Out-of place processing
* Scatter-gatter support for chained mbufs (only out-of place and
destination mbuf must be contiguous)
Signed-off-by: Piotr Azarewicz <piotrx.t.azarewicz@intel.com> Acked-by: Declan Doherty <declan.doherty@intel.com>
Fan Zhang [Mon, 16 Jan 2017 14:14:54 +0000 (14:14 +0000)]
cryptodev: add user defined name for vdev
This patch adds a user defined name initializing parameter to cryptodev
library.
Originally, for software cryptodev PMD, the vdev name parameter is
treated as the driver identifier, and will create an unique name for each
device automatically, which is not necessarily as same as the vdev
parameter.
This patch allows the user to either create a unique name for his software
cryptodev, or by default, let the system creates a unique one. This should
help the user managing the created cryptodevs easily.
Examples:
CLI command fragment 1: --vdev "crypto_aesni_gcm_pmd"
The above command will result in creating a AESNI-GCM PMD with name of
"crypto_aesni_gcm_X", where postfix X is the number assigned by the system,
starting from 0. This fragment can be placed in the same CLI command
multiple times, resulting the postfixs incremented by one for each new
device.
CLI command fragment 2: --vdev "crypto_aesni_gcm_pmd,name=gcm1"
The above command will result in creating a AESNI-GCM PMD with name of
"gcm1". This fragment can be placed in the same CLI command multiple
times, as long as each having a unique name value.
Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com> Acked-by: Declan Doherty <declan.doherty@intel.com>
Zbigniew Bodek [Thu, 12 Jan 2017 14:52:37 +0000 (15:52 +0100)]
examples/ipsec-secgw: support SHA256 HMAC
Add minor adjustments to support SHA256 HMAC:
- extend maximum key length to match SHA256 HMAC
- add SHA256 HMAC parameters and configuration string
- add SHA256 HMAC to inbound and outbound cases
Signed-off-by: Zbigniew Bodek <zbigniew.bodek@caviumnetworks.com> Acked-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
Tomasz Kulasek [Fri, 13 Jan 2017 15:23:17 +0000 (16:23 +0100)]
app/test: check scatter-gather for crypto drivers
This patch provides unit tests for set of cipher/hash combinations covering
currently implemented crypto PMD's and allowing to verify scatter gather
support.
Signed-off-by: Daniel Mrzyglod <danielx.t.mrzyglod@intel.com> Signed-off-by: Tomasz Kulasek <tomaszx.kulasek@intel.com> Acked-by: Declan Doherty <declan.doherty@intel.com>
Tomasz Kulasek [Fri, 13 Jan 2017 15:23:15 +0000 (16:23 +0100)]
crypto: support scatter-gather in software drivers
This patch introduces RTE_CRYPTODEV_FF_MBUF_SCATTER_GATHER feature flag
informing that selected crypto device supports segmented mbufs natively
and doesn't need to be coalesced before crypto operation.
While using segmented buffers in crypto devices may have unpredictable
results, for PMDs which doesn't support it natively, additional check is
made for debug compilation.
Signed-off-by: Tomasz Kulasek <tomaszx.kulasek@intel.com> Acked-by: Declan Doherty <declan.doherty@intel.com>
Daniel Mrzyglod [Tue, 10 Jan 2017 14:44:25 +0000 (15:44 +0100)]
crypto/openssl: fix indentation in guide
The code section was lacking indentation to be be correctly formatted.
Fixes: d61f70b4c918 ("crypto/libcrypto: add driver for OpenSSL library") Signed-off-by: Daniel Mrzyglod <danielx.t.mrzyglod@intel.com> Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Fan Zhang [Wed, 11 Jan 2017 14:09:47 +0000 (14:09 +0000)]
cryptodev: fix loop in device query
This patch fixes the dev value update problem in
rte_cryptodev_pmd_get_named_dev, orginally, dev won't be updated
after the initial step in the loop.
Fixes: d11b0f30df88 ("cryptodev: introduce API and framework for crypto devices") Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com> Acked-by: Fiona Trahe <fiona.trahe@intel.com>
Declan Doherty [Wed, 21 Dec 2016 22:05:00 +0000 (22:05 +0000)]
crypto/aesni_mb: support AVX512
Release v0.44 of Intel(R) Multi-Buffer Crypto for IPsec library adds
support for AVX512 instructions. This patch enables the new AVX512
accelerated functions from the aesni_mb_pmd crypto poll mode driver.
This patch set requires that the aesni_mb_pmd is linked against the
version 0.44 or greater of the Multi-Buffer Crypto for IPsec library.
Signed-off-by: Declan Doherty <declan.doherty@intel.com> Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Pablo de Lara [Mon, 19 Dec 2016 17:29:02 +0000 (17:29 +0000)]
crypto/aesni_mb: add single operation functionality
Update driver to use new AESNI Multibuffer IPSec library single
operation functionality (cipher only and authentication only).
This patch also adds tests for this new feature.
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com> Acked-by: Declan Doherty <declan.doherty@intel.com>
Pablo de Lara [Mon, 19 Dec 2016 17:29:01 +0000 (17:29 +0000)]
crypto/aesni_mb: update dependency in guide
The Intel(R) Multi Buffer Crypto library used in the AESNI MB PMD
has been moved to a new repository, in github.
This patch updates the link where it can be downloaded.
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com> Acked-by: John McNamara <john.mcnamara@intel.com>
Pablo de Lara [Mon, 19 Dec 2016 17:29:00 +0000 (17:29 +0000)]
crypto/aesni_mb: fix incorrect crypto session
When using sessionless crypto operations, crypto session
is obtained from a pool of sessions, when processing the
operation. Once the operation is processed, the session
is put back in the pool, but for the AESNI MB PMD, this
session was not being saved in the operation and therefore,
it did not return to the session pool.
Fixes: 924e84f87306 ("aesni_mb: add driver for multi buffer based crypto") Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com> Acked-by: Declan Doherty <declan.doherty@intel.com>
Arek Kusztal [Fri, 23 Dec 2016 12:51:10 +0000 (12:51 +0000)]
app/test: check SGL on QAT
This commit adds GCM tests to use within scatter-gather list.
Test use direct chained mbufs created based on the input parameter
for max size for in place operations and out of place operations.
Piotr Azarewicz [Wed, 7 Dec 2016 10:45:54 +0000 (11:45 +0100)]
crypto/openssl: fix extra bytes written at end of data
Extra bytes are being written at end of data while process standard
openssl cipher encryption. This behaviour is unexpected.
This patch disable the padding feature in openssl library, which is
causing the problem.
Fixes: d61f70b4c918 ("crypto/libcrypto: add driver for OpenSSL library") Signed-off-by: Piotr Azarewicz <piotrx.t.azarewicz@intel.com> Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Fiona Trahe [Fri, 9 Dec 2016 15:39:05 +0000 (15:39 +0000)]
crypto/qat: fix buffer overwrite in OOP case
In out-of-place operation, data is DMAed from source mbuf
to destination mbuf. To avoid header data in dest mbuf being
overwritten, the minimal data-set should be DMAed.
Fixes: 39e0bee48e81 ("crypto/qat: rework request builder for performance") Signed-off-by: Fiona Trahe <fiona.trahe@intel.com> Acked-by: John Griffin <john.griffin@intel.com>
Jerin Jacob [Sat, 3 Dec 2016 18:34:01 +0000 (00:04 +0530)]
cryptodev: fix crash on null dereference
crypodev->data->name will be null when
rte_cryptodev_get_dev_id() invoked without a valid
crypto device instance.
Fixes: d11b0f30df88 ("cryptodev: introduce API and framework for crypto devices") Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> Acked-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Fiona Trahe [Thu, 24 Nov 2016 18:29:24 +0000 (18:29 +0000)]
app/test: check AES cipher-only on QAT
Extended functional AES-CBC and AES-CTR cipher-only
tests to run on QAT PMD.
Added AES_CBC cipher-only performance tests on QAT PMD.
No driver changes, but as now tested, QAT documentation
is updated to remove constraint.
Fiona Trahe [Thu, 17 Nov 2016 17:33:17 +0000 (17:33 +0000)]
cryptodev: remove unused digest-appended feature
The cryptodev API had specified that if the digest address field was
left empty on an authentication operation, then the PMD would assume
the digest was appended to the source or destination data.
This case was not handled at all by most PMDs and incorrectly handled
by the QAT PMD.
As no bugs were raised, it is assumed to be not needed, so this patch
removes it, rather than add handling for the case on all PMDs.
The digest can still be appended to the data, but its
address must now be provided in the op.
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com> Acked-by: John Griffin <john.griffin@intel.com>
Pablo de Lara [Tue, 17 Jan 2017 22:23:56 +0000 (22:23 +0000)]
doc: add flow distributor example guide
Signed-off-by: Sameh Gobriel <sameh.gobriel@intel.com> Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com> Acked-by: Christian Maciocco <christian.maciocco@intel.com>
Pablo de Lara [Tue, 17 Jan 2017 22:23:54 +0000 (22:23 +0000)]
examples/flow_distributor: new example to demonstrate EFD
This new sample app, based on the client/server sample app,
shows the user an scenario using the EFD library.
It consists of:
- A front-end server which has an EFD table that stores the
node id for each flow key, which will distribute the incoming
packets to the different nodes
- A back-end node, which has a hash table where node checks,
after reading packets coming from the server, whether the packet
is meant to be used in such node, in which case it will be TXed,
or not, in which case, packet will be dropped.
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com> Signed-off-by: Saikrishna Edupuganti <saikrishna.edupuganti@intel.com> Acked-by: Christian Maciocco <christian.maciocco@intel.com>
Pablo de Lara [Tue, 17 Jan 2017 22:23:51 +0000 (22:23 +0000)]
efd: new Elastic Flow Distributor library
Elastic Flow Distributor (EFD) is a distributor library that uses
perfect hashing to determine a target/value for a given incoming flow key.
It has the following advantages:
- First, because it uses perfect hashing, it does not store
the key itself and hence lookup performance is not dependent
on the key size.
- Second, the target/value can be any arbitrary value hence
the system designer and/or operator can better optimize service rates
and inter-cluster network traffic locating.
- Third, since the storage requirement is much smaller than a hash-based
flow table (i.e. better fit for CPU cache), EFD can scale to
millions of flow keys.
Finally, with current optimized library implementation performance
is fully scalable with number of CPU cores.
Signed-off-by: Byron Marohn <byron.marohn@intel.com> Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com> Signed-off-by: Saikrishna Edupuganti <saikrishna.edupuganti@intel.com> Acked-by: Christian Maciocco <christian.maciocco@intel.com>
Santosh Shukla [Wed, 18 Jan 2017 01:21:28 +0000 (06:51 +0530)]
crypto/qat: use I/O device memory read/write API
Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix portability
issues across different architectures.
Santosh Shukla [Wed, 18 Jan 2017 01:21:42 +0000 (06:51 +0530)]
net/vmxnet3: use I/O device memory read/write API
Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix
portability issues across different architectures.
CC: Yong Wang <yongwang@vmware.com> Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com> Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Santosh Shukla [Wed, 18 Jan 2017 01:21:41 +0000 (06:51 +0530)]
net/virtio: use I/O device memory read/write API
Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix
portability issues across different architectures.
Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com> Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> Acked-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Jerin Jacob [Wed, 18 Jan 2017 01:21:40 +0000 (06:51 +0530)]
net/thunderx: use I/O device memory read/write API
Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix portability
issues across different architectures.
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Jerin Jacob [Wed, 18 Jan 2017 01:21:34 +0000 (06:51 +0530)]
net/ena: use I/O device memory read/write API
Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix
portability issues across different architectures.
Suggested-by: Jan Medala <jan@semihalf.com> Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> Acked-by: Jan Medala <jan@semihalf.com>
Santosh Shukla [Wed, 18 Jan 2017 01:21:39 +0000 (06:51 +0530)]
net/qede: use I/O device memory read/write API
Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix
portability issues across different architectures.
Santosh Shukla [Wed, 18 Jan 2017 01:21:29 +0000 (06:51 +0530)]
net/bnxt: use I/O device memory read/write API
Replace the raw I/O device memory read/write access with eal abstraction
for I/O device memory read/write access to fix portability issues across
different architectures.
CC: Stephen Hurd <stephen.hurd@broadcom.com> CC: Ajit Khaparde <ajit.khaparde@broadcom.com> Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com> Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Santosh Shukla [Wed, 18 Jan 2017 01:21:30 +0000 (06:51 +0530)]
net/bnx2x: use I/O device memory read/write API
Replace the raw I/O device memory read/write access with eal abstraction
for I/O device memory read/write access to fix portability issues across
different architectures.
Santosh Shukla [Wed, 18 Jan 2017 01:21:31 +0000 (06:51 +0530)]
net/cxgbe: use I/O device memory read/write API
Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix
portability issues across different architectures.
Santosh Shukla [Wed, 18 Jan 2017 01:21:38 +0000 (06:51 +0530)]
net/nfp: use I/O device memory read/write API
Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix
portability issues across different architectures.
Santosh Shukla [Wed, 18 Jan 2017 01:21:33 +0000 (06:51 +0530)]
net/enic: use I/O device memory read/write API
Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix portability
issues across different architectures.
CC: John Daley <johndale@cisco.com> CC: Nelson Escobar <neescoba@cisco.com> Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com> Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Santosh Shukla [Wed, 18 Jan 2017 01:21:35 +0000 (06:51 +0530)]
net/fm10k: use I/O device memory read/write API
Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix
portability issues across different architectures.
Santosh Shukla [Wed, 18 Jan 2017 01:21:36 +0000 (06:51 +0530)]
net/i40e: use I/O device memory read/write API
Replace the raw I/O device memory read/write access with eal abstraction
for I/O device memory read/write access to fix portability issues across
different architectures.
Santosh Shukla [Wed, 18 Jan 2017 01:21:37 +0000 (06:51 +0530)]
net/ixgbe: use I/O device memory read/write API
Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix
portability issues across different architectures.
CC: Helin Zhang <helin.zhang@intel.com> CC: Konstantin Ananyev <konstantin.ananyev@intel.com> Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com> Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Santosh Shukla [Wed, 18 Jan 2017 01:21:32 +0000 (06:51 +0530)]
net/e1000: use I/O device memory read/write API
Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix
portability issues across different architectures.
CC: Wenzhuo Lu <wenzhuo.lu@intel.com> Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com> Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
This commit introduces 8-bit, 16-bit, 32bit, 64bit I/O device
memory read/write operations along with the relaxed versions.
The weakly-ordered machine like ARM needs additional I/O barrier for
device memory read/write access over PCI bus.
By introducing the eal abstraction for I/O device memory read/write access,
The drivers can access I/O device memory in architecture agnostic manner.
The relaxed version does not have additional I/O memory barrier, useful in
accessing the device registers of integrated controllers which
implicitly strongly ordered with respect to memory access.
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Jerin Jacob [Wed, 18 Jan 2017 01:21:15 +0000 (06:51 +0530)]
eal/x86: define I/O device memory barriers
The patch does not provide any functional change for IA.
I/O barriers are mapped to existing smp barriers.
CC: Bruce Richardson <bruce.richardson@intel.com> CC: Konstantin Ananyev <konstantin.ananyev@intel.com> Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Thomas Monjalon [Tue, 17 Jan 2017 14:35:11 +0000 (15:35 +0100)]
devtools: relax tag checking in fixes
The tag "Cc: stable@dpdk.org" must be set when the commit must be
backported to a stable branch. The reminder is reworded.
It should be located just below the "Fixes:" tag (without blank line)
and followed by a blank line, separated from SoB and review tags below.
However, there is no strong need for checking blank lines.
Signed-off-by: Thomas Monjalon <thomas.monjalon@6wind.com> Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Alejandro Lucero [Fri, 13 Jan 2017 11:50:02 +0000 (11:50 +0000)]
config: enable nfp driver on Linux
Because using a NFP PMD requires specific BSP installed, the PMD
support was not the default option before. This was just for making
people aware of such dependency, since there is no need for such a
BSP for just compiling DPDK with NFP PMD support.
net/i40e: support Linux VF to configure IRQ link list
i40e PF host only support to work with DPDK VF driver, Linux
VF driver is not supported. This change will enhance in
configuring IRQ link list.
This Change will identify VF client by number of vector
requested. DPDK VF will ask only single one while Linux VF
will request at least 2. It will have different configuration
for different clients. DPDK VF will be configured to link all
queue together, while Linux VF will be configured per request.
When VF requested to configure TX queue, a few parameters are
missed to be configured in PF host. This change have more
fields parsed and configured for TX context.
When VF sends request to add a new MAC address, PF host
will check if it's a non-zero or unicast address, or it
will return with error. In fact, VF still can set multicast
address. This change remove to check if it's a unicast
address.
Wenzhuo Lu [Tue, 17 Jan 2017 08:45:20 +0000 (16:45 +0800)]
app/testpmd: use VFD APIs on i40e
The new VF Daemon (VFD) APIs is implemented on i40e. Change
testpmd code to use them, including VF MAC anti-spoofing,
VF VLAN anti-spoofing, TX loopback, VF VLAN strip, VF VLAN
insert.
Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com> Signed-off-by: Chen Jing D(Mark) <jing.d.chen@intel.com> Signed-off-by: Bernard Iremonger <bernard.iremonger@intel.com> Acked-by: Helin Zhang <helin.zhang@intel.com> Acked-by: Vincent Jardin <vincent.jardin@6wind.com>
Ferruh Yigit [Tue, 17 Jan 2017 08:45:14 +0000 (16:45 +0800)]
net/i40e: fix VF MAC address assignment
If PF sets vf->mac_addr, in VF initialization hw->mac.addr will be set
to that same value. It is possible to check if PF set a MAC address or
not through the hw->mac.addr variable.
hw->mac.addr set by i40e_vf_parse_hw_config(), call stack is:
In PF side
i40e_pf_host_process_cmd_get_vf_resources()
eth_addr_copy(vf->mac_addr, vf_res->vsi_res[0].default_mac_address)
In VF sise
i40evf_init_vf()
i40evf_get_vf_resources()
i40e_vf_parse_hw_config()
memcpy(hw->mac.addr, vsi_res->default_mac_addr)
Updated code is after i40evf_get_vf_resources() and can benefit from
hw->mac.addr variable.
Fixes: 89e6b86384bb ("i40evf: rework MAC address validation") Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com> Acked-by: Helin Zhang <helin.zhang@intel.com> Acked-by: Vincent Jardin <vincent.jardin@6wind.com>
git.droids-corp.org / dpdk.git / log