ethdev: validate input in register info

This patch adds validity check of input pointer in regs dump API.

Fixes: 7a3f27cbf59b ("ethdev: add access to specific device info")
Fixes: 936eda25e8da ("net/hns3: support dump register")
Cc: stable@dpdk.org
Signed-off-by: Chengchang Tang <tangchengchang@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>

ethdev: validate input in module EEPROM dump

The validity verification of input parameters should be performed at
API layer, not in the PMD.

Fixes: 3a18c44b45df ("ethdev: add access to EEPROM")
Fixes: 40ff8b305ab8 ("net/e1000: add module EEPROM callbacks for e1000")
Fixes: f2088e785cca ("net/i40e: fix dereference before check when getting EEPROM")
Fixes: b74d0cd43e37 ("net/ixgbe: add module EEPROM callbacks for ixgbe")
Fixes: 8a6a09f853a0 ("net/mlx5: support reading module EEPROM data")
Fixes: 58f6f93c34c1 ("net/octeontx2: add module EEPROM dump")
Cc: stable@dpdk.org
Signed-off-by: Chengchang Tang <tangchengchang@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>

net/virtio: fix interrupt unregistering for listening socket

virtio_user_dev_server_reconnect() is typically called from the
interrupt context while checking the link state:

  vhost_user_update_link_state()
  --> virtio_user_dev_server_reconnect()

Under this conditions callback unregistering always fails.  This means
that listenfd is never unregistered and continue to trigger interrupts.
For example, if second client will try to connect to the same socket,
the server will receive interrupts infinitely because it will not
accept them while listen fd is readable and generates epoll events.

Fix that by moving reconfiguration of interrupts out of the
interrupt context to alarm handler.

'virtio_user_dev_delayed_handler' renamed to
'virtio_user_dev_delayed_disconnect_handler' to better reflect its
purpose.

Additionally improved error logging around interrupt management.

Fixes: bd8f50a45d0f ("net/virtio-user: support server mode")
Cc: stable@dpdk.org
Signed-off-by: Ilya Maximets <i.maximets@ovn.org>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>

vhost: avoid IOTLB mempool allocation while IOMMU disabled

If vhost device's IOMMU feature is disabled, IOTLB mempool allocation
is unnecessary.

Reported-by: Peng He <hepeng.0320@bytedance.com>
Signed-off-by: Junjie Wan <wanjunjie@bytedance.com>
Reviewed-by: Zhihong Wang <wangzhihong.wzh@bytedance.com>
Reviewed-by: Chenbo Xia <chenbo.xia@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>

vhost: fix initialization of async temporary header

This patch fixes coverity issue in async enqueue function by adding
initialization step before using temporary virtio header.

Coverity issue: 366123
Fixes: cd6760da1076 ("vhost: introduce async enqueue for split ring")
Cc: stable@dpdk.org
Signed-off-by: Marvin Liu <yong.liu@intel.com>
Reviewed-by: Chenbo Xia <chenbo.xia@intel.com>

vhost: fix initialization of temporary header

This patch fixs coverity issue by adding initialization step before
using temporary virtio header.

Coverity issue: 366181
Fixes: fb3815cc614d ("vhost: handle virtually non-contiguous buffers in Rx-mrg")
Cc: stable@dpdk.org
Signed-off-by: Marvin Liu <yong.liu@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>

net/bnxt: fix FW unregister log

The "Unregistered with fw" message was being logged in a wrong function.
Moved it to the right place.

Fixes: a7dda7e0a00b ("net/bnxt: log port id in async events")

Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>

net/bnxt: fix configuring LRO

While configuring LRO, driver should check the return value
of bnxt_hwrm_vnic_tpa_cfg() HWRM command and return error
when the FW command fails.

Fixes: 0958d8b6435d ("net/bnxt: support LRO")
Cc: stable@dpdk.org
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>

net/bnxt: fix double free in port start failure

During port start when bnxt_start_nic() fails, it tries to free
"intr_handle->intr_vec" but the variable is not set to NULL after that.
If port start fails, driver invokes bnxt_dev_stop() which will lead
to a double free of "intr_handle->intr_vec".

Fix it by removing the call to free "intr_handle->intr_vec" in the
bnxt_start_nic() failure path as it is anyway doing in bnxt_dev_stop().

Fixes: 9d276b439aaf ("net/bnxt: fix error handling in device start")
Cc: stable@dpdk.org
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>

net/mlx5: fix drop action for Direct Rules/Verbs

There are multiple branches in rdma-core library backing
the rte flows:
  - Verbs
  - Direct Verbs (DV)
  - Direct Rules (DR)

The Verbs API always requires the specifying the queue even
if there is the drop action in the flow, though the kernel
optimizes out the actual queue usage for the flows containing
the drop action. The PMD handles the dedicated Rx queue to
provide Verbs API compatibility.

The DV/DR API does not require explicit specifying the queue
at the flow creation, but PMD still specified the dedicated
drop queue as action. It performed the packet forwarding to
the dummy queue (that was not polled at all) causing the
steering pipeline resources usage and degrading the overall
packet processing rate. For example, with inserted flow to
drop all the ingress packets the statistics reported only
15Mpps of 64B packets were received over 100Gbps line.

Since the Direct Rule API for E-Switch was introduced the
rdma-core supports the dedicated drop action, that is recognized
both for DV and DR and can be used for the entire device in
unified fashion, regardless of steering domain. The similar drop
action was introduced for E-Switch, the usage of this one can be
extended for other steering domains, not for E-Switch's one only.

This patch:
  - renames esw_drop_action to dr_drop_action to emphasize
    the global nature of the variable (not only E-Switch domain)
  - specifies this global drop action instead of dedicated
    drop queue for the DR/DV flows

Fixes: 34fa7c0268e7 ("net/mlx5: add drop action to Direct Verbs E-Switch")
Fixes: 65b3cd0dc39b ("net/mlx5: create global drop action")
Cc: stable@dpdk.org
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

common/mlx5: rename definition of PCI driver name

The current define for MLX5_DRIVER_NAME refers specially for the PCI
driver.

The define itself does not mention PCI and this is confusing.

Rename from MLX5_DRIVER_NAME to MLX5_PCI_DRIVER_NAME.

Signed-off-by: Asaf Penso <asafp@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

common/mlx5: align log prefix across drivers

Some mlx5 PMDs define the log prefix as "mlx5_pmd" while others as
"pmd_mlx5".
The patch aligns all pmds to use the "mlx5_pmd" format.

Signed-off-by: Asaf Penso <asafp@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

net/mlx5: fix missing shared RSS hash types

Shared RSS action create all supported RSS hash combination
in advance and lookup the right hash TIR when flow is actually
applied by comparing hash field value.

Unfortunately some hash combination is missed, for example,
UDP/TCP dest port only, L3-src-only, etc.

This patch add the missing hash combination.

In order to reduce the usage of pre-created TIRs and because
for one L3+L4 combination only one IBV hash type is possible,
for example, either IBV_RX_HASH_SRC_PORT_UDP or IBV_RX_HASH_DST_PORT_UDP
or both of them could be set so they can share same slot in
mlx5_rss_hash_fields, means only one TIR will be created.

Fixes: d2046c09aa64 ("net/mlx5: support shared action for RSS")
Cc: stable@dpdk.org
Signed-off-by: Xiaoyu Min <jackmin@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

net/mlx5: fix shared inner RSS

The shared RSS action use the _tunnel_ information which is derived
from flow items to decide whether need to do inner RSS or not.
However, inner RSS should be decided by RSS level (>1) in configuration
and then to create TIR with 'IBV_RX_HASH_INNER' hash bit set.

Also, for one shared RSS action there is only one set of TIRs -
outer or inner could be so the unnecessary set of TIRs are removed
in order to reduce resource.

Fixes: d2046c09aa64 ("net/mlx5: support shared action for RSS")
Cc: stable@dpdk.org
Signed-off-by: Xiaoyu Min <jackmin@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

net/ice: support VXLAN VNI field in flow director

Add support for VNI field in FDIR. Treat VXLAN flow type as
ICE_FLTR_PTYPE_NONF_IPV4_UDP_VXLAN to align with shared code. It
allows to match outer L2/L3, VNI and inner L2/L3 fields with VXLAN
pattern.
VNI takes 24 bits in VXLAN header, but uses 32 bits for matching in
shared code. The 8 bits reserved field adjacent should always be 0.

Signed-off-by: Zhirun Yan <zhirun.yan@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>

net/i40e: fix flow director config after flow validate

The configuration of FDIR input set should not be set
during flow validate. It should be set when flow create.

Fixes: fe5d0e85b713 ("net/i40e: fix flow director flex configuration")
Fixes: 15018d79f0be ("net/i40e: add FDIR support for GTP-C and GTP-U")
Cc: stable@dpdk.org
Signed-off-by: Murphy Yang <murphyx.yang@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>

raw/ifpga/base: check null pointer

In init_sec_mgr(), pointer "hw" may be NULL, so "hw" should
be checked before dereferencing.

Coverity issue: 367483
Fixes: a05bd1b40bde ("raw/ifpga: add FPGA RSU APIs")

Signed-off-by: Wei Huang <wei.huang@intel.com>
Acked-by: Tianfei Zhang <tianfei.zhang@intel.com>
Acked-by: Rosen Xu <rosen.xu@intel.com>

raw/ifpga/base: check file length

In fpga_update_flash(), "smgr->rsu_length" is passed to a
parameter that cannot be negative. So return value of
function "lseek" should be checked before being assigned
to "smgr->rsu_length".

Coverity issue: 367481
Fixes: a05bd1b40bde ("raw/ifpga: add FPGA RSU APIs")

Signed-off-by: Wei Huang <wei.huang@intel.com>
Acked-by: Tianfei Zhang <tianfei.zhang@intel.com>
Acked-by: Rosen Xu <rosen.xu@intel.com>

raw/ifpga/base: check lseek failure

In write_flash_image(), calling function "lseek" without checking
return value has risk. Negative return value should be handled as
an error condition.

Coverity issue: 367478
Fixes: a05bd1b40bde ("raw/ifpga: add FPGA RSU APIs")

Signed-off-by: Wei Huang <wei.huang@intel.com>
Acked-by: Tianfei Zhang <tianfei.zhang@intel.com>
Acked-by: Rosen Xu <rosen.xu@intel.com>

doc: update recommended versions for i40e

Kernel driver 2.13.10 is removed, so update recommended matching list
for i40e.

Cc: stable@dpdk.org
Signed-off-by: Robin Zhang <robinx.zhang@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>

net/e1000: fix Rx error counter for bad length

When the size of a packet in Rx channel is less than the minimum
or greater than the maximum, the packet will be simultaneously
counted by RLEC(Receive Length Error Count) and
RUC(Receive Under Size Count)/ROC(Receive Oversize Count) registers.

This patch fixes the issue of counting a length error packet twice
when counting the total number of received error packets.

Fixes: 70bdb18657da ("ethdev: add Rx error counters for missed, badcrc and badlen packets")
Cc: stable@dpdk.org
Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com>
Acked-by: Haiyue Wang <haiyue.wang@intel.com>

net/igc: fix Rx error counter for bad length

When the size of a packet in Rx channel is less than the minimum
or greater than the maximum, the packet will be simultaneously
counted by RLEC(Receive Length Error Count) and
RUC(Receive Under Size Count)/ROC(Receive Oversize Count) registers.

This patch fixes the issue of counting a length error packet twice
when counting the total number of received error packets.

Fixes: e6defdfddc3b ("net/igc: enable statistics")
Cc: stable@dpdk.org
Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com>
Acked-by: Haiyue Wang <haiyue.wang@intel.com>

net/ena: fix releasing Tx ring mbufs

When ena_tx_queue_release_bufs() frees the mbufs it does not clear
the mbuf pointers.  So, when the device starts and stops multiple
times it can cause the application to receive duplicate mbufs for
two different packets.  Fix the issue by clearing the mbuf pointer.

Also, while tracking down the "double free" issue the ena calls to
allocate and free mbufs in bulk were migrated to the mbuf based APIs
so the common mbuf alloc/free routines are exercised.

Fixes: 79405ee17585 ("net/ena: fix out of order completion")
Fixes: 1173fca25af9 ("ena: add polling-mode driver")
Cc: stable@dpdk.org
Signed-off-by: David Harton <dharton@cisco.com>
Acked-by: Michal Krawczyk <mk@semihalf.com>

net/ice: disable DDP package on Windows

Disable loading of external DDP package as it is not
supported on Windows.

Signed-off-by: Pallavi Kadam <pallavi.kadam@intel.com>
Reviewed-by: Ranjit Menon <ranjit.menon@intel.com>
Acked-by: Jie Zhou <jizh@microsoft.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>

net/ice: build on Windows

- Add Intel ice PMD support on Windows.
- Remove #include sys/ioctl header file as it is not needed.
- Replace x86intrin.h with rte_vect.h to avoid __m_prefetchw conflicting
  types.
- Replace POSIX usleep() API with rte API.
- Add a new macro for the access() API as the original function
  has been deprecated on Windows.
- Add extra cflags '-fno-asynchronous-unwind-tables'
  to avoid MinGW build error:
  Error: invalid register for .seh_savexmm
- Add documentation to support ice PMD on Windows.
  Update the release notes and features list for the same.

Signed-off-by: Pallavi Kadam <pallavi.kadam@intel.com>
Reviewed-by: Ranjit Menon <ranjit.menon@intel.com>
Acked-by: Jie Zhou <jizh@microsoft.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>

common/iavf: build on Windows

Enable IAVF driver to build on Windows as it is required
to build ice PMD.
Disable all other drivers from common directory.

This patch also includes fix for a macro redefinition warning
in the IAVF driver.

Signed-off-by: Pallavi Kadam <pallavi.kadam@intel.com>
Reviewed-by: Ranjit Menon <ranjit.menon@intel.com>
Acked-by: Jie Zhou <jizh@microsoft.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>

net/hns3: update HiSilicon copyright syntax

According to the suggestion of our legal department,
to standardize the copyright license of our code to
avoid potential copyright risks, we make a unified
modification to the "Hisilicon", which was nonstandard,
in the main modules we maintain.

We change it to "HiSilicon", which is consistent with
the terms used on the following official website:
https://www.hisilicon.com/en/terms-of-use.

Fixes: 565829db8b8f ("net/hns3: add build and doc infrastructure")
Fixes: 952ebacce4f2 ("net/hns3: support SVE Rx")
Fixes: e31f123db06b ("net/hns3: support NEON Tx")
Fixes: c09c7847d892 ("net/hns3: support traffic management")
Cc: stable@dpdk.org
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>

net/hns3: support IEEE 1588 PTP

Add hns3 support for new ethdev APIs to enable and read IEEE1588/
802.1AS PTP timestamps.

Signed-off-by: Min Hu (Connor) <humin29@huawei.com>

net/hns3: fix MTU config complexity

This patch fixed cyclomatic complexity about MTU
in device configure process.

Fixes: 1f5ca0b460cd ("net/hns3: support some device operations")
Cc: stable@dpdk.org
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>

net/igc: refine debug build option

1. replace RTE_LIBRTE_IGC_DEBUG_RX with RTE_ETHDEV_DEBUG_RX.
2. replace RTE_LIBRTE_IGC_DEBUG_TX with RTE_ETHDEV_DEBUG_TX.
3. merge RTE_LIBRTE_ETHDEV_DEBUG into RTE_ETHDEV_DEBUG_TX

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>

net/ixgbe: refine debug build option

1. replace RTE_LIBRTE_IXGBE_DEBUG_RX with RTE_ETHDEV_DEBUG_RX.
2. replace RTE_LIBRTE_IXGBE_DEBUG_TX with RTE_ETHDEV_DEBUG_TX.
3. merge RTE_LIBRTE_IXGBE_DEBUG_TX_FREE and RTE_LIBRTE_ETHDEV_DEBUG
   into RTE_ETHDEV_DEBUG_TX

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>

net/ice: refine debug build option

1. replace RTE_LIBRTE_ICE_DEBUG_RX with RTE_ETHDEV_DEBUG_RX.
2. replace RTE_LIBRTE_ICE_DEBUG_TX with RTE_ETHDEV_DEBUG_TX.
3. merge RTE_LIBRTE_ICE_DEBUG_TX_FREE and RTE_LIBRTE_ETHDEV_DEBUG
   into RTE_LIBRTE_DEBUG_TX

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>

net/iavf: refine debug build option

1. replace RTE_LIBRTE_IAVF_DEBUG_RX with RTE_ETHDEV_DEBUG_RX.
2. replace RTE_LIBRTE_IAVF_DEBUG_TX with RTE_ETHDEV_DEBUG_TX.
3. merge RTE_LIBRTE_IAVF_DEBUG_TX_FREE and RTE_LIBRTE_ETHDEV_DEBUG
   into RTE_ETHDEV_DEBUG_TX

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>

net/i40e: refine debug build option

1. replace RTE_LIBRTE_I40E_DEBUG_RX with RTE_ETHDEV_DEBUG_RX.
2. replace RTE_LIBRTE_I40E_DEBUG_TX with RTE_ETHDEV_DEBUG_TX.
3. merge RTE_LIBRTE_I40E_DEBUG_TX_FREE and RTE_LIBRTE_ETHDEV_DEBUG
   into RTE_ETHDEV_DEBUG_TX

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>

net/e1000: refine debug build option

1. replace RTE_LIBRTE_E1000_DEBUG_RX with RTE_ETHDEV_DEBUG_RX.
2. replace RTE_LIBRTE_E1000_DEBUG_TX with RTE_ETHDEV_DEBUG_TX.
3. merge RTE_LIBRTE_E1000_DEBUG_TX_FREE and RTE_LIBRTE_ETHDEV_DEBUG
   into RTE_ETHDEV_DEBUG_TX

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>

net/fm10k: refine debug build option

1. replace RTE_LIBRTE_FM10K_DEBUG_RX with RTE_ETHDEV_DEBUG_RX.
2. replace RTE_LIBRTE_FM10K_DEBUG_TX with RTE_ETHDEV_DEBUG_TX.
3. merge RTE_LIBRTE_FM10K_DEBUG_TX_FREE and RTE_LIBRTE_ETHDEV_DEBUG
   into RTE_ETHDEV_DEBUG_TX

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>

ethdev: refine debug build option

PMDs use RTE_LIBRTE_<PMD_NAME>_DEBUG_RX|TX as build option to wrap
data path debug code. As .config has been removed since the meson build,
It is not friendly for new DPDK users to notice those debug options.

The patch introduces below build options for data path debug, so PMD
can choose to reuse them to avoid maintain their own.

- RTE_ETHDEV_DEBUG_RX
- RTE_ETHDEV_DEBUG_TX

All the build options are documented at programming guide
"3.1 Driver Option", so users can easily find them.

The original undocumented RTE_LIBRTE_ETHDEV_DEBUG will alias to
both RTE_ETHDEV_DEBUG_RX and RTE_ETHDEV_DEBUG_TX for backward
compatibility.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>

drivers/net: remove useless autoneg capability

The flag ETH_LINK_SPEED_AUTONEG is 0,
so it cannot be used in a capability bitmap.

Having 0 in speed capability means all speeds are accepted.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>

doc: add sampling and mirroring in testpmd guide

Update documentation for sample action usage in testpmd and
show the command line example.

Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>

mempool/cnxk: add cn10k batch dequeue

Add the implementation for Marvell CN10k mempool batch dequeue op.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>

mempool/cnxk: add cn10k get count

Add the implementation for Marvell CN10k get count op.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>

mempool/cnxk: add cn10k batch enqueue

Add the implementation for Marvell CN10k mempool batch enqueue op.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>

mempool/cnxk: add batch operation init

Marvell CN10k mempool supports batch enqueue/dequeue which can
dequeue up to 512 pointers and enqueue up to 15 pointers using
a single instruction.

These batch operations require a DMA memory to enqueue/dequeue
pointers. This patch adds the initialization of this DMA memory.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>

mempool/cnxk: add cn10k mempool operations

Add Marvell CN10k mempool ops and implement CN10k mempool alloc.

CN10k has 64 bytes L1D cache line size. Hence the CN10k mempool
alloc does not make the element size an odd multiple L1D cache
line size as NPA requires the element sizes to be multiples of
128 bytes.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>

mempool/cnxk: add cn9k optimized enqueue/dequeue

Add Marvell CN9k mempool enqueue/dequeue. Marvell CN9k
supports burst dequeue which allows to dequeue up to 32
pointers using pipelined casp instructions.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>

mempool/cnxk: add cn9k mempool operations

Add Marvell CN9k mempool ops and implement CN9k mempool
alloc which makes sure that the element size always occupy
odd number of cachelines to ensure even distribution among
of elements among L1D cache sets.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>

mempool/cnxk: register plt init callback

Register the CNXk mempool plt init callback which will set the
appropriate mempool ops to be used for the platform.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>

mempool/cnxk: add generic operations

Add generic CNXk mempool ops which will enqueue/dequeue
from pool one element at a time.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>

mempool/cnxk: add device probe/remove

Add the implementation for CNXk mempool device
probe and remove.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>

mempool/cnxk: add build infra and doc

Add the meson based build infrastructure for Marvell
CNXK mempool driver along with stub implementations
for mempool device probe.

Also add Marvell CNXK mempool base documentation.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>

common/cnxk: support RSS action in NPC rule

Added support for allocating RSS group and setting
it as action of an NPC rule.

Signed-off-by: Satheesh Paul <psatheesh@marvell.com>

common/cnxk: support TIM IRQ

Add TIM LF IRQ register and un-register functions.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: support TIM device

Add TIM device init, fini which are used to attach TIM LF
resources to the RVU PF/VF and TIM LF alloc and free.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: support SSO debug

Add sso debug dump support. This dumps all SSO LF register values
to a given file handle.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: support SSO IRQ

Add support to registering and un-registering SSO HWS and
HWGRP IRQs.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: add SSO HWGRP interface

Add SSO HWGRP interface for configuring XAQ pool, setting priority
and internal HW buffer limits for each HWGRP.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: add SSO HWS interface

Add SSO HWS interface for setting/unsetting links, retrieving
base address and nanoseconds to getwork timeout.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: support SSO device

Add SSO device init and fini which attach SSO LF resources to the
RVU PF/VF and SSO HWS and HWGRP LFs alloc, free.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: add NPC init and fini

Adding support initialize and fini the npc. Further, adding APIs to
create and destroy the npc rules.

Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>

common/cnxk: add NPC parsing API

Adding npc parsing API support to parse different patterns and actions.
Based on the pattern and actions ltype values will be chosen and
mcam data will be configured at perticular offsets.

Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>

common/cnxk: add mcam utility API

Adding mcam utility functions like reading KEX and reserving and writing
mcam rules.

Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>

common/cnxk: add NPC helper API

Adding NPC helper APIs to manage MCAM like pre allocating the mcam,
configuring the rules, shifting mcam rules and preparing the data for
mcam based on KEX.

Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>

common/cnxk: support NPC

Adding initial support for programming NPC. NPC is Network Parser
and CAM unit that provides Rx and Tx packet parsing and packet
manipulation functionality on Marvell CN9K and CN10K SoC's. It is
mapped to RTE Flow in DPDK.

Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>

common/cnxk: support NIX TM debug and misc utils

Add support to dump TM HW registers and hierarchy on error.
This patch also adds support for misc utils such as API to
query TM HW resource availability, resource pre-allocation
and static priority support on root node.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: support NIX TM dynamic update

Add support for dynamic node update of shaper profile,
RR quantum and also support to suspend or resume an active
TM node.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: support NIX TM internal hierarchy

Add support to create internal TM default hierarchy and ratelimit
hierarchy and API to ratelimit SQ to a given rate. This will be
used by cnxk ethdev driver's tx queue ratelimit op.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: add NIX TM hierarchy enable/disable

Add support to enable or disable hierarchy along with
allocating node HW resources such as shapers and schedulers
and configuring them to match the user created or default
hierarchy.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: add NIX TM helper to alloc/free resource

Add TM helper API to estimate, alloc, assign, and free resources
for a NIX LF / ethdev.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: support NIX TM shaper profile

Add support to add/delete/update shaper profile for
a given NIX. Also add support to walk through existing
shaper profiles.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Satha Rao <skoteshwar@marvell.com>

common/cnxk: support add/delete NIX TM node

Add support to add/delete nodes in a hierarchy.
This patch also adds misc utils to get node name,
walk through nodes etc.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Satha Rao <skoteshwar@marvell.com>

common/cnxk: support NIX traffic management

Add nix traffic management base support to init/fini node, shaper profile
and topology, setup SQ for a given user hierarchy or default internal
hierarchy.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: support NIX LSO and misc utils

Add support to create LSO formats for TCP segmentation offload
for IPv4/IPv6, tunnel and non-tunnel protocols. Tunnel protocol
support is for GRE and UDP based tunnel protocols.

This patch also adds other helper API to retrieve eeprom info
and configure Rx for different switch headers.

Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: support NIX flow control

Add support to enable/disable Rx/Tx flow control and pause
frame configuration on NIX.

Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: suport VLAN filter

Add helper API to support VLAN filtering and stripping
on Rx and VLAN insertion on Tx.

Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: support NIX debug dump

Add support to dump NIX RQ, SQ and CQ contexts apart
from NIX LF registers.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: support NIX extended stats

Add support for retrieving NIX extended stats that are
per NIX LF and per LMAC.

Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: support NIX stats

Add API to provide Rx and Tx stats for a given NIX.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: support NIX PTP

Add support to enable/disable Rx and Tx PTP timestamping
support. Also provide API's to register ptp info callbacks
to get config change update from Kernel.

Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: support NIX RSS

Add API's for default/non-default reta table setup,
key set/get, and flow algo setup for CN9K and CN10K.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: add NIX inline IPsec config API

Add API to configure NIX block for inline IPSec.

Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: add NIX specific NPC operations

Add NIX specific NPC operations such as NPC mac address get/set,
mcast entry add/delete, promiscuous mode enable/disable etc.

Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: support NIX MAC operations

Add support to different MAC related operations such as
MAC address set/get, link set/get, link status callback,
etc.

Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: add NIX Tx queue management API

This patch adds support to init/modify/fini NIX
SQ(send queue) for both CN9K and CN10K platforms.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: add NIX Rx queue management API

Add nix Rx queue management API to init/modify/fini
RQ context and also setup CQ(completion queue) context.
Current support is both for CN9K and CN10K devices.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: support NIX IRQ

Add support to register NIX error and completion
queue IRQ's using base device class IRQ helper API's.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Signed-off-by: Harman Kalra <hkalra@marvell.com>

common/cnxk: support NIX

Add base nix support as ROC(Rest of Chip) API which will
be used by generic ETHDEV PMD(net/cnxk).

This patch adds support to device init, fini, resource
alloc and free API which sets up a ETHDEV PCI device of either
CN9K or CN10K Marvell SoC.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Signed-off-by: Satha Rao <skoteshwar@marvell.com>

common/cnxk: support NPA batch alloc/free

Add APIs to do allocations/frees in batch from
NPA pool.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: support NPA performance counter

Add APIs to read NPA performance counters.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: support NPA bulk alloc/free

Add APIs to alloc/free in bulk from NPA pool.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: add NPA pool HW operations

Add APIs for creating, destroying, modifying
NPA pools.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: support NPA debug

Add NPA debug APIs.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: support NPA IRQ

Add support for NPA IRQs.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: support NPA device

Add base NPA device support. NPA i.e Network Pool Allocator is
HW block that provides HW mempool functionality on Marvell CN9K
and CN10K SoC's. NPA by providing HW mempool support, also
facilitates Rx and Tx packet alloc and packet free by HW without
SW intervention.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: add VF support to base device class

Add VF specific handling such as BAR4 setup, forwarding
VF mbox messages to AF and vice-versa, VF FLR handling
etc.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: add base device class

Introduce 'dev' class to hold cnxk PCIe device specific
information and operations.

All PCIe drivers(ethdev, mempool, cryptodev and eventdev) of cnxk
inherits this base object to avail the common functionalities such
as mailbox creation, interrupt registration, LMT setup, VF message
mbox forwarding, etc.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: add mailbox base infrastructure

This patch adds mailbox infra API's to communicate with Kernel AF
driver. These API's will be used by all the other cnxk drivers
for mbox init/fini, send/recv functionality.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: add mbox request and response definitions

The admin function driver sits in Linux kernel as mailbox
server. The DPDK AF mailbox client, send the message to mailbox
server to complete the administrative task such as get mac
address.

This patch adds mailbox request and response definition of
existing mailbox defined between AF driver and DPDK driver.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Signed-off-by: Shijith Thotton <sthotton@marvell.com>

common/cnxk: add interrupt helper API

Add interrupt helper API's in common code to register and
unregister for specific interrupt vectors. These API's
will be used by all cnxk drivers.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: add roc plt init callback support

Add support for registering callbacks for roc plt init.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

common/cnxk: add model init and IO handling API

Add routines for SoC model identification and HW IO handling
routines specific to CN9K and CN10K Marvell SoC's.
These are based on arm64 ISA and behaviour specific to
Marvell SoC's.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>