dpdk.git
3 years agonet/ice: fix memzone leak after device init failure
Haiyue Wang [Fri, 13 Aug 2021 06:21:54 +0000 (14:21 +0800)]
net/ice: fix memzone leak after device init failure

When flow engine initialization or FXP resource reset failed, it needs
to free the memory zone and unregister the interrupt callback.

Bugzilla ID: 752
Fixes: 84dc7a95a2d3 ("net/ice: enable flow director engine")
Fixes: 7615a6895009 ("net/ice: rework for generic flow enabling")
Fixes: 7edc7158d771 ("net/ice: cleanup RSS/FDIR profile on device init")
Cc: stable@dpdk.org
Reported-by: David Marchand <david.marchand@redhat.com>
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
3 years agonet/ice/base: support flow director for IPv6 fragments
Wenjun Wu [Tue, 3 Aug 2021 07:23:54 +0000 (15:23 +0800)]
net/ice/base: support flow director for IPv6 fragments

Add L2 and L3 FDIR field support for IPv6 fragment packets.

Signed-off-by: Wenjun Wu <wenjun1.wu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
3 years agomaintainers: update for mlx4/mlx5 net drivers
Viacheslav Ovsiienko [Mon, 23 Aug 2021 14:50:41 +0000 (17:50 +0300)]
maintainers: update for mlx4/mlx5 net drivers

For net/mlx4:
    - removing Shahaf Shuler
    - adding Viacheslav Ovsiienko

For net/mlx5:
    - removing Shahaf Shuler

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/nfp: fix minimum descriptor sizes
Heinrich Kuhn [Mon, 23 Aug 2021 07:59:21 +0000 (09:59 +0200)]
net/nfp: fix minimum descriptor sizes

The NFP4000/6000 supports a minimum of 256 Tx/Rx descriptors and not 64.
Before this patch when a DPDK application configured < 256 Tx
descriptors the hardware read/write pointers would be unmasked and not
wrapped at the expected size of the ring. The PMD logic to determine the
amount of free space in the Tx ring is incompatible with the unmasked
hwqueue pointers and this will result in the PMD not updating the
read pointer at all.The knock-on effect is that under high load the
PMD will potentially re-use a Tx descriptor before the hw has had a
chance to process that particular descriptor. This issue can manifest as
a DMA error when the hardware tries to perform a DMA with info from a
partially populated descriptor.

Fixes: defb9a5dd156 ("nfp: introduce driver initialization")
Cc: stable@dpdk.org
Signed-off-by: Heinrich Kuhn <heinrich.kuhn@corigine.com>
Signed-off-by: Simon Horman <simon.horman@corigine.com>
3 years agomaintainers: update for NFP
Heinrich Kuhn [Mon, 23 Aug 2021 08:29:19 +0000 (10:29 +0200)]
maintainers: update for NFP

Some of Netronome's activities and people have moved over to Corigine,
including NFP PMD maintenance and myself.

Signed-off-by: Heinrich Kuhn <heinrich.kuhn@corigine.com>
3 years agoapp/testpmd: add option for number of flows in flowgen
Zhihong Wang [Thu, 19 Aug 2021 12:35:41 +0000 (20:35 +0800)]
app/testpmd: add option for number of flows in flowgen

Make number of flows in flowgen configurable by setting parameter
--flowgen-flows=N.

Signed-off-by: Zhihong Wang <wangzhihong.wzh@bytedance.com>
Acked-by: Xiaoyun Li <xiaoyun.li@intel.com>
3 years agonet/ipn3ke: change experimental symbol to internal
Rosen Xu [Thu, 19 Aug 2021 06:05:05 +0000 (14:05 +0800)]
net/ipn3ke: change experimental symbol to internal

'ipn3ke_bridge_func' is a global variable and it used in net & raw
drivers.
It's only used for drivers, so change it from EXPERIMENTAL to INTERNAL.

Signed-off-by: Rosen Xu <rosen.xu@intel.com>
Acked-by: Ferruh Yigit <ferruh.yigit@intel.com>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
3 years agocrypto/dpaa_sec: support PDCP short MAC-I
Gagandeep Singh [Wed, 8 Sep 2021 12:51:27 +0000 (18:21 +0530)]
crypto/dpaa_sec: support PDCP short MAC-I

This patch add PDCP security short MAC-I support for
dpaa_sec driver.

Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocrypto/dpaa2_sec: support PDCP short MAC-I
Gagandeep Singh [Wed, 8 Sep 2021 12:51:26 +0000 (18:21 +0530)]
crypto/dpaa2_sec: support PDCP short MAC-I

This patch add PDCP short mac support in dpaa2_sec driver.

Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agotest/crypto: support PDCP short MAC-I
Gagandeep Singh [Wed, 8 Sep 2021 12:51:25 +0000 (18:21 +0530)]
test/crypto: support PDCP short MAC-I

This patch add support to test the PDCP short MAC
packets in crypto.

Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agosecurity: support PDCP short MAC-I
Hemant Agrawal [Wed, 8 Sep 2021 12:51:24 +0000 (18:21 +0530)]
security: support PDCP short MAC-I

This patch add support to handle PDCP short MAC-I domain
along with standard control and data domains as it has to
be treaty as special case with PDCP protocol offload support.

ShortMAC-I is the 16 least significant bits of calculated MAC-I. Usually
when a RRC message is exchanged between UE and eNodeB it is integrity &
ciphered protected.

MAC-I = f(key, varShortMAC-I, count, bearer, direction).
Here varShortMAC-I is prepared by using (current cellId, pci of source cell
and C-RNTI of old cell). Other parameters like count, bearer and
direction set to all 1.

crypto-perf app is updated to take short MAC as input mode.

Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocrypto/dpaa2_sec: support integrity only PDCP
Hemant Agrawal [Wed, 8 Sep 2021 12:51:23 +0000 (18:21 +0530)]
crypto/dpaa2_sec: support integrity only PDCP

To support short MAC-I, integrity only case is required
to be supported for PDCP.

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
3 years agocommon/cnxk: fix attaching NPA LF to CPT VF
Srujana Challa [Wed, 18 Aug 2021 11:56:35 +0000 (17:26 +0530)]
common/cnxk: fix attaching NPA LF to CPT VF

ATTACH_RESOURCES mailbox for CPT LFs is being called without
setting modify bit. Because of this previously attached NPA LF
to the CPT VF is getting removed, when only CPT VF is whitelisted.
This patch fixes the same.

Fixes: c045d2e5cbbc ("common/cnxk: add CPT configuration")
Cc: stable@dpdk.org
Signed-off-by: Srujana Challa <schalla@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocrypto/dpaa2_sec: add error packet counters
Hemant Agrawal [Wed, 8 Sep 2021 06:59:53 +0000 (12:29 +0530)]
crypto/dpaa2_sec: add error packet counters

This patch add support to also counter err pkt counter per queue.
This also enhances few related debug prints.

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocrypto/dpaa_sec: force inline keys to save space
Franck Lenormand [Wed, 8 Sep 2021 06:59:52 +0000 (12:29 +0530)]
crypto/dpaa_sec: force inline keys to save space

This patch improve storage and performance by force inline
of the keys.

Signed-off-by: Franck Lenormand <franck.lenormand@nxp.com>
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocommon/dpaax/caamflib: fix IV for short MAC-I in SNOW3G
Gagandeep Singh [Wed, 8 Sep 2021 06:59:51 +0000 (12:29 +0530)]
common/dpaax/caamflib: fix IV for short MAC-I in SNOW3G

The logic was incorrectly doing conditional swap. It need to
be bit swap always.

Fixes: 73a24060cd70 ("crypto/dpaa2_sec: add sample PDCP descriptor APIs")
Cc: stable@dpdk.org
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocommon/dpaax/caamflib: remove some inline keys
Franck Lenormand [Wed, 8 Sep 2021 06:59:50 +0000 (12:29 +0530)]
common/dpaax/caamflib: remove some inline keys

The space in descriptor buffer is scarce as it is limited to
64 words for platforms except ERA10 (which has 128).

As the descriptors are processed with QI, it adds some words
to the descriptor which is passed.

Some descriptors used for SDAP were using too much words reaching
the limit.

This patch reduces the number of words used by removing the inlining
of some keys (done for performance) in order to have working
descriptors.

Signed-off-by: Franck Lenormand <franck.lenormand@nxp.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocommon/dpaax/caamflib: remove DPOVRD clear for SDAP
Franck Lenormand [Wed, 8 Sep 2021 06:59:49 +0000 (12:29 +0530)]
common/dpaax/caamflib: remove DPOVRD clear for SDAP

For SDAP, we are not using the protocol operation to perform
4G/LTE operation so the DPOVRD option is not used.

Removing it save some space in the descriptor buffer and
execution time.

Signed-off-by: Franck Lenormand <franck.lenormand@nxp.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocommon/dpaax/caamflib: load correct HFN from desc buffer
Franck Lenormand [Wed, 8 Sep 2021 06:59:48 +0000 (12:29 +0530)]
common/dpaax/caamflib: load correct HFN from desc buffer

The offset of the HFN word and Bearer/Dir word is different
depending on type of PDB.

The wrong value was used.

This patch address this issue

Signed-off-by: Franck Lenormand <franck.lenormand@nxp.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocrypto/dpaa_sec: support AES-CMAC integrity check
Gagandeep Singh [Wed, 8 Sep 2021 06:59:47 +0000 (12:29 +0530)]
crypto/dpaa_sec: support AES-CMAC integrity check

This patch adds support for AES_CMAC integrity
in non-security mode.

Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocrypto/dpaa_sec: support AES-XCBC-MAC
Gagandeep Singh [Wed, 8 Sep 2021 06:59:46 +0000 (12:29 +0530)]
crypto/dpaa_sec: support AES-XCBC-MAC

This patch adds support for AES-XCBC-MAC algo.

Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocrypto/dpaa_sec: support non-HMAC auth algos
Gagandeep Singh [Wed, 8 Sep 2021 06:59:45 +0000 (12:29 +0530)]
crypto/dpaa_sec: support non-HMAC auth algos

This patch add support for non-HMAC, md5, shax algos.

Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocrypto/dpaa_sec: support DES-CBC
Gagandeep Singh [Wed, 8 Sep 2021 06:59:44 +0000 (12:29 +0530)]
crypto/dpaa_sec: support DES-CBC

add DES-CBC support and enable available cipher-only
test cases.

Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocryptodev: expose driver interface as internal
Akhil Goyal [Tue, 10 Aug 2021 19:50:20 +0000 (01:20 +0530)]
cryptodev: expose driver interface as internal

The rte_cryptodev_pmd.* files are for drivers only and should be
private to DPDK, and not installed for app use.

Signed-off-by: Akhil Goyal <gakhil@marvell.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
3 years agoexamples/fips_validation: remove illegal usage of API
Akhil Goyal [Tue, 10 Aug 2021 19:50:19 +0000 (01:20 +0530)]
examples/fips_validation: remove illegal usage of API

Some of the cryptodev APIs are not allowed to be used
by application directly. Hence removing the usage of
1. queue_pair_release: it is not required, as configure
   of queue pair release the previous queue pairs and the
   dev is not directly exposed to application, hence cannot
   use its ops from app.
2. rte_cryptodev_stop: it can be used directly without
   checking if the device is started or not.
3. rte_cryptodev_pmd_destroy: application should use
   rte_cryptodev_close instead.

Signed-off-by: Akhil Goyal <gakhil@marvell.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
3 years agocryptodev: rename function to check device validity
Akhil Goyal [Tue, 10 Aug 2021 19:50:18 +0000 (01:20 +0530)]
cryptodev: rename function to check device validity

The API rte_cryptodev_pmd_is_valid_dev, can be used
by the application as well as PMD to check whether
the device is valid or not. Hence, _pmd is removed
from the API.
The applications and drivers which use this API are
also updated.

Signed-off-by: Akhil Goyal <gakhil@marvell.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
3 years agotest/crypto: remove illegal PMD header include
Akhil Goyal [Tue, 10 Aug 2021 19:50:17 +0000 (01:20 +0530)]
test/crypto: remove illegal PMD header include

rte_cryptodev_pmd.h is an interface between
driver and library and it is mentioned in the
file that application cannot use it directly.
Hence, removing the include.

Signed-off-by: Akhil Goyal <gakhil@marvell.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
3 years agocrypto/cnxk: add feature flag for cn9k lookaside IPsec
Archana Muniganti [Tue, 7 Sep 2021 14:21:03 +0000 (19:51 +0530)]
crypto/cnxk: add feature flag for cn9k lookaside IPsec

Update device feature flag to support lookaside IPsec for
cn9k.

Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Archana Muniganti <marchana@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
3 years agocrypto/cnxk: update tailroom requirement
Archana Muniganti [Tue, 7 Sep 2021 14:21:02 +0000 (19:51 +0530)]
crypto/cnxk: update tailroom requirement

Update min tailroom to reflect IPsec additions.
PMD crypto_cn9k & crypto_cn10k would have packet
grow into tailroom post IPsec processing.

Signed-off-by: Archana Muniganti <marchana@marvell.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
3 years agocrypto/cnxk: add cn9k lookaside IPsec datapath
Archana Muniganti [Tue, 7 Sep 2021 14:21:01 +0000 (19:51 +0530)]
crypto/cnxk: add cn9k lookaside IPsec datapath

Adds support for cn9k lookaside enqueue and dequeue
operations.

Signed-off-by: Archana Muniganti <marchana@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
3 years agocrypto/cnxk: add cn9k security session operations
Archana Muniganti [Tue, 7 Sep 2021 14:21:00 +0000 (19:51 +0530)]
crypto/cnxk: add cn9k security session operations

Add security session ops.

Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Archana Muniganti <marchana@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
3 years agocommon/cnxk: add cn9k IPsec microcode defines
Archana Muniganti [Tue, 7 Sep 2021 14:20:59 +0000 (19:50 +0530)]
common/cnxk: add cn9k IPsec microcode defines

Microcode IE opcodes support IPsec operations. Add defines
and structs defined by microcode.

Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Archana Muniganti <marchana@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
3 years agocrypto/cnxk: add cn9k security context
Archana Muniganti [Tue, 7 Sep 2021 14:20:58 +0000 (19:50 +0530)]
crypto/cnxk: add cn9k security context

Add security ctx in cn9k crypto PMD.

Signed-off-by: Archana Muniganti <marchana@marvell.com>
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
3 years agocrypto/openssl: fix CCM processing 0 length source
Ciara Power [Mon, 23 Aug 2021 12:47:14 +0000 (12:47 +0000)]
crypto/openssl: fix CCM processing 0 length source

When given a source length 0 for CCM, the encryption and decryption
functions did not call the EVP_ENCRYPTUPDATE/EVP_DECRYPTUPDATE functions
with a src and dst, causing some FIPS validation failures for testcases
with PLen=0:

process_openssl_auth_encryption_ccm() line 1131:
Process openssl auth encryption ccm failed

Fixes: 1a4998dc4d94 ("crypto/openssl: support AES-CCM")
Cc: stable@dpdk.org
Signed-off-by: Ciara Power <ciara.power@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
3 years agotest/crypto: refactor scheduler workers init
Rebecca Troy [Thu, 2 Sep 2021 11:54:16 +0000 (11:54 +0000)]
test/crypto: refactor scheduler workers init

Previously, the scheduler unit test only created and attached 1 or 2
AESNI-MB cryptodev PMDs as workers if less than 2 AESNI-MB PMDs had
already been initialized.

This commit changes this to always create and attach 2 new AESNI-MB
cryptodev PMDs, regardless of previously initialized AESNI-MB PMDs.

Signed-off-by: Rebecca Troy <rebecca.troy@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
3 years agoconfig/ppc: ignore GCC 11 psabi warnings
David Christensen [Thu, 2 Sep 2021 23:53:26 +0000 (16:53 -0700)]
config/ppc: ignore GCC 11 psabi warnings

Suppress the gcc warning "note: the layout of aggregates containing
vectors with 4-byte alignment has changed in GCC 5" on POWER systems
by setting "-Wno-psabi".  Warning was originally added to gcc in
commit https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=9832651 to warn
of the vector alignment changes introduced in GCC 5.  Older gcc
versions forced vector alignment to 16 bytes due to requirements for
POWER 6 and earlier CPUs, but these restrictions don't apply to CPUs
supported by DPDK.

Bugzilla ID: 739
Cc: stable@dpdk.org
Signed-off-by: David Christensen <drc@linux.vnet.ibm.com>
3 years agoeal/ppc: ignore GCC 10 stringop-overflow warnings
David Christensen [Thu, 2 Sep 2021 22:15:14 +0000 (15:15 -0700)]
eal/ppc: ignore GCC 10 stringop-overflow warnings

Suppress gcc warning "warning: writing 16 bytes into a region of
size 0" for users of the POWER rte_memcpy() function.  Existing
rte_memcpy() code takes different code paths based on the actual
size of the move so the warning is already addressed. See also
commit b5b3ea803e47 ("eal/x86: ignore gcc 10 stringop-overflow warnings")

Cc: stable@dpdk.org
Signed-off-by: David Christensen <drc@linux.vnet.ibm.com>
3 years agocrypto/cnxk: add dual submission in cn9k
Anoob Joseph [Thu, 2 Sep 2021 12:22:34 +0000 (17:52 +0530)]
crypto/cnxk: add dual submission in cn9k

Submit two instructions with one LMTST operation.
Also updated dequeue path to have local var for constants.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocrypto/cnxk: support ucode API change
Vidya Sagar Velumuri [Thu, 2 Sep 2021 12:22:33 +0000 (17:52 +0530)]
crypto/cnxk: support ucode API change

Add support for API changes in ucode 1.13

Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocrypto/cnxk: remove redundant assignment
Anoob Joseph [Thu, 2 Sep 2021 12:22:32 +0000 (17:52 +0530)]
crypto/cnxk: remove redundant assignment

The assignment to -1 is not required. Remove the same.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocrypto/cnxk: remove redundant memcpy of IV for ZUC
Anoob Joseph [Thu, 2 Sep 2021 12:22:31 +0000 (17:52 +0530)]
crypto/cnxk: remove redundant memcpy of IV for ZUC

Swap is not required for ZUC. Update IV updation
sequence to remove the redundant swap in case of ZUC.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocrypto/cnxk: remove redundant SNOW3G decrypt
Anoob Joseph [Thu, 2 Sep 2021 12:22:30 +0000 (17:52 +0530)]
crypto/cnxk: remove redundant SNOW3G decrypt

The opcode for encryption & decryption is the
same and single routine would be able to handle
both encryption and decryption operations.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocommon/cnxk: update to v1.16 ucc codes
Anoob Joseph [Thu, 2 Sep 2021 12:22:29 +0000 (17:52 +0530)]
common/cnxk: update to v1.16 ucc codes

Update to v1.16 microcode completion codes.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocommon/cnxk: update to v1.13 ZUC API
Vidya Sagar Velumuri [Thu, 2 Sep 2021 12:22:28 +0000 (17:52 +0530)]
common/cnxk: update to v1.13 ZUC API

Add support for ZUC API change in ucode 1.13

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocrypto/mlx5: fix timestamp format configuration
Michael Baum [Sun, 5 Sep 2021 08:04:15 +0000 (11:04 +0300)]
crypto/mlx5: fix timestamp format configuration

This patch adds support for the timestamp format settings for
the receive and send queues. If the firmware version x.30.1000
or above is installed and the NIC timestamps are configured
with the real-time format, the default zero values for newly
added fields cause the queue creation to fail.

The patch queries the timestamp formats supported by the hardware
and sets the configuration values in queue context accordingly.

Fixes: 6152534e211e ("crypto/mlx5: support queue pairs operations")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agoevent/cnxk: add cn10k crypto adapter fast path
Shijith Thotton [Thu, 2 Sep 2021 14:41:56 +0000 (20:11 +0530)]
event/cnxk: add cn10k crypto adapter fast path

Set crypto adapter enqueue and dequeue operations for CN10K.

Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocrypto/cnxk: add cn10k crypto adapter fast path
Shijith Thotton [Thu, 2 Sep 2021 14:41:55 +0000 (20:11 +0530)]
crypto/cnxk: add cn10k crypto adapter fast path

Added crypto adapter enqueue and dequeue operations for CN10K.

Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
Acked-by: Anoob Joseph <anoobj@marvell.com>
3 years agoevent/cnxk: add cn9k crypto adapter fast path
Shijith Thotton [Thu, 2 Sep 2021 14:41:54 +0000 (20:11 +0530)]
event/cnxk: add cn9k crypto adapter fast path

Set crypto adapter enqueue and dequeue operations for CN9K.

Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocrypto/cnxk: add cn9k crypto adapter fast path
Shijith Thotton [Thu, 2 Sep 2021 14:41:53 +0000 (20:11 +0530)]
crypto/cnxk: add cn9k crypto adapter fast path

Added crypto adapter enqueue and dequeue operations for CN9K.

Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
Acked-by: Anoob Joseph <anoobj@marvell.com>
3 years agoevent/cnxk: add crypto adapter operations
Shijith Thotton [Thu, 2 Sep 2021 14:41:52 +0000 (20:11 +0530)]
event/cnxk: add crypto adapter operations

Added eventdev ops required to initialize crypto adapter.

Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocommon/cnxk: add function to check CPT IQ is full
Shijith Thotton [Thu, 2 Sep 2021 14:41:51 +0000 (20:11 +0530)]
common/cnxk: add function to check CPT IQ is full

Added flow control based check to determine CPT IQ is full.

Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agoevent/cnxk: add macros to set eventdev operations
Shijith Thotton [Thu, 2 Sep 2021 14:41:50 +0000 (20:11 +0530)]
event/cnxk: add macros to set eventdev operations

Added a common macro to set eventdev enqueue and
dequeue operations to reduce code.

Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agonet/cnxk: add flag to show CPT can enqueue events
Shijith Thotton [Thu, 2 Sep 2021 14:41:49 +0000 (20:11 +0530)]
net/cnxk: add flag to show CPT can enqueue events

CPT can be told to submit events to SSO upon completion.
Crypto adapter uses this feature and the new flag can be
used to optimize receive path in those cases.

Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocrypto/octeontx2: fix unaligned access to device memory
Danny Patel [Fri, 27 Aug 2021 05:33:58 +0000 (11:03 +0530)]
crypto/octeontx2: fix unaligned access to device memory

Use otx2_mbox_memcpy() instead of memcpy() to prevent unaligned access.

Fixes: a0645ed0d6ef ("crypto/octeontx2: discover capabilities")
Cc: stable@dpdk.org
Signed-off-by: Danny Patel <dannyp@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
3 years agocompress/mlx5: fix leak on QP setup failure
Michael Baum [Tue, 31 Aug 2021 20:39:41 +0000 (23:39 +0300)]
compress/mlx5: fix leak on QP setup failure

The QP setup function allocates buffer for its
opaque MR and register it into MR structure.

After buffer allocation and before MR registration,
it tries allocate MR Btree.
When the MR Btree allocation fails, the buffer was
not freed what caused a memory leak.

Allocate the MR Btree before buffer alloction.

Fixes: 0165bccdb45f ("compress/mlx5: add memory region management")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agocommon/cnxk: make IPsec defines common
Archana Muniganti [Wed, 1 Sep 2021 10:19:30 +0000 (15:49 +0530)]
common/cnxk: make IPsec defines common

Make IPsec defines common and remove redundant macros.

Signed-off-by: Archana Muniganti <marchana@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocrypto/cnxk: support cn10k transport mode
Tejasree Kondoj [Wed, 1 Sep 2021 10:19:28 +0000 (15:49 +0530)]
crypto/cnxk: support cn10k transport mode

Adding support for cn10k lookaside IPsec transport mode.

Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocrypto/cnxk: make IPsec verify functions common
Archana Muniganti [Wed, 1 Sep 2021 10:19:27 +0000 (15:49 +0530)]
crypto/cnxk: make IPsec verify functions common

IPsec verify functions can be made common which can
be used for both cn9k and cn10k

Signed-off-by: Archana Muniganti <marchana@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocrypto/cnxk: use rlen from CPT result with lookaside
Tejasree Kondoj [Wed, 1 Sep 2021 10:19:26 +0000 (15:49 +0530)]
crypto/cnxk: use rlen from CPT result with lookaside

Use rlen from CPT result with lookaside operations

Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocrypto/cnxk: remove redundant code
Tejasree Kondoj [Wed, 1 Sep 2021 10:19:25 +0000 (15:49 +0530)]
crypto/cnxk: remove redundant code

Removing redundant code in cn10k lookaside IPsec.

Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocrypto/cnxk: support lookaside IPsec
Tejasree Kondoj [Wed, 1 Sep 2021 10:19:24 +0000 (15:49 +0530)]
crypto/cnxk: support lookaside IPsec

Added lookaside IPsec AES-CBC-HMAC-SHA1
support to cnxk driver.

Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agocommon/cnxk: add hash generation API
Tejasree Kondoj [Wed, 1 Sep 2021 10:19:23 +0000 (15:49 +0530)]
common/cnxk: add hash generation API

Adding functions for hash generation that can be used
in hmac opad/ipad calculation.

Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
3 years agodevargs: parse global device syntax
Xueming Li [Tue, 13 Apr 2021 03:14:12 +0000 (03:14 +0000)]
devargs: parse global device syntax

When parsing a devargs, try to parse using the global device syntax
first. Fallback on legacy syntax on error.

Example of new global device syntax:
 -a bus=pci,addr=82:00.0/class=eth/driver=mlx5,dv_flow_en=1

Signed-off-by: Xueming Li <xuemingl@nvidia.com>
Reviewed-by: Gaetan Rivet <grive@u256.net>
3 years agobus: add device arguments name parsing
Xueming Li [Tue, 13 Apr 2021 03:14:11 +0000 (03:14 +0000)]
bus: add device arguments name parsing

For device probe and iterator, devargs name was key information,
parsed by rte_devargs_parse. In legacy parser, devargs name was
extracted after bus name:
  bus:name,kv_arguments,,,
Example:
  pci:83:00.0,arguments,...
  vdev:pcap0,...

To be compatible with legacy parser, this patch introduces new
bus driver API devargs_parse to parse devargs and update devargs name.
If devargs_parse not implemented by bus driver, the new syntax parser
rte_devargs_layers_parse default will resolve devargs name from bus's
"name" argument.

Different bus driver might choose different keys from arguments with
unified format. The PCI bus implementation fills the devargs name with
the "addr" argument, example:
 -a bus=pci,addr=83:00.0/class=eth/driver=mlx5,...
    name: 0000:03:00.0
 -a bus=vdev,name=pcap0/class=eth/driver=pcap,...
    name:pcap0

Signed-off-by: Xueming Li <xuemingl@nvidia.com>
Reviewed-by: Gaetan Rivet <grive@u256.net>
3 years agoapp/testpmd: fix dump of Tx offload flags
Nithin Dabilpuram [Mon, 16 Aug 2021 07:09:42 +0000 (12:39 +0530)]
app/testpmd: fix dump of Tx offload flags

Fix verbose mode dump for Tx to dump tx offload flags instead of
Rx offload flags.

Fixes: d862c45b5955 ("app/testpmd: move dumping packets to a separate function")
Cc: stable@dpdk.org
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Xiaoyun Li <xiaoyun.li@intel.com>
Acked-by: Raslan Darawsheh <rasland@nvidia.com>
3 years agoapp/testpmd: fix check without outer checksum
Nithin Dabilpuram [Mon, 16 Aug 2021 07:09:41 +0000 (12:39 +0530)]
app/testpmd: fix check without outer checksum

Donot use outer metadata when neither outer ip checksum nor
outer udp checksum is enabled. PMD's will ignore the
outer_l2_len and outer_l3_len in cases where none of
the outer checksum is enabled and hence only l2_len and
l3_len will be used to calculate the offsets for L2 or L3
header.

Fixes: 3c32113a1aac ("app/testpmd: fix IPv6 tunnel checksum")
Cc: stable@dpdk.org
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Xiaoyun Li <xiaoyun.li@intel.com>
3 years agonet/bnxt: fix VNIC config error in Rx queue start
Ajit Khaparde [Tue, 24 Aug 2021 01:58:20 +0000 (18:58 -0700)]
net/bnxt: fix VNIC config error in Rx queue start

During port stop/start sequence the Thor FW is returning an error.
This is because we are deriving incorrect active Rx ring and using
that wrong information in the bnxt_vnic_rss_cfg HWRM command.

Fix it by using the rx_queue_state from eth_dev.

Fixes: 0105ea1296c9 ("net/bnxt: support runtime queue setup")
Cc: stable@dpdk.org
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
3 years agonet/bnxt: fix crash after port stop/start
Somnath Kotur [Mon, 23 Aug 2021 15:44:53 +0000 (21:14 +0530)]
net/bnxt: fix crash after port stop/start

On chips like Thor, port stop/start sequence could result in a crash
in the application. This is because of false detection of a bad
opaque in the Rx completion and the subsequent kicking-in of the ring
reset code to recover from the condition.
The root cause being that the port stop/start would result in the HW
starting with fresh values, while the driver internal tracker variable
`rx_next_cons` is still pointing to a stale value.
Fix this by resetting rx_next_cons to 0 in bnxt_init_one_rx_ring()

Fixes: 03c8f2fe111c ("net/bnxt: detect bad opaque in Rx completion")
Cc: stable@dpdk.org
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
3 years agoapp/testpmd: use per-core variable in flowgen
Zhihong Wang [Fri, 13 Aug 2021 08:05:48 +0000 (16:05 +0800)]
app/testpmd: use per-core variable in flowgen

Use per-core variable for flow indexing to solve cache contention in
multi-core scenarios.

Signed-off-by: Zhihong Wang <wangzhihong.wzh@bytedance.com>
Acked-by: Xiaoyun Li <xiaoyun.li@intel.com>
3 years agoapp/testpmd: record Rx and dropped stats in flowgen
Zhihong Wang [Fri, 13 Aug 2021 08:05:47 +0000 (16:05 +0800)]
app/testpmd: record Rx and dropped stats in flowgen

Call inc_rx_burst_stats for rx operation, and record fwd_dropped.

Signed-off-by: Zhihong Wang <wangzhihong.wzh@bytedance.com>
Acked-by: Xiaoyun Li <xiaoyun.li@intel.com>
3 years agoapp/testpmd: use existing checksum API in flowgen engine
Zhihong Wang [Fri, 13 Aug 2021 08:05:46 +0000 (16:05 +0800)]
app/testpmd: use existing checksum API in flowgen engine

Use the rte_ipv4_cksum API to replace local ip_sum implementation.

Signed-off-by: Zhihong Wang <wangzhihong.wzh@bytedance.com>
Acked-by: Xiaoyun Li <xiaoyun.li@intel.com>
3 years agoapp/testpmd: fix Tx retry in flowgen engine
Zhihong Wang [Fri, 13 Aug 2021 08:05:45 +0000 (16:05 +0800)]
app/testpmd: fix Tx retry in flowgen engine

Fix tx_pkt number in tx retry logic.

Fixes: bf56fce1fb45 ("app/testpmd: add retry option")
Cc: stable@dpdk.org
Signed-off-by: Zhihong Wang <wangzhihong.wzh@bytedance.com>
Acked-by: Xiaoyun Li <xiaoyun.li@intel.com>
3 years agonet/mlx5: update GENEVE TLV option matching
Shiri Kuzin [Mon, 31 May 2021 11:45:43 +0000 (14:45 +0300)]
net/mlx5: update GENEVE TLV option matching

The GENEVE TLV option matching is done using a flex parser.

Recent update in firmware, requires that in order to match on the
GENEVE TLV option the "geneve_tlv_option_0_exist" bit should be set.

Add the new "geneve_tlv_option_0_exist" setting when translating the
GENEVE TLV option item.

Signed-off-by: Shiri Kuzin <shirik@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
3 years agonet/bnxt: update ring group after ring stop start
Ajit Khaparde [Mon, 2 Aug 2021 04:44:30 +0000 (21:44 -0700)]
net/bnxt: update ring group after ring stop start

A Rx ring stop start sequence may result in the FW returning
a different set of Rx ring and AGG ring IDs. If the ring group
is not updated with the new IDs, the HW sees the host driver using
incorrect BD types for the Rx ring and AGG ring. This can cause
the chip to go into a bad state or encounter RE_flush issue
or leak mbufs in the HW.

Fix this by issuing a bnxt_hwrm_ring_grp_free() and an
bnxt_hwrm_ring_grp_alloc() to refresh the ring group information.

Fixes: 9b63c6fd70e3 ("net/bnxt: support Rx/Tx queue start/stop")
Cc: stable@dpdk.org
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
3 years agonet/mlx5: fix eCPRI matching
Dmitry Kozlyuk [Mon, 9 Aug 2021 14:26:46 +0000 (17:26 +0300)]
net/mlx5: fix eCPRI matching

When an ETH or VLAN flow item directly preceding ECPRI (i. e. a pattern
for eCPRI over Ethernet) did not specify the eCPRI protocol, matches
were not restricted to eCPRI traffic. For example, "eth / ecpri / end"
pattern behaved as "eth / end". Implicitly add Ethernet type condition,
so that "eth / ecpri / end" behaves as "eth type is 0xAEFE / end".

Fixes: daa38a8924a0 ("net/mlx5: add flow translation of eCPRI header")
Cc: stable@dpdk.org
Signed-off-by: Dmitry Kozlyuk <dkozlyuk@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/mlx5: fix mbuf replenishment check for zipped CQE
Alexander Kozyrev [Wed, 4 Aug 2021 06:23:16 +0000 (09:23 +0300)]
net/mlx5: fix mbuf replenishment check for zipped CQE

A core dump is being generated with the following call stack:
0 _mm256_storeu_si256 (__A=..., __P=0x80)
1 rte_mov32 (src=0x2299c9140 "", dst=0x80)
2 rte_memcpy_aligned (n=60, src=0x2299c9140, dst=0x80)
3 rte_memcpy (n=60, src=0x2299c9140, dst=0x80)
4 mprq_buf_to_pkt (strd_cnt=1, strd_idx=0, buf=0x2299c8a00, len=60,
pkt=0x18345f0c0, rxq=0x18345ef40)
5 rxq_copy_mprq_mbuf_v (rxq=0x18345ef40, pkts=0x7f76e0ff6d18, pkts_n=5)
6 rxq_burst_mprq_v (rxq=0x18345ef40, pkts=0x7f76e0ff6d18, pkts_n=46,
err=0x7f76e0ff6a28, no_cq=0x7f76e0ff6a27)
7 mlx5_rx_burst_mprq_vec (dpdk_rxq=0x18345ef40, pkts=0x7f76e0ff6a88,
pkts_n=128)
8 rte_eth_rx_burst (nb_pkts=128, rx_pkts=0x7f76e0ff6a88,
queue_id=<optimized out>, port_id=<optimized out>)

This crash is caused by an attempt to copy previously uncompressed CQEs
into non-allocated mbufs. There is a check to make sure we only use
allocated mbufs in the rxq_burst_mprq_v() function, but it is done only
before the main processing loop. Leftovers of compressed CQEs session are
handled before that loop and may lead to the mbufs overflow as seen.

Move the check for replenished mbufs up to protect uncompressed CQEs
session leftovers from accessing non-allocated mbufs after the
mlx5_rx_mprq_replenish_bulk_mbuf() function is invoked.

Bugzilla ID: 746
Fixes: 0f20acbf5eda ("net/mlx5: implement vectorized MPRQ burst")
Cc: stable@dpdk.org
Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
3 years agonet/mlx5: fix RSS expansion for inner tunnel VLAN
Lior Margalit [Tue, 3 Aug 2021 18:13:22 +0000 (21:13 +0300)]
net/mlx5: fix RSS expansion for inner tunnel VLAN

The RSS expansion algorithm is using a graph to find the possible
expansion paths. The VLAN item in the flow pattern requires special
treatment, because it should not be added implicitly by the expansion
algorithm.  If the flow pattern ends with ETH item, the pattern will be
expanded with IPv4 and IPv6.
For example:
testpmd> flow create ... eth / end actions rss / end
ETH END
ETH IPV4 END
ETH IPV6 END
If a VLAN item follows the ETH item in the flow pattern, the pattern
will be expanded with IPv4 and IPv6 following the VLAN item.
For example:
testpmd> flow create ... eth / vlan / end actions rss level 1 / end
ETH VLAN END
ETH VLAN IPV4 END
ETH VLAN IPV6 END

The case of inner tunnel VLAN item was not taken care of so the flow
pattern did not expand with IPv6 and IPv4 as expected.
Example with inner VLAN:
testpmd> flow create ... / vxlan / eth / vlan / end actions rss level 2
/ end
The current result of the expansion alg:
ETH IPV6 UDP VXLAN ETH VLAN END
The expected result of the expansion alg:
ETH IPV6 UDP VXLAN ETH VLAN END
ETH IPV6 UDP VXLAN ETH VLAN IPV4 END
ETH IPV6 UDP VXLAN ETH VLAN IPV6 END

The fix is to introduce a new flag to set on a graph expansion node
to apply the 'explicit' behavior, meaning the node is not added to
the expanded pattern, if it is not found in the flow pattern, but the
expansion alg can go deeper to its next nodes.

Fixes: c7870bfe09dc ("ethdev: move RSS expansion code to mlx5 driver")
Cc: stable@dpdk.org
Signed-off-by: Lior Margalit <lmargalit@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
3 years agonet/txgbe: fix L4 port mask in flow director
Jiawen Wu [Thu, 12 Aug 2021 02:00:20 +0000 (10:00 +0800)]
net/txgbe: fix L4 port mask in flow director

Remove bit reverse for TCP/UDP port mask, since it causes the flows with
some TCP/UDP ports to disobey the flow director rules.

Fixes: ea230dda16ad ("net/txgbe: configure flow director filter")
Cc: stable@dpdk.org
Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
3 years agonet/txgbe: fix reading SFP module SFF-8472 data
Jiawen Wu [Thu, 12 Aug 2021 02:00:19 +0000 (10:00 +0800)]
net/txgbe: fix reading SFP module SFF-8472 data

Fix the I2C target address selection to read SFP module's SFF-8472 data.

Fixes: 8f09fb4642fa ("net/txgbe: add module identify")
Cc: stable@dpdk.org
Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
3 years agonet/txgbe: fix link status when device stopped
Jiawen Wu [Thu, 12 Aug 2021 02:00:18 +0000 (10:00 +0800)]
net/txgbe: fix link status when device stopped

When device is stopped, the port status is not changed and only the Tx
laser is turned off by hardware design.

Fixes: 0c061eadec59 ("net/txgbe: add link status change")
Cc: stable@dpdk.org
Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
3 years agonet/nfp: rename files for consistency
Heinrich Kuhn [Thu, 29 Jul 2021 13:47:11 +0000 (15:47 +0200)]
net/nfp: rename files for consistency

Rename the nfp_net.c file to nfp_common as it now contains functions
common to VF and PF functionality. Rename the header file too to be
consistent. Also remove the "net" naming from the _ctrl and _logs files
for consistency across the PMD.

Signed-off-by: Heinrich Kuhn <heinrich.kuhn@netronome.com>
Signed-off-by: Simon Horman <simon.horman@corigine.com>
3 years agonet/nfp: move PF functions into its own file
Heinrich Kuhn [Thu, 29 Jul 2021 13:47:10 +0000 (15:47 +0200)]
net/nfp: move PF functions into its own file

Similar to the last commit, this changeset moves all the PF specific
functions to a new file called nfp_ethdev.c.

Signed-off-by: Heinrich Kuhn <heinrich.kuhn@netronome.com>
Signed-off-by: Simon Horman <simon.horman@corigine.com>
3 years agonet/nfp: move VF functions into its own file
Heinrich Kuhn [Thu, 29 Jul 2021 13:47:09 +0000 (15:47 +0200)]
net/nfp: move VF functions into its own file

Move any ethdev functionality specific to VF devices into a new file
called nfp_ethdev_vf.c.

Signed-off-by: Heinrich Kuhn <heinrich.kuhn@netronome.com>
Signed-off-by: Simon Horman <simon.horman@corigine.com>
3 years agonet/nfp: move common function prototypes
Heinrich Kuhn [Thu, 29 Jul 2021 13:47:08 +0000 (15:47 +0200)]
net/nfp: move common function prototypes

The majority of "ethdev" type functions are used for both PF devices and
VF devices. Prototype these functions in the nfp_net_pmd header file in
preparation of splitting PF and VF specific functions.

Signed-off-by: Heinrich Kuhn <heinrich.kuhn@netronome.com>
Signed-off-by: Simon Horman <simon.horman@corigine.com>
3 years agonet/nfp: move CPP bridge to separate file
Heinrich Kuhn [Thu, 29 Jul 2021 13:47:07 +0000 (15:47 +0200)]
net/nfp: move CPP bridge to separate file

This commit moves the CPP bridge logic to a separate file. A new
corresponding header file is also created.

Signed-off-by: Heinrich Kuhn <heinrich.kuhn@netronome.com>
Signed-off-by: Simon Horman <simon.horman@corigine.com>
3 years agonet/nfp: move datapath functions to their own file
Heinrich Kuhn [Thu, 29 Jul 2021 13:47:06 +0000 (15:47 +0200)]
net/nfp: move datapath functions to their own file

Create a new rxtx file and move the Rx/Tx functions to this file. This
commit will also move the needed shared functions to the nfp_net_pmd.h
file as needed.

Signed-off-by: Heinrich Kuhn <heinrich.kuhn@netronome.com>
Signed-off-by: Simon Horman <simon.horman@corigine.com>
3 years agonet/nfp: split datapath structs into separate file
Heinrich Kuhn [Thu, 29 Jul 2021 13:47:05 +0000 (15:47 +0200)]
net/nfp: split datapath structs into separate file

This change splits out the rx/tx specific structs and defines from the
main nfp_net_pmd header file and into their own header file.

Signed-off-by: Heinrich Kuhn <heinrich.kuhn@netronome.com>
Signed-off-by: Simon Horman <simon.horman@corigine.com>
3 years agonet/hns3: support set link up/down for PF
Huisong Li [Mon, 26 Jul 2021 10:59:40 +0000 (18:59 +0800)]
net/hns3: support set link up/down for PF

This patch adds set link up/down feature. RxTx datapath and link status
will be disabled when dev_set_link_down() is called, and can be enabled by
dev_start() or dev_set_link_up().

Signed-off-by: Huisong Li <lihuisong@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
3 years agonet/hns3: add Tx start/stop multi-process handling
Huisong Li [Mon, 26 Jul 2021 10:59:39 +0000 (18:59 +0800)]
net/hns3: add Tx start/stop multi-process handling

Currently, hns3 PMD has supported start/stop RxTx datapath request message
between the primary and secondary processes. However, there are some cases
only to start/stop Tx datapath. This patch adds start/stop Tx datapath
request for MP.

Signed-off-by: Huisong Li <lihuisong@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
3 years agonet/nfp: remove compile time log
Ferruh Yigit [Tue, 18 May 2021 10:41:15 +0000 (11:41 +0100)]
net/nfp: remove compile time log

Logging should be converted to dynamic log.

Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
Reviewed-by: Heinrich Kuhn <heinrich.kuhn@netronome.com>
3 years agonet/ice: fix bandwidth config size in memory copy
Ting Xu [Tue, 27 Jul 2021 10:55:08 +0000 (18:55 +0800)]
net/ice: fix bandwidth config size in memory copy

The memory size of bandwidth config parameters is not set correctly in
memory copy process, which leads to the wrong values. This patch fixed
the size to the correct value.

Fixes: 3a6bfc37eaf4 ("net/ice: support QoS config VF bandwidth in DCF")
Cc: stable@dpdk.org
Signed-off-by: Ting Xu <ting.xu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
3 years agonet/ice: fix max entry number for ACL normal priority
Simei Su [Wed, 28 Jul 2021 02:24:29 +0000 (10:24 +0800)]
net/ice: fix max entry number for ACL normal priority

For ACL, there are three entry priorities: LOW, NORMAL, HIGH.
Low priority starts from the highest index, 25% of total entries;
Normal priority starts from the highest index, 50% of total entries;
High priority starts from the lowest index, 25% of total entries.

Each TCAM block has 512 entries of 40 bits. Currently, there is a
scenario in which multiple TCAM blocks are cascaded. It means the
total entries are 512. The default priority is NORMAL, so the max
entry is 256, not 512. This patch changes the max entry number for
NORMAL priority.

Fixes: 40d466fa9f76 ("net/ice: support ACL filter in DCF")
Cc: stable@dpdk.org
Signed-off-by: Simei Su <simei.su@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
3 years agonet/ice/base: increase maximum TCAM/PTG per profile
Qi Zhang [Tue, 10 Aug 2021 02:51:40 +0000 (10:51 +0800)]
net/ice/base: increase maximum TCAM/PTG per profile

For GTPoGRE protocol in AVF FDIR/RSS, the number of associated PTGs
of one Profile may exceed the defined ICE_MAX_PTG_PER_PROFILE and
ICE_MAX_TCAM_PER_PROFILE. In those cases, some PTGs may be missed,
and therefore, the related and received packets will not have hash
values. Thus, this patch updated the ICE_MAX_PTG_PER_PROFILE and
ICE_MAX_TCAM_PER_PROFILE to a larger number 64.

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: fix typo in comment
Qi Zhang [Tue, 10 Aug 2021 02:51:39 +0000 (10:51 +0800)]
net/ice/base: fix typo in comment

Correct spelling of word data instead of date.

Fixes: 453d087ccaff ("net/ice/base: add common functions")
Cc: stable@dpdk.org
Signed-off-by: Kevin Scott <kevin.c.scott@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: rename and add setter for unicast MAC flag
Qi Zhang [Tue, 10 Aug 2021 02:51:38 +0000 (10:51 +0800)]
net/ice/base: rename and add setter for unicast MAC flag

Rename ucast_shared to umac_shared, as "umac" is a more widely
used shorthand for "unicast MAC".

Also add a helper function to set this flag. This helper is
expected to be called by core drivers.

Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: support flow director for GTPU UL/DL with QFI
Qi Zhang [Tue, 10 Aug 2021 02:51:37 +0000 (10:51 +0800)]
net/ice/base: support flow director for GTPU UL/DL with QFI

Enable Flow Director filtering for GTPU UL/DL QFI field matching.

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: enable jumbo frame during HW init
Qi Zhang [Tue, 10 Aug 2021 02:51:36 +0000 (10:51 +0800)]
net/ice/base: enable jumbo frame during HW init

Call ice_aq_set_mac_cfg in ice_hw_init to enable jumbo frame support.

Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: support RSS for IPv4/L4 checksum
Qi Zhang [Tue, 10 Aug 2021 02:51:35 +0000 (10:51 +0800)]
net/ice/base: support RSS for IPv4/L4 checksum

The IPv4/TCP/UDP/SCTP header checksum fields are defined in this
patch and can be used as RSS input sets.

Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: support flow director for GTPoGRE
Qi Zhang [Tue, 10 Aug 2021 02:51:34 +0000 (10:51 +0800)]
net/ice/base: support flow director for GTPoGRE

Enable Flow Director filtering for GTPoGRE inner/outer fields
matching.

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
3 years agonet/ice/base: enable NVM update reset capabilities
Qi Zhang [Tue, 10 Aug 2021 02:51:33 +0000 (10:51 +0800)]
net/ice/base: enable NVM update reset capabilities

Add logic to parse capabilities relating to the firmware update reset
requirements. This includes both capability 0x76, which informs the
driver if the firmware can sometimes skip PCIe resets, and 0x77, which
informs the driver if the firmware might potentially restrict EMP
resets.

For capability 0x76, if the number is 1, the firmware will report the
required reset level for a given update as part of its response to the
last command sent to program the NVM bank. (Otherwise, if the firmware
does not support this capability then it will always send a 0 in the
field of the response).

For capability 0x77, if the number is 1, the firmware will report when
EMP reset is available as part of the response to the command for
switching flash banks. (Otherwise, if the firmware does not support this
capability, it will always send a 0 in the field of the response
message).

These capabilities are required to implement immediate firmware
activation. If the capabilities are set, software can read the response
data and determine what reset level is required to activate the firmware
image. If only an EMP reset is required, and if the EMP reset is not
restricted by firmware, then the driver can issue an EMP reset to
immediately activate the new firmware.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>