dpdk.git
4 years agonet/bnxt: add TruFlow hash function
Mike Baucom [Thu, 23 Jul 2020 11:56:24 +0000 (17:26 +0530)]
net/bnxt: add TruFlow hash function

Added TruFlow hash API for common hash uses across TruFlow
core functions.

Signed-off-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
4 years agonet/bnxt: modify ULP mapper to use TCAM search
Mike Baucom [Thu, 23 Jul 2020 11:56:23 +0000 (17:26 +0530)]
net/bnxt: modify ULP mapper to use TCAM search

Modified ulp mapper to use the new tf_search_tcam_entry API.
When search before allocation is requested, mapper calls
tc_search_tcam_entry with the alloc flag.

- On HIT, the result and tcam index is returned.
- On MISS, the tcam index is returned but the result is
created and the tcam entry is set.
- On REJECT, the flow request is rejected.

Signed-off-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
4 years agonet/bnxt: configure PARIF for offload miss rules
Kishore Padmanabha [Thu, 23 Jul 2020 11:56:22 +0000 (17:26 +0530)]
net/bnxt: configure PARIF for offload miss rules

PARIF is handler to a partition of the physical port.
For the offload miss rules, the parif miss path needs to be
considered. The higher parif are reserved for handling this.

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
4 years agonet/bnxt: add access to NAT global register
Kishore Padmanabha [Thu, 23 Jul 2020 11:56:21 +0000 (17:26 +0530)]
net/bnxt: add access to NAT global register

Add support to enable or disable the NAT global registers.
The NAT feature is enabled in hardware during initialization
and disabled at deinitialization of the application.

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
4 years agonet/bnxt: add shadow and search capability to TCAM
Mike Baucom [Thu, 23 Jul 2020 11:56:20 +0000 (17:26 +0530)]
net/bnxt: add shadow and search capability to TCAM

- Add TCAM shadow tables for searching
- Add Search API to allow reuse of TCAM entries

Signed-off-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
4 years agonet/mlx4: fix premature disabling of interrupt
Ophir Munk [Tue, 28 Jul 2020 11:54:06 +0000 (11:54 +0000)]
net/mlx4: fix premature disabling of interrupt

RXQ interrupts under Linux are based on the epoll mechanism. An
expected order of operations is as follows:
1. Call rte_eth_dev_rx_intr_enable(), to arm the CQ for receiving events
on data input.
2. Block on rte_epoll_wait() with an array of file descriptors
representing the CQ events. Upon data arrival the kernel will signal an
input event on the corresponding CQ fd.
3. Call rte_eth_dev_rx_intr_disable() after the event was received and
continue in polling mode. The mlx4 implementation of
rte_eth_dev_rx_intr_disable() is to get the CQ event and ack it.

In practice applications may wake up from rte_epoll_wait() due to
timeout with no event to ack but still call
rte_eth_dev_rx_intr_disable() unconditionally.  In such cases the call
should return EAGAIN (since the file descriptors are non-blocked), as
opposed to EINVAL which indicates a real failure.  In case of EAGAIN the
PMD should not warn on "unable to disable interrupt on rx queue".

Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Raslan Darawsheh <rasland@mellanox.com>
4 years agonet/hinic: check memory allocations in flow creation
Yunjian Wang [Tue, 28 Jul 2020 12:34:46 +0000 (20:34 +0800)]
net/hinic: check memory allocations in flow creation

The function rte_zmalloc() could return NULL, the return
value need to be checked.

Fixes: f4ca3fd54c4d ("net/hinic: create and destroy flow director filter")
Cc: stable@dpdk.org
Signed-off-by: Yunjian Wang <wangyunjian@huawei.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
4 years agonet/hinic/base: avoid system time jump
Xiaoyun Wang [Sat, 25 Jul 2020 08:15:36 +0000 (16:15 +0800)]
net/hinic/base: avoid system time jump

Replace gettimeofday() with clock_gettime(CLOCK_MONOTONIC_RAW, &now),
the reason is same with
commit d08d304508a8 ("eal/linux: make alarm not affected by system time
jump")

Fixes: 81d53291a466 ("net/hinic/base: add various headers")
Cc: stable@dpdk.org
Signed-off-by: Xiaoyun Wang <cloud.wangxiaoyun@huawei.com>
4 years agonet/hinic/base: modify VHD type for SDI
Xiaoyun Wang [Sat, 25 Jul 2020 08:15:35 +0000 (16:15 +0800)]
net/hinic/base: modify VHD type for SDI

For ovs offload scenario, when fw processes the virtio header,
there is no need to offset; and for standard card scenarios,
fw does not care about the vhd_type parameter, so in order to
be compatible with these two scenarios, use 0 offset instead.

Signed-off-by: Xiaoyun Wang <cloud.wangxiaoyun@huawei.com>
4 years agonet/hinic: optimize Rx performance for x86
Xiaoyun Wang [Sat, 25 Jul 2020 08:15:34 +0000 (16:15 +0800)]
net/hinic: optimize Rx performance for x86

For x86 platform, the rq cqe without cache aligned, which can
improve performance for some gateway scenarios.

Fixes: 361a9ccf81d6 ("net/hinic: optimize Rx performance")
Cc: stable@dpdk.org
Signed-off-by: Xiaoyun Wang <cloud.wangxiaoyun@huawei.com>
4 years agonet/hinic: refactor checksum functions
Xiaoyun Wang [Sat, 25 Jul 2020 08:15:33 +0000 (16:15 +0800)]
net/hinic: refactor checksum functions

Encapsulate different types of packet checksum preprocessing
into functions.

Signed-off-by: Xiaoyun Wang <cloud.wangxiaoyun@huawei.com>
4 years agonet/mlx5: fix Rx interrupt handling and cleanup
Dekel Peled [Mon, 27 Jul 2020 08:50:47 +0000 (11:50 +0300)]
net/mlx5: fix Rx interrupt handling and cleanup

Recent patch added creation of Rx CQ using DevX API.
The reading of events from DevX channel was not done correctly.
This patch fixes the event reading, using the correct data structure.
Cleanup after CQ creation, in case of error, is also updated.

Fixes: 08d1838f645a ("net/mlx5: implement CQ for Rx using DevX API")

Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
4 years agonet/ice: fix hash action validation
Jeff Guo [Mon, 27 Jul 2020 07:58:31 +0000 (15:58 +0800)]
net/ice: fix hash action validation

An invalid rule should not be validated successfully. If the rule is not
in the supporting list, just return failure to application.

Fixes: 5ad3db8d4bdd ("net/ice: enable advanced RSS")
Cc: stable@dpdk.org
Signed-off-by: Jeff Guo <jia.guo@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
4 years agonet/ice: remove RSS for SCTP in PPPoE
Qi Zhang [Mon, 27 Jul 2020 05:16:04 +0000 (13:16 +0800)]
net/ice: remove RSS for SCTP in PPPoE

We don't support SCTP in PPPoE RSS, remove it.

Fixes: d117de460035 ("net/ice: fix GTPU/PPPoE packets with no hash value")
Fixes: 0b952714e9c1 ("net/ice: refactor PF hash flow")

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Tested-by: Nannan Lu <nannan.lu@intel.com>
Acked-by: Jeff Guo <jia.guo@intel.com>
4 years agonet/ice/base: fix RSS interference
Qi Zhang [Sat, 25 Jul 2020 12:14:24 +0000 (20:14 +0800)]
net/ice/base: fix RSS interference

A new symmetric RSS rule may force another asymmetric rule to be
symmetric, vice versa. The reason is due to the flow engine will
try to reuse the existing profile if the input set matches with the
new rule. The fix is to disable this optimization for RSS since we
are not at the situation as profile shortage.

Fixes: ddae0440353f ("net/ice/base: enable symmetric hash for RSS")
Cc: stable@dpdk.org
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Tested-by: Nannan Lu <nannan.lu@intel.com>
Acked-by: Jeff Guo <jia.guo@intel.com>
4 years agonet/i40e: enable QinQ stripping
Wei Zhao [Fri, 24 Jul 2020 07:01:37 +0000 (15:01 +0800)]
net/i40e: enable QinQ stripping

This patch enable i40e outer vlan strip on and off in QinQ
mode with mask bit of DEV_RX_OFFLOAD_QINQ_STRIP, users can
use "vlan set qinq_strip on 0" to enable or "vlan set
qinq_strip off 0" to disable i40e outer vlan strip when
try with testpmd app.

Fixes: 4861cde46116 ("i40e: new poll mode driver")
Cc: stable@dpdk.org
Signed-off-by: Wei Zhao <wei.zhao1@intel.com>
Reviewed-by: Qiming Yang <qiming.yang@intel.com>
4 years agonet/af_xdp: remove mempool freeing on umem destruction
Ciara Loftus [Fri, 24 Jul 2020 13:20:32 +0000 (13:20 +0000)]
net/af_xdp: remove mempool freeing on umem destruction

Other PMDs may be using the mempool, so don't free it when destroying the
UMEM.

Fixes: d8a210774e1d ("net/af_xdp: support unaligned umem chunks")
Cc: stable@dpdk.org
Signed-off-by: Ciara Loftus <ciara.loftus@intel.com>
4 years agonet/mlx5: fix dynamic inline hint handling
Gregory Etelson [Thu, 23 Jul 2020 14:21:04 +0000 (17:21 +0300)]
net/mlx5: fix dynamic inline hint handling

The ConnectX NICs can transfer data from the host memory with two
approaches: provide the pointer to the data buffer, or do data inline
- copy the data to the transmit descriptor (WQE) entirely or only the
part of data. In some configurations the NIC hardware requires the
minimal data to be inline in the descriptor to operate correctly. And
there is the special dynamic flag to hint PMD not to inline the data
(for example, if buffer is located on some other device - storage or
GPU) on per packet basis.

If there was a packet with length shorter than the minimal inline data
length requested by the NIC hardware and the no-inline hint was set
the PMD tried to inline the packet with minimal required length
instead of actual packet's one.  This patch adds the missed length
check into no-inline hint handling branch.

Fixes: cacb44a09962 ("net/mlx5: add no-inline Tx flag")
Cc: stable@dpdk.org
Signed-off-by: Gregory Etelson <getelson@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
4 years agonet/mlx5: fix metadata storing for NEON Rx
Viacheslav Ovsiienko [Thu, 23 Jul 2020 10:53:32 +0000 (10:53 +0000)]
net/mlx5: fix metadata storing for NEON Rx

There was the typo introducing the bug, affected the mlx5 vectorized
rx_burst on ARM architectures in case if CQE compression was enabled.

Fixes: 6c55b622a956 ("net/mlx5: set dynamic flow metadata in Rx queues")
Cc: stable@dpdk.org
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
4 years agonet/mlx5: fix UAR memory mapping type
Viacheslav Ovsiienko [Wed, 22 Jul 2020 14:59:08 +0000 (14:59 +0000)]
net/mlx5: fix UAR memory mapping type

The User Access Region is a special mechanism to provide direct
access to the hardware registers, and is the part of PCI address
space that is mapped to CPU virtual address. The mapping can be
performed with the type "Write-Combining" or "Non-Cached", and
these ones might be supported or not on different setups.

To prevent device probing failure the UAR allocation attempt
with alternative mapping type is performed. The datapath
takes the actual UAR mapping into account on queue creation.

There was another issue with NULL UAR base address.
OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
UAR base address if UAR was not the first object in the UAR page.
It caused the PMD failure and we should try to get another UAR
till we get the first one with non-NULL base address returned.

Fixes: fc4d4f732bbc ("net/mlx5: introduce shared UAR resource")

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Ori Kam <orika@mellanox.com>
4 years agonet/i40e: fix hash lookup table
Shougang Wang [Fri, 24 Jul 2020 09:38:34 +0000 (09:38 +0000)]
net/i40e: fix hash lookup table

The hash look up table (LUT) is managed by global register but it is not
initialized when RSS is disabled. Once user wants to enable RSS during
runtime, the LUT will not be initialized.
This patch fixes the issue by initializing the LUT whatever RSS enabled
or not.

Fixes: feaae285b342 ("net/i40e: support hash configuration in RSS flow")
Cc: stable@dpdk.org
Signed-off-by: Shougang Wang <shougangx.wang@intel.com>
Tested-by: Xi Zhang <xix.zhang@intel.com>
Acked-by: Jeff Guo <jia.guo@intel.com>
4 years agonet/iavf: delete unsupported RSS types
Jeff Guo [Fri, 24 Jul 2020 04:07:02 +0000 (12:07 +0800)]
net/iavf: delete unsupported RSS types

The combined hash type should be bound with prefix protocol when
configure it, so delete some useless and unsupported part for
rss types mapping.

Fixes: 7be10c3004be ("net/iavf: add RSS configuration for VF")
Cc: stable@dpdk.org
Signed-off-by: Jeff Guo <jia.guo@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
4 years agonet/qede: remove dead code
Yunjian Wang [Fri, 17 Jul 2020 11:16:23 +0000 (19:16 +0800)]
net/qede: remove dead code

This patch removes logically dead code reported by coverity.

Coverity issue: 261777, 261778
Fixes: dd28bc8c6ef4 ("net/qede: fix VF port creation sequence")
Cc: stable@dpdk.org
Signed-off-by: Yunjian Wang <wangyunjian@huawei.com>
Acked-by: Rasesh Mody <rmody@marvell.com>
4 years agonet/iavf: add GTPU in default hash
Jeff Guo [Fri, 24 Jul 2020 02:21:52 +0000 (10:21 +0800)]
net/iavf: add GTPU in default hash

Add GTPU_IP and GTPU_EH hash in default.

Signed-off-by: Jeff Guo <jia.guo@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
4 years agonet/i40e: fix flow director MSI-X resource allocation
Mao Jiang [Thu, 23 Jul 2020 16:11:52 +0000 (00:11 +0800)]
net/i40e: fix flow director MSI-X resource allocation

FDIR allocating msix resource is not strictly necessary, if no
resource left, jump the error.

Fixes: 4861cde46116 ("i40e: new poll mode driver")
Cc: stable@dpdk.org
Signed-off-by: Mao Jiang <maox.jiang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
4 years agonet/i40e: fix binding interrupt without MSI-X vector
Mao Jiang [Thu, 23 Jul 2020 15:27:10 +0000 (23:27 +0800)]
net/i40e: fix binding interrupt without MSI-X vector

The value of vsi->nb_msix shouldn't`t be zero, otherwise, all of
interrupts will be bind to vector 0.

Fixes: 4861cde46116 ("i40e: new poll mode driver")
Cc: stable@dpdk.org
Signed-off-by: Mao Jiang <maox.jiang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
4 years agodoc: update release notes for hns3 driver
Wei Hu (Xavier) [Wed, 22 Jul 2020 11:56:32 +0000 (19:56 +0800)]
doc: update release notes for hns3 driver

Add release notes for Hisilicon hns3 PMD driver.

Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>
4 years agodoc: announce dpaa-specific API parameter change
Sachin Saxena [Tue, 14 Jul 2020 11:32:42 +0000 (17:02 +0530)]
doc: announce dpaa-specific API parameter change

'port_id' storage size should be 'uint16_t', the API
'rte_pmd_dpaa_set_tx_loopback()' has it as 'uint8_t' but fixing it is an
ABI breakage, that is why planning the fix in v20.11 release where ABI
breakage is allowed.

Signed-off-by: Sachin Saxena <sachin.saxena@nxp.com>
Acked-by: Ferruh Yigit <ferruh.yigit@intel.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Zhiyong Yang <zhiyong.yang@intel.com>
4 years agonet/mlx5: fix VF MAC address set over BlueField
Raslan Darawsheh [Wed, 22 Jul 2020 09:07:55 +0000 (12:07 +0300)]
net/mlx5: fix VF MAC address set over BlueField

When trying to set MAC address of an ethernet device and if it was
a representor, PMD sets the MAC over the corresponding VF instead.

For the case of HPF (Host PF representor on BlueField), PMD shouldn't
attempt to set it, since it doesn't have any corresponding VF and fails.

This will fix the issue by setting the MAC on the dev directly.

Fixes: 0d1d73170820 ("net/mlx5: set VF MAC address from host")
Cc: stable@dpdk.org
Signed-off-by: Raslan Darawsheh <rasland@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
4 years agonet/mlx5: fix vectorized mini-CQE prefetching
Alexander Kozyrev [Wed, 22 Jul 2020 20:32:38 +0000 (20:32 +0000)]
net/mlx5: fix vectorized mini-CQE prefetching

There was an optimization work to prefetch all the CQEs before
their invalidation. It allowed us to speed up the mini-CQE
decompression process by preheating the cache in the vectorized
Rx routine.

Prefetching of the next mini-CQE, on the other hand, showed
no difference in the performance on x86 platform. So, that was
removed. Unfortunately this caused the performance drop on ARM.

Prefetch the mini-CQE as well as all the soon to be
invalidated CQEs to get both CQE and mini-CQE on the hot path.

Fixes: 28a4b96321a3 ("net/mlx5: prefetch CQEs for a faster decompression")
Cc: stable@dpdk.org
Signed-off-by: Alexander Kozyrev <akozyrev@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
4 years agonet/iavf: disable simple XOR RSS hash function
Junfeng Guo [Thu, 23 Jul 2020 11:10:25 +0000 (11:10 +0000)]
net/iavf: disable simple XOR RSS hash function

Function simple_xor for AVF RSS is not required currently, thus we
just return rte_flow error when the command line has item simple_xor.

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
4 years agonet/mlx5: optimize stack memory in probe
Michael Baum [Tue, 21 Jul 2020 12:05:16 +0000 (12:05 +0000)]
net/mlx5: optimize stack memory in probe

The device configuration struct is not small enough to be used as
function argument by value.

Call spawn function with device configuration by reference.

Signed-off-by: Michael Baum <michaelba@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
4 years agonet/mlx5: fix unnecessary init in mark conversion
Michael Baum [Tue, 21 Jul 2020 12:04:37 +0000 (12:04 +0000)]
net/mlx5: fix unnecessary init in mark conversion

The flow_dv_convert_action_mark function defines an array of
field_modify_info structures and initializes the first entity.

In the first entity id field, it initializes to 0, even though its type
is an enum that has no value of 0.
In fact, the function does not use this id field before assigning the
appropriate register id into it, so the initialization is unnecessary.
Moreover, this initialization is int into enum, and it would be better
not to create a type conflict for no reason.

Wait for the first entity initialization until the appropriate register
id is already known.

Fixes: 55deee1715f0 ("net/mlx5: extend flow mark support")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
4 years agonet/mlx5: optimize critical section in device free
Michael Baum [Tue, 21 Jul 2020 12:03:38 +0000 (12:03 +0000)]
net/mlx5: optimize critical section in device free

When PMD releases shared IB device context, It locks the
mlx5_ibv_list_mutex lock throughout the function so that it does not
happen while removing a device from the list, another process will try
to insert another device into it.
On the other hand, having removed the device from the list even if it
has not yet released all of its resources, it should not care about
other processes and can release the lock.

However, the PMD does not release the lock even though it can, and
performs a number of operations, some of which include sleep and may be
long.
To improve this, shorten the lock time to the minimum necessary.

Signed-off-by: Michael Baum <michaelba@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
4 years agonet/mlx5: fix unlimited parsing of switch info
Michael Baum [Tue, 21 Jul 2020 12:02:32 +0000 (12:02 +0000)]
net/mlx5: fix unlimited parsing of switch info

In mlx5_sysfs_switch_info function, the driver gets switch information
associated with network interface.

The driver writes the port name into buffer and translates it.
However, when it writes the name, it does not limit writing to the
buffer size.

Limit writing to the size of the buffer.

Fixes: 1256805dd54d ("net/mlx5: move Linux-specific functions")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
4 years agonet/mlx4: optimize stack memory size in probe
Michael Baum [Tue, 21 Jul 2020 12:01:09 +0000 (12:01 +0000)]
net/mlx4: optimize stack memory size in probe

The mlx4_pci_probe function sets a pointer to the mlx4_priv structure,
and during that function fills its fields one by one with relevant
values.

It wants to put a value in the intr_handle field that has all its fields
zero except 2. To do so, it initializes a local struct rte_intr_handle
type variable and updates it only 2 fields and assigns it into the
appropriate field. However, it initializes a very large structure on the
stack while not at all certain that this place exists and in any case it
is very wasteful.

Reset all fields directly to the pointer by memset, then format the 2
fields to the relevant values.

Fixes: 63c2f23c852a ("net/mlx4: use a single interrupt handle")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
4 years agonet/mlx5: remove ineffective increment in hairpin split
Michael Baum [Tue, 21 Jul 2020 12:00:04 +0000 (12:00 +0000)]
net/mlx5: remove ineffective increment in hairpin split

The flow_hairpin_split function defines a pointer called addr that
points to the list of items.
When the function wants to progress in the list, it adds the size of an
item to the pointer.

At the end of the function, it precedes the pointer one more time even
though it is not used afterwards. In fact, this line is unaffected and
the operation of the function would have been no different without it.

Remove the line where the pointer is preceded unnecessarily.

Fixes: d85c7b5ea59f ("net/mlx5: split hairpin flows")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
4 years agonet/mlx5: fix crash in NVGRE item translation
Michael Baum [Tue, 21 Jul 2020 11:59:04 +0000 (11:59 +0000)]
net/mlx5: fix crash in NVGRE item translation

The flow_dv_translate_item_nvgre function add NVGRE item to matcher and
to the value.
It defines a pointer named nvrge_m that receives the item's mask into
it, and then copies some of it to the matcher.

Before copying, it checks for mask validation, and in case the mask is
NULL the function gives it a pointer to rte_flow_item_nvgre_mask.
However, the function calls from the vni mask's field before the check,
and if there is no mask, it actually does dereference to the NULL
pointer and indeed the program crashes with segfault.

Move the call from the vni field to post-validation.

Fixes: cd18e1b72f73 ("net/mlx5: fix build on Arm")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
4 years agonet/mlx5: fix initialization of steering registers
Michael Baum [Tue, 21 Jul 2020 11:57:21 +0000 (11:57 +0000)]
net/mlx5: fix initialization of steering registers

The mlx5_flow_action_copy_mreg structure contains a field called src
type enum modify_reg, similarly the mlx5_rte_flow_item_tag field
contains a field called id type enum modify_reg.
The enum modify_reg variable represents different registers in the
system and it also has a field called REG_NONE whose value is 0 which
means that the register does not exist.

The flow_mreg_add_copy_action function sets a variable of struct
mlx5_flow_action_copy_mreg type, and initializes the src field to be 0.
Similarly the flow_create_split_metadata function sets a variable of
struct mlx5_rte_flow_item_tag type and initializes the id field to be 0.
In both functions, they initialize a enum modify_reg type variable with
an int type value while modify_reg has an appropriate field for that
value (REG_NONE).

Replace assigning 0 with REG_NONE in both functions.

Fixes: dd3c774f6ffb ("net/mlx5: add metadata register copy table")
Fixes: 71e254bc0294 ("net/mlx5: split Rx flows to provide metadata copy")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
4 years agonet/mlx5: fix counter query
Suanming Mou [Wed, 22 Jul 2020 07:58:47 +0000 (15:58 +0800)]
net/mlx5: fix counter query

Currently, the counter query requires the counter ID should start
with 4 aligned. In none-batch mode, the counter pool might have the
chance to get the counter ID not 4 aligned. In this case, the counter
should be skipped, or the query will be failed.

Skip the counter with ID not 4 aligned as the first counter in the
none-batch count pool to avoid invalid counter query. Once having
new min_dcs ID in the poll less than the skipped counters, the
skipped counters will be returned to the pool free list to use.

Fixes: 5382d28c2110 ("net/mlx5: accelerate DV flow counter transactions")
Cc: stable@dpdk.org
Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
4 years agonet/mlx5: separate aging counter pool range
Suanming Mou [Wed, 22 Jul 2020 07:58:45 +0000 (15:58 +0800)]
net/mlx5: separate aging counter pool range

Currently, when allocate the counter or counter based age from group 0,
counter and age may share the same counter dcs ID range. Both age and
pure counter need to sync up with each other's container to check if
the ID range exists and update the min_dcs.

It comes two disadvantages:
1. If the ID range is shared, this counter range will be queried twice
   both from age and pure counter container in 1s.
2. The same range counter check between the two container makes the
   counter allocate sync min_dcs time to time with extra min_dcs
   updating.

This patch avoid the same ID range to be shared when allocate the new
pool. If the same ID range exists in other container, just add the
counter to the other container until get new range which saves the
min_dcs sync up time to time.

Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
4 years agocommon/mlx5: fix queue doorbell record size
Viacheslav Ovsiienko [Tue, 21 Jul 2020 11:11:29 +0000 (11:11 +0000)]
common/mlx5: fix queue doorbell record size

When Rx/Tx queue was being created with DevX the allocated
doorbell record size was only uint64_t. That was definitely
less than size of CPU cacheline and it might have happened the
doorbell records attached to different queues handled by
different cores were allocated within same cacheline. It might
have caused the contention on doorbell record writing.

This patch extends the allocated memory size for doorbell
record to cacheline size.

Fixes: 21cae8580fd0 ("net/mlx5: allocate door-bells via DevX")
Cc: stable@dpdk.org
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
4 years agonet/mlx5: fix flow items size calculation
Raslan Darawsheh [Thu, 16 Jul 2020 12:14:55 +0000 (15:14 +0300)]
net/mlx5: fix flow items size calculation

flow_dv_get_item_len returns the actual header size of
an rte_flow item.

Changing any of the structs for rte_flow items by adding
or removing some extra fields will break this function.

This fixes the behavior by returning the actual header size
of each item.

Fixes: 34d41b7aa3bf ("net/mlx5: add VXLAN encap action to Direct Verbs")
Cc: stable@dpdk.org
Signed-off-by: Raslan Darawsheh <rasland@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
4 years agonet/mlx5: fix premature disabling of interrupt
Ophir Munk [Tue, 21 Jul 2020 14:41:07 +0000 (14:41 +0000)]
net/mlx5: fix premature disabling of interrupt

RXQ interrupts under Linux are based on the epoll mechanism. An expected
order of operations is as follows:
1. Call rte_eth_dev_rx_intr_enable(), to arm the CQ for receiving events
   on data input.
2. Block on rte_epoll_wait() with an array of file descriptors
   representing the CQ events. Upon data arrival the kernel will signal
   an input event on the corresponding CQ fd.
3. Call rte_eth_dev_rx_intr_disable() after the event was received and
   continue in polling mode. The mlx5 implementation of
   rte_eth_dev_rx_intr_disable() is to get the CQ event and ack it.

In practice applications may wake up from rte_epoll_wait() due to
timeout with no event to ack but still call
rte_eth_dev_rx_intr_disable() unconditionally.  In such cases the call
should return EAGAIN (since the file descriptors are non-blocked), as
opposed to EINVAL which indicates a real failure.  In case of EAGAIN the
PMD should not warn on "Unable to disable interrupt on Rx queue".

This commit fixes a earlier commit where the returned value 0 from
function devx_get_event() - was considered an error.

Fixes: 08d1838f645a ("net/mlx5: implement CQ for Rx using DevX API")

Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Raslan Darawsheh <rasland@mellanox.com>
4 years agonet/ice: fix bytes statistics
Junyu Jiang [Tue, 21 Jul 2020 07:20:21 +0000 (07:20 +0000)]
net/ice: fix bytes statistics

This patch fixed the issue that rx/tx bytes overflowed
on 40 bit limitation by enlarging the limitation.

Fixes: a37bde56314d ("net/ice: support statistics")
Cc: stable@dpdk.org
Signed-off-by: Junyu Jiang <junyux.jiang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
4 years agoapp/regex: add RegEx test application
Yuval Avnery [Wed, 29 Jul 2020 18:09:57 +0000 (18:09 +0000)]
app/regex: add RegEx test application

Following the new RegEx class.
There is a need to create a dedicated test application in order to
validate this class and PMD.

Unlike net device this application loads data from a file.

This commit introduces the new RegEx test app.

The basic app flow:
1. Configure the RegEx device to use one queue, and set the rule
   database, using precompiled file.
2. Allocate mbufs based on the requested number of jobs, each job will
i  get one mbuf.
3. Enqueue as much as possible jobs.
4. Dequeue jobs.
5. if the number of dequeue jobs < requested number of jobs job to step

Signed-off-by: Ori Kam <orika@mellanox.com>
Signed-off-by: Yuval Avnery <yuvalav@mellanox.com>
4 years agoregex/mlx5: fix overrun on enqueueing
Yuval Avnery [Wed, 29 Jul 2020 02:14:51 +0000 (02:14 +0000)]
regex/mlx5: fix overrun on enqueueing

When enqueueing a buffer the PMD check if there is room
in its send queue (SQ).
The current implementation did not take into account that
queue indices are wrapping around, which may result in
consumer index (sq->ci) can have bigger value than than
the producer index (sq->pi).

Fixes: 4d4e245ad637 ("regex/mlx5: support enqueue")

Signed-off-by: Yuval Avnery <yuvalav@mellanox.com>
Acked-by: Ori Kam <orika@mellanox.com>
4 years agobus/vmbus: use SMP memory barrier for signaling read
Long Li [Fri, 17 Jul 2020 20:18:29 +0000 (13:18 -0700)]
bus/vmbus: use SMP memory barrier for signaling read

rte_smp_mb() uses the same locked ADD as the in-kernel vmbus driver,
and it has slightly performance improvement over rte_mb().

Signed-off-by: Long Li <longli@microsoft.com>
4 years agoapp/crypto-perf: support security protocol in PMDCC mode
David Coyle [Tue, 21 Jul 2020 14:56:48 +0000 (15:56 +0100)]
app/crypto-perf: support security protocol in PMDCC mode

This patch adds support for DOCSIS and PDCP security protocols to the
pmd-cyclecount mode of the crypto performance tool. Adding this support
involves freeing the correct session type (i.e. security or cryptodev
session) when the test ends, depending on the op_type specified.

Signed-off-by: David Coyle <david.coyle@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agoapp/crypto-perf: fix mbuf lengths for DOCSIS
David Coyle [Thu, 16 Jul 2020 15:31:11 +0000 (16:31 +0100)]
app/crypto-perf: fix mbuf lengths for DOCSIS

Set the source mbuf data and packet lengths correctly for DOCSIS
performance tests.

Fixes: d4a131a9498d ("test/crypto-perf: support DOCSIS protocol")

Signed-off-by: David Coyle <david.coyle@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agocrypto/armv8: remove redundant assert definition
Ruifeng Wang [Tue, 28 Jul 2020 09:24:06 +0000 (17:24 +0800)]
crypto/armv8: remove redundant assert definition

No need to define assert function in PMD since RTE provides the same.
Remove private definition and use RTE_VERIFY instead.

Suggested-by: David Marchand <david.marchand@redhat.com>
Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agocrypto/armv8: use dedicated log type
Ruifeng Wang [Tue, 28 Jul 2020 09:24:05 +0000 (17:24 +0800)]
crypto/armv8: use dedicated log type

armv8 crypto PMD used CRYPTODEV general log type.
Create a dedicated log type for the PMD to not pollute CRYPTODEV log type.

Typo in crypto dev name macro caused unexpected device name in log.
Fixed the typo to log with correct device name.

Fixes: 169ca3db550c ("crypto/armv8: add PMD optimized for ARMv8 processors")
Cc: stable@dpdk.org
Suggested-by: David Marchand <david.marchand@redhat.com>
Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agocrypto/armv8: remove debug option
Ruifeng Wang [Tue, 28 Jul 2020 09:24:04 +0000 (17:24 +0800)]
crypto/armv8: remove debug option

Typo in debug log switch macro caused debug log cannot be enabled.
Since no log used in data path, remove the debug option entirely
and have logs always enabled.

Resolved compilation error when debug log is enabled:
rte_armv8_pmd.c: In function â€˜process_armv8_chained_op’:
rte_armv8_pmd.c:633:22: error: expected â€˜)’ before â€˜crypto_func’
  ARMV8_CRYPTO_ASSERT(crypto_func != NULL);
                      ^

Fixes: 169ca3db550c ("crypto/armv8: add PMD optimized for ARMv8 processors")
Cc: stable@dpdk.org
Reported-by: David Marchand <david.marchand@redhat.com>
Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
4 years agodoc: update QAT PMD release notes
Adam Dybkowski [Mon, 27 Jul 2020 10:14:08 +0000 (12:14 +0200)]
doc: update QAT PMD release notes

This patch updates 20.08 release notes inside
the part that describe changes in Intel QuickAssist PMD.

Fixes: faa57df0b458 ("crypto/qat: support ChaCha20-Poly1305")
Fixes: 9904ff684981 ("common/qat: improve multi-process handling")

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
4 years agocommon/qat: support GEN2 device 200xx
Adam Dybkowski [Mon, 27 Jul 2020 10:14:07 +0000 (12:14 +0200)]
common/qat: support GEN2 device 200xx

This adds pci detection and documentation for Intel GEN2
QuickAssist device 200xx (PF Did 0x18ee, VF Did 0x18ef).

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
4 years agocommon/qat: fix uninitialized variable
Adam Dybkowski [Fri, 24 Jul 2020 09:40:10 +0000 (11:40 +0200)]
common/qat: fix uninitialized variable

This patch fixes the uninitialized variable bug in QAT PMD.

Fixes: 9f27a860dc16 ("crypto/qat: move generic qp function to qp file")
Cc: stable@dpdk.org
Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
4 years agocommon/qat: remove unused fields
Adam Dybkowski [Tue, 21 Jul 2020 13:36:58 +0000 (15:36 +0200)]
common/qat: remove unused fields

This patch removes unused fields from structs qat_qp and
qat_qp_config, together with their initializations.

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
4 years agocrypto/octeontx2: fix structure alignment
Tejasree Kondoj [Tue, 21 Jul 2020 04:16:18 +0000 (09:46 +0530)]
crypto/octeontx2: fix structure alignment

The structure cpt_request_info needs only 8 byte alignment.
This patch replaces __rte_cache_aligned of cpt_request_info
with __rte_aligned(8) and removes __rte_aligned(8) in
cpt_meta_info structure.

Fixes: fab634eb87ca ("crypto/octeontx2: support security session data path")

Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
4 years agocrypto/qat: fix DOCSIS performance
David Coyle [Tue, 21 Jul 2020 14:47:18 +0000 (15:47 +0100)]
crypto/qat: fix DOCSIS performance

DOCSIS protocol performance in the downlink direction can be improved
significantly in the QAT SYM PMD, especially for larger packets, by
pre-processing all CRC generations in a batch before building and
enqueuing any requests to the HW. This patch adds this optimization.

Fixes: 6f0ef237404b ("crypto/qat: support DOCSIS protocol")

Signed-off-by: David Coyle <david.coyle@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
4 years agocrypto/aesni-mb: improve security instance setup
David Coyle [Mon, 20 Jul 2020 12:16:21 +0000 (13:16 +0100)]
crypto/aesni-mb: improve security instance setup

This patch makes some improvements to the security instance setup for
the AESNI-MB PMD, as follows:
- fix potential memory leak where the security instance was not freed if
  an error occurred later in the device creation
- tidy-up security instance initialization code by moving it all,
  including enabling the RTE_CRYPTODEV_FF_SECURITY feature, into one
  '#ifdef AESNI_MB_DOCSIS_SEC_ENABLED' block

Fixes: fda5216fba55 ("crypto/aesni_mb: support DOCSIS protocol")

Signed-off-by: David Coyle <david.coyle@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
4 years agocrypto/qat: improve security instance setup
David Coyle [Mon, 20 Jul 2020 12:16:20 +0000 (13:16 +0100)]
crypto/qat: improve security instance setup

This patch makes some improvements to the security instance setup for
the QAT SYM PMD, as follows:
- fix potential memory leak where the security instance was not freed if
  an error occurred later in the device creation
- tidy-up security instance initialization code by moving it all,
  including enabling the RTE_CRYPTODEV_FF_SECURITY feature, into one
  '#ifdef RTE_LIBRTE_SECURITY' block

Fixes: 6f0ef237404b ("crypto/qat: support DOCSIS protocol")

Signed-off-by: David Coyle <david.coyle@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
4 years agoevent/dpaa2: add all-types queue capability flag
Apeksha Gupta [Thu, 23 Jul 2020 17:04:25 +0000 (22:34 +0530)]
event/dpaa2: add all-types queue capability flag

DPAA2 eventdev device is capable of all type queue feature.
Fix the capability flag to reflect the same.

Fixes: 8f4a294c23 ("event/dpaa2: apply new capability flags")
Cc: stable@dpdk.org
Signed-off-by: Apeksha Gupta <apeksha.gupta@nxp.com>
Acked-by: Nipun Gupta <nipun.gupta@nxp.com>
4 years agoapp/eventdev: fix capability check in pipeline ATQ test
Apeksha Gupta [Thu, 23 Jul 2020 17:02:32 +0000 (22:32 +0530)]
app/eventdev: fix capability check in pipeline ATQ test

Add all type queue capability check before configuring event device
for pipeline atq test.

Fixes: 6bf570a9911 ("app/eventdev: add pipeline atq test")
Cc: stable@dpdk.org
Signed-off-by: Apeksha Gupta <apeksha.gupta@nxp.com>
Acked-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
4 years agoevent/dpaa: remove dead code
Yunjian Wang [Fri, 17 Jul 2020 11:31:52 +0000 (19:31 +0800)]
event/dpaa: remove dead code

Fix logical dead code.

Coverity issue: 323495
Fixes: 77b5311d0ece ("event/dpaa: support select based event")
Cc: stable@dpdk.org
Signed-off-by: Yunjian Wang <wangyunjian@huawei.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
4 years agocommon/mlx5: remove class check from class drivers
Parav Pandit [Mon, 27 Jul 2020 17:47:15 +0000 (20:47 +0300)]
common/mlx5: remove class check from class drivers

Now that mlx5_pci PMD checks for enabled classes and performs
probe(), remove() of associated classes, individual class driver
does not need to check if other driver is enabled.

Signed-off-by: Parav Pandit <parav@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
4 years agocommon/mlx5: register class drivers through common layer
Parav Pandit [Mon, 27 Jul 2020 17:47:14 +0000 (20:47 +0300)]
common/mlx5: register class drivers through common layer

Migrate mlx5 net, vdpa and regex PMD to start using mlx5 common class
driver.

Signed-off-by: Parav Pandit <parav@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
4 years agocommon/mlx5: introduce layer for multiple class drivers
Parav Pandit [Mon, 27 Jul 2020 17:47:13 +0000 (20:47 +0300)]
common/mlx5: introduce layer for multiple class drivers

Add generic mlx5 PCI PMD layer as part of existing common_mlx5
module. This enables multiple classes (net, regex, vdpa) PMDs
to be supported at same time.

Signed-off-by: Parav Pandit <parav@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
4 years agocommon/mlx5: change class values as bits
Parav Pandit [Mon, 27 Jul 2020 17:47:12 +0000 (20:47 +0300)]
common/mlx5: change class values as bits

mlx5 PCI Device supports multiple classes of devices such as net, vdpa,
and/or regex.
To support these multiple classes, change mlx5_class to a
bitmap values so that if users asks to enable multiple of them, all
supported classes can be parsed.

Signed-off-by: Parav Pandit <parav@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
4 years agocommon/mlx5: avoid class constructor priority
Parav Pandit [Mon, 27 Jul 2020 17:47:11 +0000 (20:47 +0300)]
common/mlx5: avoid class constructor priority

mlx5_common is shared library between mlx5 net, VDPA and regex PMD.
It is better to use common initialization helper instead of using
RTE_PRIORITY_CLASS priority.

Suggested-by: David Marchand <david.marchand@redhat.com>
Signed-off-by: Parav Pandit <parav@mellanox.com>
Reviewed-by: David Marchand <david.marchand@redhat.com>
4 years agoregex/mlx5: fix crash on initialization failure
Parav Pandit [Mon, 27 Jul 2020 17:47:10 +0000 (20:47 +0300)]
regex/mlx5: fix crash on initialization failure

When fail to initialize the device, avoid segmentation fault while
accessing uninitialized priv.

Fixes: cfc672a90b74 ("regex/mlx5: support probing")

Signed-off-by: Parav Pandit <parav@mellanox.com>
4 years agocommon/mlx5: fix void parameters in glue wrappers
Parav Pandit [Mon, 27 Jul 2020 17:47:09 +0000 (20:47 +0300)]
common/mlx5: fix void parameters in glue wrappers

Following two errors are reported when compiled with
gcc (GCC) 8.3.1 20191121 (Red Hat 8.3.1-5).

drivers/common/mlx5/linux/mlx5_glue.h:188:2:
error: function declaration isn't a prototype [-Werror=strict-prototypes]

drivers/common/mlx5/linux/mlx5_glue.h:188:2:
error: function declaration isn't a prototype [-Werror=strict-prototypes]

Fix them by adding void data type in empty argument list.

Fixes: 34fa7c0268e7 ("net/mlx5: add drop action to Direct Verbs E-Switch")
Fixes: 400d985eb586 ("net/mlx5: add VLAN push/pop DR commands to glue")
Cc: stable@dpdk.org
Signed-off-by: Parav Pandit <parav@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
4 years agodrivers: relax dependency order
Thomas Monjalon [Mon, 27 Jul 2020 17:47:08 +0000 (20:47 +0300)]
drivers: relax dependency order

Drivers dependencies are evaluated in the order defined per their parent
directory (also called class). This strict ordering prevents from
having pairs of drivers from two classes with different dependency
ordering. For example, if the mlx5 common code depends on the pci bus
driver, while the dpaax common code is itself a dependency of the dpaa
bus driver.  Having a strict ordering between directories bus and common
is too restrictive, as processing either common drivers or bus drivers
first leads us to missing dependencies in this scenario.

This patch makes it possible to have a more fine-grain directory list,
adding a specific driver sub-directory in the top-level drivers
subdirectory list. In this case, the isolated driver must also be removed
from its class list, and the per-class variables must be duplicated in
the isolated driver, because the call "subdir(class)" is skipped in the
isolated driver case.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Reviewed-by: David Marchand <david.marchand@redhat.com>
4 years agodrivers: fix indent of directory list
Thomas Monjalon [Mon, 27 Jul 2020 17:47:07 +0000 (20:47 +0300)]
drivers: fix indent of directory list

Define each sub-directory on its own line ended with a comma,
and use a simple indent.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Reviewed-by: David Marchand <david.marchand@redhat.com>
4 years agoeal: introduce macro for bit definition
Parav Pandit [Mon, 27 Jul 2020 17:47:06 +0000 (20:47 +0300)]
eal: introduce macro for bit definition

There are several drivers which duplicate bit generation macro.
Introduce a generic bit macros so that such drivers avoid redefining
same in multiple drivers.

Signed-off-by: Parav Pandit <parav@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Acked-by: Morten Brørup <mb@smartsharesystems.com>
4 years agotest/cycles: restore default delay callback
Ruifeng Wang [Mon, 27 Jul 2020 10:21:50 +0000 (18:21 +0800)]
test/cycles: restore default delay callback

test_delay_us_sleep registers sleep based delay for testing.
This changes the default delay function of testing environment.
It is not expected.

Restore default delay function after the test to fix the issue.

Fixes: a51639cc720a ("eal: add nanosleep based delay function")
Cc: stable@dpdk.org
Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
4 years agohash: fix out-of-memory handling in hash creation
Yunjian Wang [Wed, 22 Jul 2020 03:58:58 +0000 (11:58 +0800)]
hash: fix out-of-memory handling in hash creation

The function rte_zmalloc_socket() could return NULL, the return
value need to be checked.

Fixes: 5915699153d7 ("hash: fix scaling by reducing contention")
Cc: stable@dpdk.org
Reported-by: Bin Huang <brian.huangbin@huawei.com>
Signed-off-by: Yunjian Wang <wangyunjian@huawei.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Acked-by: Yipeng Wang <yipeng1.wang@intel.com>
4 years agoversion: 20.08-rc2
Thomas Monjalon [Wed, 22 Jul 2020 00:45:20 +0000 (02:45 +0200)]
version: 20.08-rc2

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
4 years agobus/vdev: fix a typo in doxygen comment
Muhammad Bilal [Tue, 23 Jun 2020 13:26:02 +0000 (18:26 +0500)]
bus/vdev: fix a typo in doxygen comment

While uninitalizing the driver, the comment was mentioning
initialized instead of uninitalized in description of parameter.

Fixes: 0fe11ec592b2 ("eal: add vdev init and uninit")
Cc: stable@dpdk.org
Signed-off-by: Muhammad Bilal <m.bilal@emumba.com>
4 years agodoc: fix typo in bbdev test guide
Sarosh Arif [Tue, 16 Jun 2020 08:22:01 +0000 (13:22 +0500)]
doc: fix typo in bbdev test guide

fixed typing error in doc/guides/tools/testbbdev.rst

Fixes: f714a18885a6 ("app/testbbdev: add test application for bbdev")
Cc: stable@dpdk.org
Signed-off-by: Sarosh Arif <sarosh.arif@emumba.com>
Acked-by: Nicolas Chautru <nicolas.chautru@intel.com>
4 years agodoc: fix some typos in Linux guide
Honnappa Nagarahalli [Mon, 8 Jun 2020 21:52:07 +0000 (16:52 -0500)]
doc: fix some typos in Linux guide

The display was not proper due to the missing space. Changed
arm64 to aarch64.

Fixes: 2eb7c526b929 ("doc: clarify IOMMU disabling for uio_pci_generic")
Cc: stable@dpdk.org
Signed-off-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
4 years agoexamples/l3fwd-power: fix updating lcore parameters
Anatoly Burakov [Tue, 14 Jul 2020 10:30:02 +0000 (11:30 +0100)]
examples/l3fwd-power: fix updating lcore parameters

When perf-config option is specified, we are calling into the power
library even though it may not necessarily be enabled. It is
questionable whether perf-config option is even applicable to non-power
library modes, but for now, fix it just by avoiding calling into the
power library if it wasn't initialized, and assume that every lcore is
high performance core.

Fixes: e0194feb322c ("examples/l3fwd-power: add interrupt-only mode")

Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
Acked-by: David Hunt <david.hunt@intel.com>
4 years agopower: fix environment detection
Anatoly Burakov [Tue, 14 Jul 2020 10:30:01 +0000 (11:30 +0100)]
power: fix environment detection

Anything coming from sysfs has a newline at the end. Cut it off before
comparing the strings.

Fixes: 20ab67608a39 ("power: add environment capability probing")

Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
Acked-by: David Hunt <david.hunt@intel.com>
Tested-by: Lihong Ma <lihongx.ma@intel.com>
Reviewed-by: Bruce Richardson <bruce.richardson@intel.com>
4 years agomempool: fix allocation in memzone during retry
Zhike Wang [Tue, 14 Jul 2020 07:26:05 +0000 (15:26 +0800)]
mempool: fix allocation in memzone during retry

If allocation is successful on the first attempt, typically
there is no problem since we allocated everything required and
we'll terminate the loop (if memory chunk is really sufficient
to populate required number of mempool elements).

If the first attempt fails, we try to allocate half
of mem_size and it succeed, we'll have one more iteration of
the for-loop to allocate memory for remaining elements and
should not try the next time with quarter of the mem_size.

It is wrong that max_alloc_size is divided by 2 in the
case of successful allocation as well, or invalid memory
can be allocated, and leads to population failure, then errno
other than ENOMEM may be returned.

Fixes: 3a3d0c75b43e ("mempool: fix slow allocation of large pools")
Cc: stable@dpdk.org
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Signed-off-by: Zhike Wang <wangzhike@jd.com>
Acked-by: Anatoly Burakov <anatoly.burakov@intel.com>
4 years agonode: add packet classifier
Nithin Dabilpuram [Sun, 7 Jun 2020 16:40:42 +0000 (22:10 +0530)]
node: add packet classifier

This node classifies pkts based on packet type and
sends them to appropriate next node. This is node
helps in distribution of packets from ethdev_rx node
to different next node with a constant overhead for
all packet types.

Currently all except non fragmented IPV4 packets are marked
to be sent to "pkt_drop" node.
Performance difference on ARM64 Octeontx2 is -4.9% due to
addition of new node in the path.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
4 years agoraw/ifpga/base: fix NIOS SPI init
Tianfei Zhang [Tue, 14 Jul 2020 21:35:09 +0000 (05:35 +0800)]
raw/ifpga/base: fix NIOS SPI init

Add fecmode setting on NIOS SPI primary initialization.
this SPI is shared by NIOS core inside FPGA, NIOS will
use this SPI primary to do some one-time initialization
after power up, and then release the control to DPDK.

Fix the timeout initialization for polling the
NIOS_INIT_DONE.

Fixes: bc44402f ("raw/ifpga/base: configure FEC mode")
Cc: stable@dpdk.org
Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
Acked-by: Rosen Xu <rosen.xu@intel.com>
4 years agoraw/ifpga/base: fix SPI transaction
Tianfei Zhang [Tue, 14 Jul 2020 21:35:08 +0000 (05:35 +0800)]
raw/ifpga/base: fix SPI transaction

0x4a means idle status on physical layer. when encounter
0x4a on raw data, it need insert a ESCAPE character for
indication.

Fixes: 96ebfcf8 ("raw/ifpga/base: add SPI and MAX10 device driver")
Cc: stable@dpdk.org
Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
Acked-by: Rosen Xu <rosen.xu@intel.com>
4 years agonet/vhost: support queue update
Matan Azrad [Tue, 21 Jul 2020 16:38:16 +0000 (16:38 +0000)]
net/vhost: support queue update

The commit below changed the readiness condition of vhost device to fix
multi-queues issues showed with QEMU versions.

Now, the vhost device is ready when the first queue-pair is ready.
When more queues are being ready, the queue state callback will be
triggered to notify the vhost manager.

In case of Rx interrupt configuration, the vhost driver set the
kickfd queue file descriptor in order to be notified on Rx traffic.

So, when queue becomes ready, the kickfd may be changed and should be
updated in the Rx interrupt structure.

Update kickfd when the queue state callback is invoked.
Also update event notification when it is enabled by the user.

Fixes: d0fcc38f5fa4 ("vhost: improve device readiness notifications")

Suggested-by: Marvin Liu <yong.liu@intel.com>
Signed-off-by: Matan Azrad <matan@mellanox.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
4 years agonet/sfc: do not enforce hash offload in RSS multi-queue
Andrew Rybchenko [Tue, 21 Jul 2020 14:54:49 +0000 (15:54 +0100)]
net/sfc: do not enforce hash offload in RSS multi-queue

Rx RSS hash offload should be controlled by the user and should
not be enforced by RSS multi-queue Rx mode.

Fixes: 8b945a7f7dcb ("drivers/net: update Rx RSS hash offload capabilities")
Cc: stable@dpdk.org
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
4 years agonet/sfc: avoid unnecessary actions on dummy default MAC set
Andrew Rybchenko [Tue, 21 Jul 2020 08:58:45 +0000 (09:58 +0100)]
net/sfc: avoid unnecessary actions on dummy default MAC set

Just an optimization to avoid extra reconfiguration when it
is not actually required.

Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
4 years agonet/sfc: remove inclusion of unused headers
Andrew Rybchenko [Tue, 21 Jul 2020 08:57:55 +0000 (09:57 +0100)]
net/sfc: remove inclusion of unused headers

Defines and functions from rte_mbuf_ptype.h are not used.

Only libefx types and EF10 register definitions are used.
Native datapaths should be independent from main libefx interface.

Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
4 years agonet/sfc/base: improve headers independence
Andrew Rybchenko [Tue, 21 Jul 2020 08:57:54 +0000 (09:57 +0100)]
net/sfc/base: improve headers independence

efx_types.h uses defines from efx_annote.h, but does not include the
header. As the result if efx_types.h is included by a driver first,
build fails.

Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
4 years agonet: fix pedantic build
Raslan Darawsheh [Tue, 21 Jul 2020 08:31:55 +0000 (11:31 +0300)]
net: fix pedantic build

when trying to compile rte_mpls with pedantic enabled,
on old compilers like 4.8 it will complain about bit field definition.

error: type of bit-field 'bs' is a GCC extension [-Werror=pedantic]
error: type of bit-field 'tc' is a GCC extension [-Werror=pedantic]
error: type of bit-field 'tag_lsb' is a GCC extension [-Werror=pedantic]

This fixes the compilation error by adding extension to the header
definition.

Fixes: e480cf487a0d ("net: add MPLS header structure")
Cc: stable@dpdk.org
Signed-off-by: Raslan Darawsheh <rasland@mellanox.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
4 years agovhost: fix double-free with zero-copy
Patrick Fu [Tue, 21 Jul 2020 12:10:57 +0000 (12:10 +0000)]
vhost: fix double-free with zero-copy

zmbufs should be set to NULL when getting freed to avoid double free on
the same buffer pointer

Fixes: b0a985d1f340 ("vhost: add dequeue zero copy")
Cc: stable@dpdk.org
Signed-off-by: Patrick Fu <patrick.fu@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
4 years agovhost: fix async completion of multi-seg packets
Patrick Fu [Tue, 21 Jul 2020 05:47:20 +0000 (13:47 +0800)]
vhost: fix async completion of multi-seg packets

In async enqueue copy, a packet could be split into multiple copy
segments. When polling the copy completion status, current async data
path assumes the async device callbacks are aware of the packet
boundary and return completed segments only if all segments belonging
to the same packet are done. Such assumption are not generic to common
async devices and may degrade the copy performance if async callbacks
have to implement it in software manner.

This patch adds tracking of the completed copy segments at vhost side.
If async copy device reports partial completion of a packets, only
vhost internal record is updated and vring status keeps unchanged
until remaining segments of the packet are also finished. The async
copy device is no longer necessary to care about the packet boundary.

Fixes: cd6760da1076 ("vhost: introduce async enqueue for split ring")

Signed-off-by: Patrick Fu <patrick.fu@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
4 years agovhost: fix missing virtqueue status check in async path
Patrick Fu [Tue, 21 Jul 2020 03:35:57 +0000 (11:35 +0800)]
vhost: fix missing virtqueue status check in async path

Vring should not be touched if vq is disabled. This patch adds the vq
status check in async enqueue polling to avoid accessing to a disabled
queue.

Fixes: cd6760da1076 ("vhost: introduce async enqueue for split ring")

Signed-off-by: Patrick Fu <patrick.fu@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
4 years agovhost: fix missing device pointer validity check
Patrick Fu [Tue, 21 Jul 2020 03:23:04 +0000 (11:23 +0800)]
vhost: fix missing device pointer validity check

This patch adds the check of dev pointer in vhost async enqueue
completion poll. If a NULL dev pointer detected, the poll function
returns immediately.

Coverity issue: 360839
Fixes: cd6760da1076 ("vhost: introduce async enqueue for split ring")

Signed-off-by: Patrick Fu <patrick.fu@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
4 years agonet/octeontx2: free CQ ring memzone on queue release
Pavan Nikhilesh [Sun, 28 Jun 2020 23:31:35 +0000 (05:01 +0530)]
net/octeontx2: free CQ ring memzone on queue release

Free CQ ring memzone on Rx queue release. This prevents CQ using
incorrect memory size when ring size is reconfigured.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
4 years agonet/mlx5: fix tunnel flow priority
Gregory Etelson [Thu, 16 Jul 2020 07:39:58 +0000 (10:39 +0300)]
net/mlx5: fix tunnel flow priority

PMD flow priority is different from application flow priority.  Flow
rules with higher match granularity assigned higher PMD priority. Also
PMD splits internally RSS flows according to flow RSS layer.

Final PMD flow rule priority derived from the last match item network
level, after PMD adjusts flow rule, where L4 match gets the highest
priority and L2 the lowest.

The patch adjusts tunnels flow rule priority calculation for PMDs
running verb API.

Introduce MLX5_TUNNEL_PRIO_GET macro.

Fixes: 4a78c88e3bae ("net/mlx5: fix Verbs flow tunnel")
Cc: stable@dpdk.org
Signed-off-by: Gregory Etelson <getelson@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Acked-by: Ori Kam <orika@mellanox.com>
4 years agonet/mlx5: fix VLAN push action on hairpin queue
Dekel Peled [Wed, 15 Jul 2020 07:31:01 +0000 (10:31 +0300)]
net/mlx5: fix VLAN push action on hairpin queue

Push VLAN action is allowed on Tx only, same as encap action.
Flow rules for hairpin queue are created on Rx, and split
by PMD to Rx and Tx rules, according to the above limitation.
In current implementation the encap action is split to Tx rule.
This patch adds the same handling for push-vlan action, as well as
its complementing actions set-vlan-vid and set-vlan-pcp.

Fixes: d85c7b5ea59f ("net/mlx5: split hairpin flows")
Cc: stable@dpdk.org
Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
4 years agonet/mlx5: fix VLAN pop with decap action validation
Dekel Peled [Wed, 15 Jul 2020 07:30:33 +0000 (10:30 +0300)]
net/mlx5: fix VLAN pop with decap action validation

The combination of decap action followed by pop VLAN action is not
fully validated in existing code.

This patch updates the validation function of pop vlan action.
Pop VLAN with preceding Decap requires inner header with VLAN.
Pop VLAN without preceding Decap requires outer header with VLAN.

Fixes: b41e47da2592 ("net/mlx5: support pop flow action on VLAN header")
Cc: stable@dpdk.org
Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>