net/i40e: support TSO on tunneling packet

To enable Tx side offload on tunneling packet, driver should set
correct tunneling parameters: (1) EIPT, External IP header type;
(2) EIPLEN, External IP; (3) L4TUNT; (4) L4TUNLEN. This parsing
behavior is based on (ol_flag & PKT_TX_TUNNEL_MASK). And when
it's a tunneling packet, MACLEN defines the outer L2 header.

Also, we define TSO on each kind of tunneling type as a capabilities.
Now only i40e declares to support them.

Signed-off-by: Zhe Tao <zhe.tao@intel.com>
Signed-off-by: Jianfeng Tan <jianfeng.tan@intel.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>

mbuf: add Tx side tunneling type

To support tunneling packet offload capabilities on Tx side, PMDs
(e.g., i40e) need to know what kind of tunneling type of this packet.
Instead of analyzing the packet itself, we depend on applications to
correctly set the tunneling type. These flags are defined inside
rte_mbuf.ol_flags.

Signed-off-by: Zhe Tao <zhe.tao@intel.com>
Signed-off-by: Jianfeng Tan <jianfeng.tan@intel.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>

app/test: remove crypto queue number hard-coding

ts_params->conf.nb_queue_pairs should not be hard coded with device
specific number. It should be retrieved from the device info.
Any test which changes it should restore it to orig value.

Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>

app/test: cleanup unnecessary crypto ring size setup

Removed obsolete comments re inability to free and re-allocate
queue memory and obsolete workaround for it
which used to create maximum size queues first, then later
create smaller queues.

Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>

app/test: remove useless loop for crypto

Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>

crypto/aesni_mb: free ring memory on queue release

Free ring memory on queue_pair release, else
releasing and setting up queue-pair of a different size fails.

Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>

doc: fix typo in SNOW 3G guide

Fixes: 1d0c90e6cf0b ("doc: update build instructions for libsso_snow3g")

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: John McNamara <john.mcnamara@intel.com>

cryptodev: fix build on Suse 11 SP2

This commit fixes following build error, which happens in SUSE 11 SP2,
with gcc 4.5.1:

In file included from lib/librte_cryptodev/rte_cryptodev.c:70:0:
lib/librte_cryptodev/rte_cryptodev.h:772:7:
error: flexible array member in otherwise empty struct

Fixes: 347a1e037fd3 ("lib: use C99 syntax for zero-size arrays")

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>

examples/ipsec-secgw: initialize SA salt

This patch initializes the salt value used by the following cipher
algorithms:
- CBC: random salt
- GCM/CTR: the key required is 20B, and the last 4B are used as salt.

Signed-off-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

examples/ipsec-secgw: add cryptodev queue size constant

Introduce a specific cryptodev queue size macro.

Signed-off-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

examples/ipsec-secgw: check SP only when setup

Application will segfault if there is IPv4 or IPv6 and no SP/ACL rules
for IPv4 or IPv6 respectively.

Avoid checking the ACL/SP in such cases.

Fixes: 906257e965b7 ("examples/ipsec-secgw: support IPv6")

Signed-off-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

examples/ipsec-secgw: add AES-CTR

RFC3686: Using AES Counter (CTR) Mode With IPsec ESP.`

Signed-off-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

examples/ipsec-secgw: add AES-GCM

Add support for AES-GCM (Galois-Counter Mode).

RFC4106: The Use of Galois-Counter Mode (GCM) in IPSec ESP.

Signed-off-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

examples/ipsec-secgw: reset crypto operation status

Signed-off-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

examples/ipsec-secgw: change CBC IV generation

NIST SP800-38A recommends two methods to generate unpredictable IVs
(Initilisation Vector) for CBC mode:
1) Apply the forward function to a nonce (ie. counter)
2) Use a FIPS-approved random number generator

This patch implements the first recommended method by using the forward
function to generate the IV.

Signed-off-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

examples/l2fwd-crypto: update for libcrypto

Libcrypto PMD has support for:

Supported cipher algorithms:
RTE_CRYPTO_CIPHER_3DES_CBC
RTE_CRYPTO_CIPHER_AES_CBC
RTE_CRYPTO_CIPHER_AES_CTR
RTE_CRYPTO_CIPHER_3DES_CTR
RTE_CRYPTO_CIPHER_AES_GCM

Supported authentication algorithms:
RTE_CRYPTO_AUTH_AES_GMAC
RTE_CRYPTO_AUTH_MD5
RTE_CRYPTO_AUTH_SHA1
RTE_CRYPTO_AUTH_SHA224
RTE_CRYPTO_AUTH_SHA256
RTE_CRYPTO_AUTH_SHA384
RTE_CRYPTO_AUTH_SHA512
RTE_CRYPTO_AUTH_MD5_HMAC
RTE_CRYPTO_AUTH_SHA1_HMAC
RTE_CRYPTO_AUTH_SHA224_HMAC
RTE_CRYPTO_AUTH_SHA256_HMAC
RTE_CRYPTO_AUTH_SHA384_HMAC
RTE_CRYPTO_AUTH_SHA512_HMAC

Signed-off-by: Daniel Mrzyglod <danielx.t.mrzyglod@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

app/test: add libcrypto

This patch contains unit tests for libcrypto PMD. User can
use app/test application to check how to use this pmd and to
verify crypto processing.

Test name is cryptodev_libcrypto_autotest.
For performance test cryptodev_libcrypto_perftest can be used.

Signed-off-by: Piotr Azarewicz <piotrx.t.azarewicz@intel.com>
Signed-off-by: Marcin Kerlin <marcinx.kerlin@intel.com>
Signed-off-by: Daniel Mrzyglod <danielx.t.mrzyglod@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

app/test: rework AES

This patch rework AES tests .
In general - rename AES-named functions to blockcipher functions pattern.

Signed-off-by: Piotr Azarewicz <piotrx.t.azarewicz@intel.com>
Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

crypto/libcrypto: add driver for OpenSSL library

This code provides the initial implementation of the libcrypto
poll mode driver. All cryptography operations are using Openssl
library crypto API. Each algorithm uses EVP_ interface from
openssl API - which is recommended by Openssl maintainers.

This patch adds libcrypto poll mode driver support to librte_cryptodev
library.

Signed-off-by: Slawomir Mrozowicz <slawomirx.mrozowicz@intel.com>
Signed-off-by: Michal Kobylinski <michalx.kobylinski@intel.com>
Signed-off-by: Tomasz Kulasek <tomaszx.kulasek@intel.com>
Signed-off-by: Daniel Mrzyglod <danielx.t.mrzyglod@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

examples/l2fwd-crypto: enable ZUC EEA3 and EIA3

This patch enables ZUC EEA3 cipher algorithm and
ZUC EIA3 authentication algorithm support to
l2fwd-crypto sample application.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>

app/test: add ZUC

Add cipher and authentication ZUC algorithm tests.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>

app/test: rename some SNOW 3G functions

Before adding the new ZUC tests, since they will use
the existing common functions for SNOW3G and KASUMI,
these functions are renamed to *_wireless_algo_*,
instead of *_snow3g_kasumi_*, as they are common
functions for all the three wireless algorithms.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>

crypto/zuc: add driver for ZUC library

Added new SW PMD which makes use of the libsso SW library,
which provides wireless algorithms ZUC EEA3 and EIA3
in software.

This PMD supports cipher-only, hash-only and chained operations
("cipher then hash" and "hash then cipher") of the following
algorithms:
- RTE_CRYPTO_SYM_CIPHER_ZUC_EEA3
- RTE_CRYPTO_SYM_AUTH_ZUC_EIA3

The ZUC hash and cipher algorithms, which are enabled
by this crypto PMD are implemented by Intel's libsso software
library.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>

app/test: improve error message for disabled crypto

Improve error message if crypto PMD build is not enabled in config file

Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

app/test: add AES GCM performance test

This patch adds AES Galois Counter Mode performance test case
for cryptodev QAT and AESNI GCM. Test is performed with different
buffer sizes, burst size of 32 and 128b key. Test vectors
are placed in app/test/test_cryptodev_perf_vectors.h file.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>

crypto: fix build with icc

This commit fixes a compilation error on icc,
due to unallowed conversion from int to enum:

drivers/crypto/snow3g/rte_snow3g_pmd.c(155):
    error #188: enumerated type mixed with another type
        sess->op = mode;
                 ^
drivers/crypto/kasumi/rte_kasumi_pmd.c(155):
    error #188: enumerated type mixed with another type
        sess->op = mode;
                 ^

Fixes: 3aafc423cf4d ("snow3g: add driver for SNOW 3G library")
Fixes: 2773c86d061a ("crypto/kasumi: add driver for KASUMI library")

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Ferruh Yigit <ferruh.yigit@intel.com>

app/test: remove unnecessary conditional for crypto

Regardless the result of the conditional, the true and false
statements were the same, so the conditional can be removed.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

examples/ipsec-secgw: add sample configuration files

This patch adds two sample configuration files to ipsec-secgw sample
application. The sample configuration files show how to setup
back-to-back systems that would forward traffic through an IPsec
tunnel.

Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com>
Acked-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>

examples/ipsec-secgw: support configuration file

This patch adds the configuration file support to ipsec_secgw
sample application. Instead of hard-coded rules, the users can
specify their own SP, SA, and routing rules in the configuration
file. A command line option "-f" is added to pass the
configuration file location to the application.

Configuration item formats:

SP rule format:
sp <ip_ver> <dir> esp <action> <priority> <src_ip> <dst_ip> \
<proto> <sport> <dport>

SA rule format:
sa <dir> <spi> <cipher_algo> <cipher_key> <auth_algo> <auth_key> \
<mode> <src_ip> <dst_ip>

Routing rule format:
rt <ip_ver> <src_ip> <dst_ip> <port>

Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com>
Acked-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>

app/test: fix verification of digest for GCM

This patch fixes verification of digest in test_cryptodev.c file
for AES GCM test cases.

Fixes: eec136f3c54f ("aesni_gcm: add driver for AES-GCM crypto operations")

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>

crypto/aesni_gcm: move pre-counter block to driver

This patch moves computing of pre-counter block into the AESNI-GCM
driver so it can be moved from test files.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>

crypto/qat: add 3DES cipher algorithm

3DES support added to QuickAssist PMD with CTR and CBC mode.
Both cipher-only and chained with HMAC_SHAx.

Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>

crypto/qat: cleanup code

Cleanup of unused code.
Rename and simplify a badly named struct element, was aes, but
used for all types of ciphers.
Print correct error msg (Unsupported rather than Undefined)
for all ciphers not supported by QAT PMD.

Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>

tools: bind crypto devices

Adding the support to bind/unbind crypto devices with
dpdk-devbind.py script, as now it is not restricted
to network devices anymore.

Signed-off-by: Eoin Breen <eoin.breen@intel.com>
Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>

crypto: rename all KASUMI references

KASUMI algorithm has all uppercase letters,
but some references of it had some lowercase letters.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>

crypto: rename some SNOW 3G references

SNOW 3G algorithm has all uppercase letters in its name
and a space between SNOW and 3G, but some references of it
had some lowercase letters or no space.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>

crypto/qat: fix FreeBSD build

Using sys/types.h instead of linux/types.h
so as to compile QAT_PMD on FreeBSD.

Fixes: 1703e94ac5ce ("qat: add driver for QuickAssist devices")

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

cryptodev: update GMAC API comments

In file rte_crypto_sym.h, GMAC API comments need to be changed
to comply with the GMAC specification. Main areas of change are
aad pointer and aad len, which now will be used to
provide plaintext.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>

app/test: add GMAC for qat

Added Galois Message Authentication Code (GMAC) tests to cryptodev tests.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>

crypto/qat: add GMAC capability

Added Galois Message Authentication Code (GMAC) capability to
QuickAssist Technology symmetric cryptographic driver.
GMAC is authentication only variant of Galois Counter Mode (GCM)
where all plaintext is provided with AAD pointer only.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>

crypto/qat: add C3xxx device

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

crypto/qat: add C62x device

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

app/test: add KASUMI for qat

This patch adds KASUMI tests in the QAT testsuite.
Alg-Chaining tests have also been added in the KASUMI
SW PMD.

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

crypto/qat: add KASUMI

This patch add kasumi support in Intel(R)
QuickAssist driver.

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

app/test: rename some SNOW 3G functions

Renamed authenticated encryption and encrypted authentication
tests with easily recognized names.

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

app/test: cleanup crypto code

Cleanup the code for code design consistency.

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

doc: fix names of supported crypto algorithms

Update documentation with correct names of supported algorithms.

Fixes: 1703e94ac5cee ("qat: add driver for QuickAssist devices")
Fixes: 3aafc423cf4d ("snow3g: add driver for SNOW 3G library")
Fixes: 924e84f87306 ("aesni_mb: add driver for multi buffer based crypto")
Fixes: 2773c86d061a ("crypto/kasumi: add driver for KASUMI library")

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

doc: add instructions to enable qat

Signed-off-by: Eoin Breen <eoin.breen@intel.com>
Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

crypto/null: fix key size increment value

This patch fixes the values of increment in key size.

Fixes: 94b0ad8e0aa5 ("null_crypto: add driver for null crypto operations")

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

app/test: add NULL operation for qat

Added NULL algorithm to test file for Intel(R) QuickAssist
Technology Driver.

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

crypto/qat: add NULL capability

Enabled NULL crypto for Intel(R) QuickAssist Technology.

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

app/test: add aes-sha384-hmac for qat

Added aes-sha384-hmac algorithm to test file for Intel(R) QuickAssist
Technology Driver.

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

crypto/qat: add aes-sha384-hmac capability

Enable support of aes-sha384-hmac in Intel(R) QuickAssist driver.

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

app/test: add aes-sha224-hmac for qat

Added aes-sha224-hmac algorithm to test file for Intel(R) QuickAssist
Technology Driver.

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

crypto/qat: add aes-sha224-hmac capability

Added support of aes-sha224-hmac in Intel(R) QuickAssist driver.

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

app/test: add MD5 HMAC for qat

Added MD5 HMAC hash algorithm to test file for Intel QuickAssist
Technology driver.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

crypto/qat: add MD5 HMAC capability

Added posibility to compute MD5 HMAC digest with Intel QuickAssist
Technology driver.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

crypto/qat: optimize request copy

using rte_mov128 instead of structure assignment to copy
template request from session context into request

Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: John Griffin <john.griffin@intel.com>

crypto/qat: make the session struct variable in size

This patch changes the qat firmware session data structure from a fixed
size to a variable size which is dependent on the size of the chosen
algorithm.
This reduces the amount of bytes which are transferred across
PCIe and thus helps to increase qat performance when the
accelerator is bound by PCIe.

Signed-off-by: John Griffin <john.griffin@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

vdev: rename init/uninit ops to probe/remove

Inline with PCI probe and remove, VDEV probe and remove hooks provide
a uniform naming.
PCI probe represents scan and driver initialization. For VDEV, it will
represent argument parsing and initialization.

Signed-off-by: Shreyansh Jain <shreyansh.jain@nxp.com>

mem: fix build with -O1

When compiled with EXTRA_CFLAGS="-O1", the compiler is not
able to detect that size is always initialized when used, and
issues a wrong warning:

  eal_memory.c: In function ‘rte_eal_hugepage_attach’:
  eal_memory.c:1684:3: error: ‘size’ may be used uninitialized in this
                       function [-Werror=maybe-uninitialized]
     munmap(hp, size);
     ^

Workaround this issue by initializing size to 0.
Seen on gcc (Debian 5.4.1-1) 5.4.1 20160803.

Signed-off-by: Olivier Matz <olivier.matz@6wind.com>

net/bnxt: update struct definitions for 1.5.1 HWRM API

Update the PMD to use the 1.5.1 HWRM API.
Most of the changes in the patch are white spaces and rearrangement of the
lines - a onetime change owing to the usage of a different auto generated
file.

Structures updated:
hwrm_stat_ctx_alloc_input, hwrm_stat_ctx_alloc_output,
hwrm_stat_ctx_free_input, hwrm_stat_ctx_free_output,
hwrm_stat_ctx_clr_stats_input, hwrm_stat_ctx_clr_stats_output,
hwrm_exec_fwd_resp_input, hwrm_exec_fwd_resp_output

Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>

net/bnxt: update HWRM filter related structures

Update the PMD to use packet filtering related structures as per the
1.5.1 version of the HWRM API. Most of the changes in the patch are
white spaces and rearrangement of the lines - a onetime change owing to
the usage of a different auto generated file.

Structures being updated:
hwrm_cfa_l2_filter_cfg_input, hwrm_cfa_l2_filter_cfg_output,
hwrm_cfa_l2_set_rx_mask_input, hwrm_cfa_l2_set_rx_mask_output,
hwrm_cfa_l2_filter_alloc_input, hwrm_cfa_l2_filter_alloc_output,
hwrm_cfa_l2_filter_free_input, hwrm_cfa_l2_filter_free_output

Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>

net/bnxt: update HWRM ring related structures

Update the PMD to use HWRM ring related structures as per the 1.5.1
version of the HWRM API.  Most of the changes in the patch are white
spaces and rearrangement of the lines - a onetime change owing to the
usage of a different auto generated file.

Structures being updated:
hwrm_ring_alloc_input, hwrm_ring_alloc_output, hwrm_ring_free_input,
hwrm_ring_free_output, hwrm_ring_grp_alloc_input,
hwrm_ring_grp_alloc_output, hwrm_ring_grp_free_input,
hwrm_ring_grp_free_output

Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>

net/bnxt: update VNIC related structures

Update the PMD to use VNIC related structures as per the 1.5.1 HWRM API.
Most of the changes in the patch are white spaces and rearrangement of the
lines - a onetime change owing to the usage of a different
auto generated file.

Structures being updated:
hwrm_vnic_alloc_input, hwrm_vnic_alloc_output, hwrm_vnic_free_input,
hwrm_vnic_free_output, hwrm_vnic_cfg_input, hwrm_vnic_cfg_output,
hwrm_vnic_rss_cfg_input, hwrm_vnic_rss_cfg_output,
hwrm_vnic_rss_cos_lb_ctx_alloc_input,
hwrm_vnic_rss_cos_lb_ctx_alloc_output,
hwrm_vnic_rss_cos_lb_ctx_free_input,
hwrm_vnic_rss_cos_lb_ctx_free_output

Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>

net/bnxt: update structures for 1.5.1 HWRM API

Update the PMD to use the 1.5.1 HWRM API.
Most of the changes in the patch are white spaces and rearrangement of the
lines - a onetime change owing to the usage of a different
auto generated file.

Structures updated:
hwrm_func_qcfg_input, hwrm_func_qcfg_output, hwrm_func_drv_rgtr_input,
hwrm_func_drv_rgtr_output, hwrm_func_drv_unrgtr_input,
hwrm_func_drv_unrgtr_output, hwrm_queue_qportcfg_input,
hwrm_queue_qportcfg_output

Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>

net/bnxt: update structures for 1.5.1 HWRM API

Update the PMD to use the 1.5.1 HWRM API.
Most of the changes in the patch are white spaces and rearrangement of the
lines - a onetime change owing to the usage of a different
auto generated file.

Structures being updated in this patch:
input, output, hwrm_ver_get_input, hwrm_ver_get_output,
hwrm_func_reset_input, hwrm_func_reset_output, hwrm_func_qcaps_input,
hwrm_func_qcaps_output

Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>

net/bnxt: update completion descriptors

Update the PMD to use structures as per the 1.5.1 HWRM API.
Most of the changes in the patch are white spaces and rearrangement of the
lines - hopefully a onetime change owing to the usage of a different
auto generated file.

Structures updated:
cmpl_base, tx_cmpl, rx_pkt_cmpl, rx_pkt_cmpl_hi, hwrm_fwd_req_cmpl,
hwrm_async_event_cmpl

Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>

net/bnxt: update buffer descriptor definitions

Update the PMD to use the 1.5.1 HWRM API.
Most of the changes in the patch are white spaces and rearrangement of the
lines - hopefully a onetime change owing to the usage of a different
auto generated file.

Structures updated in this patch:
tx_bd_short, tx_bd_long, tx_bd_long_hi, rx_prod_pkt_bd

Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>

net/bnxt: refactor for 1.5.1 HWRM API

Update the PMD to use the 1.5.1 HWRM API.
Most of the changes in this patch and the following patches are
white spaces and rearrangement of the lines - hopefully a onetime change
owing to the usage of a different auto generated file.

Other than that, the following fields have been renamed:
1) rx_err_pkts and tx_err_pkts are now rx_discard_pkts and tx_discard_pkts
in struct ctx_hw_stats64
2) the perm_mac_addr field in the response of bnxt_hwrm_func_qcaps has
changed to mac_addr.

Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>

net/bnxt: support hotplug

This patch adds support for port hotplug framework.

Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>

net/bnxt: support VF

Add support to the bnxt PMD to load on a PCI VF.
1) VF cannot change parameters like - speed, autoneg and pause
2) If the VF MAC address shows up as all 0's it has to be provisioned
by the PF in the hypervisor.

Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: David Christensen <david.christensen@broadcom.com>

net/bnxt: update guide

Update doc/guides/nics/bnxt.rst to indicate that the bnxt PMD driver
supports Broadcom NetXtreme-C/NetXtreme-E BCM5730X/BCM5740X family of
network controllers and Broadcom StrataGX BCM5871X family of
communications processors.

Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Acked-by: John McNamara <john.mcnamara@intel.com>

net/bnxt: add new device IDs

More PCI Device IDs for Cumulus, Cumulus+ and Whitney, Whitney+ SKUs.

The NPAR model supported by firmware has been altered. It now allocates a
unique Device ID for each NPAR partition for each device.  In addition,
ASIC's that are capable of supporting dual media have a unique DID
depending whether they are configured in copper or fiber mode.
This patch adds the necessary DIDs.

Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: David Christensen <david.christensen@broadcom.com>

net/bnxt: support NIC Partitioning

Adding code to enable support for NIC Partitioning or NPAR 1.0
As a part of NPAR, we don't allow port settings like speed or flow
control to be changed.

Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Stephen Hurd <stephen.hurd@broadcom.com>
Reviewed-by: David Christensen <david.christensen@broadcom.com>

net/bnxt: support Broadcom StrataGX

This patch adds support for the Broadcom StrataGX® BCM5871X
series of Communications Processors.

These ARM based processors target a broad range of networking
applications including virtual CPE (vCPE) and NFV appliances,
10G service routers and gateways, control plane processing for
Ethernet switches, and network attached storage (NAS).

Other than adding the PCI Id for supporting the device,
the patch also adds a memory barrier before the Tx doorbell
and Completing ring doorbell is written to. Since ARM has a
weakly ordered memory model this enforces a strict ordering
of the descriptor writes before the doorbell writes happen.

Signed-off-by: John Carney <john.carney@broadcom.com>
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>

net/ixgbe/base: add base driver update brief

The ixgbe base driver was updated to version
cid-10g-shared-code.2016.04.12.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

net/ixgbe/base: clean up

Change the parameter bypass_vlvf to vlvf_bypass for consistency
with ixgbe_common.c.

Clean up some whitespace and misalignment.

Change variable type of secrxreg from int to u32 as it's used
to store register value.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

net/ixgbe/base: fix skipping PHY config

By exiting early we could skip the PHY configuration and as such
the driver may not configure the PHY correctly for SFP+.

This patch removes the logic which would previously skip the PHY
configuration in the case where we are already at the requested
speed in ixgbe_setup_mac_link_multispeed_fiber().

Fixes: f3430431abaf ("ixgbe/base: add SFP+ dual-speed support")

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

net/ixgbe/base: remove unneeded flow control code

Support for flow control auto negotiation is defeatured from X550em_a
fiber when connected to speeds lower than 10Gbps. This patch cleans up
the code path which is mostly dead to begin with.

- add device IDs check in ixgbe_device_supports_autoneg_fc().
- ixgbe_fc_autoneg_fiber_x550em_a() is now used only to pass the user
  settings to ixgbe_fc_enable_generic().
- make sure that start_hw does not fail when setup_fc is not implemented.
- small fix in the debug message when ixgbe_device_supports_autoneg_fc()
  returns false.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

net/ixgbe/base: update X550em_a backplane speed

Correct link flow for X550em_a backplane with ALEF.

Report the correct link capabilities:
   SKUs configured for 2.5G only support 2.5G.
   non-10G SKUs can only support 2.5 or 1G.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

net/ixgbe/base: fix possible corruption of shadow RAM

Currently, not all shadow RAM accesses are being done under the
protection of a semaphore, which could result in corruption.

Refactor the code so that it is possible to hold the semaphore
around ixgbe_host_interface_command by introducing an unlocked form.
This patch also eliminates the function ixgbe_read_ee_hostif_data_X550
in favor of the function ixgbe_read_ee_hostif_X550.
The new arrangement is able to get both the management interface semaphore
and the EEPROM semaphore at the same time instead of separately.

Fixes: af75078fece3 ("first public release")

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

net/ixgbe/base: add two MAC ops for Hyper-V

This patch adds negotiate_api_version and set_rlpml into mac_ops. With the
introduction of Hyper-V functionality, we can have separate functions to
accommodate different implementations without have one break the other.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

net/ixgbe/base: add X550em_a FW ALEF support

This patch adds X550em_a FW ALEF support. ALEF is the new unified FW.
The driver uses the KRM_PMD_RX_FLEX_PORT/FLX_MASK_ST20 registers to
configure the lane mode.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

net/ixgbe/base: separate PHY ops init from PHY init

This patch moves PHY ops pointers initialization to
ixgbe_init_phy_ops_X550em and PHY identifying/initializing
to ixgbe_identify_phy_x550em.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

net/ixgbe/base: prevent link speed value conflict

This patch changes the value of IXGBE_LINK_SPEED_10_FULL from 4 to 2,
as 4 is reserved to 100Mbit Half Duplex in E1000 shared code.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

net/ixgbe/base: remove X550em_a 100Mbps

X550em_a only supports 10G/1G link.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

net/ixgbe/base: report autoneg supported for X550

Make sure ixgbe_device_supports_autoneg_fc() returns true for the device
IDs of X550EM_A_1G_T and X550EM_A_1G_T_L.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

net/ixgbe/base: reduce delay for SWFW semaphore

This patch reduces the SWFW semaphore/PHY Token retry delay.

ixgbe_release_swfw_sync_X540: Reduce 5 ms delay after releasing
semaphore to 2 ms. HW team indicated 1 ms delay would be sufficient
for FW access.

ixgbe_acquire_swfw_sync_X540: Remove 5 ms delay after acquiring
semaphore.

ixgbe_acquire_swfw_sync_X550a: Remove 5 ms delay since there are
two 2 ms delays in the semaphore release flow.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

net/ixgbe/base: factorize mailbox write needing ack

ixgbevf_write_msg_read_ack() is now performing mailbox write and read,
so this patch use this function to commonize mailbox write and read.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

net/ixgbe/base: add missing FDIRSCTPM mask setting

This patch adds missing FDIRSCTPM mask setting for tunneled packets.
It should be set the same way as FDIRTCPM and FDIRUDPM so that SCTP
packets can be filtered correctly.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

net/ixgbe/base: set default autoneg speed at reset

This patch avoids the situation where we initialize an adapter but have not
yet set up phy.autoneg_advertised speeds. In that case we could end
up with having no autoneg speeds enabled and therefore get no link until we
reset the link and set the autoneg speeds correctly.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

net/ixgbe/base: use default check link for X550em_a

This patch removes the X550em_a specific check link function and uses
ixgbe_check_mac_link_generic instead. It is not necessary to
check both the MAC link register and external PHY registers when
checking the link.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

net/ixgbe/base: add bounds check in LED functions

Do parameter check to prevent exceptional value being written into
register.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

net/ixgbe/base: add constants for GENEVE UDP port

X550em_a adds GENEVE support by using the upper 16 bits of VXLANCTRL
to store the UDP port (VXLANCTRL.GENEVE_UDP_PORT).

This patch adds definitions that can be used to manipulate the ports
depending on which protocol is being configured.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

net/ixgbe/base: support X550em_a SGMII FC autoneg

Create flow control (FC) setup and enable functions to configure PHY
registers. These registers advertise FC settings according to the user
requested mode. On link establishment, these settings are negotiated
with the link partner to agree on the settings to use: RX and TX enabled,
TX only enabled, or FC disabled and RX enabled (which also enables TX).

Remove the part of code that performs FC auto-negotiation (AN) in
ixgbe_setup_m88 and put it in a new function to maintain consistency
with other FC AN implementations so far. Add function pointers to the
setup-fc and enable-fc functions so that they get called during init
to perform FC AN.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

net/ixgbe/base: bypass checking link for crosstalk

When HW starts, first read the NVM to see if the crosstalk fix should
be used on the given HW and cache that information in the HW structure.

When we check_link we first see if 1) NVM requests this fix 2) if
we are an SFP+ device 3) see if a module is not in the SFP+ cage.
If all the above are true then don't bother checking the link, just
say it is down.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

net/ixgbe/base: define X550 PCIe serial MAC address

Add SERIAL_NUMBER_MAC_ADDR definition for X550.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

net/ixgbe/base: fix check for NACK

Previously we checked return buffer for
(IXGBE_VF_SET_MACVLAN | IXGBE_VT_MSGTYPE_NACK), but this would not
work if index is not 0 and as a result NACK will not be detected.

Fixes: af75078fece3 ("first public release")

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>

net/ixgbe/base: access IOSF by host interface

This patch makes sure that we access IOSF registers through the
host interface command (HIC) for the majority of X550em devices.
All devices with NVM are capable of using the HIC.

For consistency all instances where the ixgbe_write_phy_reg_mdi is called
directly are converted to function pointer calls.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>