The meson for the turbo_sw PMD is updated to prevent the
requirement for any device specific toplevel flags to be
passed down (unlike what used to be the case with make).
The linking to the optional libraries is purely auto
detected at build time and flags are then set appropriately.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com> Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Maxime Coquelin [Tue, 6 Oct 2020 10:04:21 +0000 (12:04 +0200)]
baseband/fpga_lte_fec: fix crash with debug
When RTE_LIBRTE_BBDEV_DEBUG is enabled, rte_device's driver
pointer is dereferenced twice in fpga_lte_fec's probe callback.
It causes a segmentation fault because this pointer is only
assigned after probe callback call.
This patch makes use of rte_pci_driver pointer instead
Fixes: efd453698c49 ("baseband/fpga_lte_fec: add driver for FEC on FPGA") Cc: stable@dpdk.org Signed-off-by: Maxime Coquelin <maxime.coquelin@redhat.com> Acked-by: Nicolas Chautru <nicolas.chautru@intel.com>
Maxime Coquelin [Tue, 6 Oct 2020 10:04:20 +0000 (12:04 +0200)]
baseband/fpga_5gnr_fec: fix crash with debug
When RTE_LIBRTE_BBDEV_DEBUG is enabled, rte_device's driver
pointer is dereferenced twice in fpga_5gnr_fec's probe callback.
It causes a segmentation fault because this pointer is only
assigned after probe callback call.
This patch makes use of rte_pci_driver pointer instead.
Fixes: 0b5927cbcba7 ("baseband/fpga_5gnr_fec: add PMD for FPGA 5GNR FEC") Cc: stable@dpdk.org Signed-off-by: Maxime Coquelin <maxime.coquelin@redhat.com> Acked-by: Nicolas Chautru <nicolas.chautru@intel.com>
Adam Dybkowski [Mon, 28 Sep 2020 14:16:33 +0000 (16:16 +0200)]
crypto/scheduler: rename slave to worker
This patch replaces the usage of the word 'slave' with more
appropriate word 'worker' in QAT PMD and Scheduler PMD
as well as in their docs. Also the test app was modified
to use the new wording.
The Scheduler PMD's public API was modified according to the
previous deprecation notice:
rte_cryptodev_scheduler_slave_attach is now called
rte_cryptodev_scheduler_worker_attach,
rte_cryptodev_scheduler_slave_detach is
rte_cryptodev_scheduler_worker_detach,
rte_cryptodev_scheduler_slaves_get is
rte_cryptodev_scheduler_workers_get.
Also, the configuration value RTE_CRYPTODEV_SCHEDULER_MAX_NB_SLAVES
was renamed to RTE_CRYPTODEV_SCHEDULER_MAX_NB_WORKERS.
Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com> Acked-by: Fan Zhang <roy.fan.zhang@intel.com> Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com> Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
Maxime Coquelin [Fri, 2 Oct 2020 08:59:31 +0000 (10:59 +0200)]
baseband/fpga_lte_fec: fix API naming
DPDK APIs have to be prefixed with "rte_" in order to avoid
namespace pollution.
Let's fix it while fpga_lte_fec API is still experimental. Fixes: efd453698c49 ("baseband/fpga_lte_fec: add driver for FEC on FPGA") Signed-off-by: Maxime Coquelin <maxime.coquelin@redhat.com> Reviewed-by: Tom Rix <trix@redhat.com>
Since librte_ipsec was first introduced in 19.02 and there were no changes
in it's public API since 19.11, it should be considered mature enough to
remove the 'experimental' tag from it.
The RTE_SATP_LOG2_NUM enum is also being dropped from rte_ipsec_sa.h to
avoid possible ABI problems in the future.
Signed-off-by: Conor Walsh <conor.walsh@intel.com> Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Acked-by: Ray Kinsella <mdr@ashroe.eu> Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
Nicolas Chautru [Mon, 5 Oct 2020 22:12:49 +0000 (15:12 -0700)]
baseband/acc100: add configure function
Add configure function to configure the PF from within
the bbdev-test itself without external application
configuration the device.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com> Acked-by: Liu Tianjiao <tianjiao.liu@intel.com> Acked-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Nicolas Chautru [Mon, 5 Oct 2020 22:12:48 +0000 (15:12 -0700)]
baseband/acc100: add debug function to validate input
Debug functions to validate the input API from user
Only enabled in DEBUG mode at build time
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com> Acked-by: Liu Tianjiao <tianjiao.liu@intel.com> Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Nicolas Chautru [Mon, 5 Oct 2020 22:12:47 +0000 (15:12 -0700)]
baseband/acc100: support interrupt
Adding capability and functions to support MSI
interrupts, call backs and inforing.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com> Acked-by: Liu Tianjiao <tianjiao.liu@intel.com> Acked-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Nicolas Chautru [Mon, 5 Oct 2020 22:12:46 +0000 (15:12 -0700)]
baseband/acc100: support 4G processing
Adding capability for 4G encode and decoder processing
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com> Acked-by: Liu Tianjiao <tianjiao.liu@intel.com> Acked-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Nicolas Chautru [Mon, 5 Oct 2020 22:12:45 +0000 (15:12 -0700)]
baseband/acc100: support HARQ loopback
Additional support for HARQ memory loopback
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com> Acked-by: Liu Tianjiao <tianjiao.liu@intel.com> Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Nicolas Chautru [Mon, 5 Oct 2020 22:12:44 +0000 (15:12 -0700)]
baseband/acc100: add LDPC processing functions
Adding LDPC decode and encode processing operations
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com> Acked-by: Liu Tianjiao <tianjiao.liu@intel.com> Acked-by: Dave Burley <dave.burley@accelercomm.com> Acked-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Nicolas Chautru [Mon, 5 Oct 2020 22:12:42 +0000 (15:12 -0700)]
baseband/acc100: add info get function
Add in the "info_get" function to the driver, to allow us to query the
device.
No processing capability are available yet.
Linking bbdev-test to support the PMD with null capability.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com> Acked-by: Liu Tianjiao <tianjiao.liu@intel.com> Acked-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Nicolas Chautru [Mon, 5 Oct 2020 22:12:41 +0000 (15:12 -0700)]
baseband/acc100: add HW register definitions
Add in the list of registers for the device and related
HW specs definitions.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com> Reviewed-by: Rosen Xu <rosen.xu@intel.com> Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Liu Tianjiao <tianjiao.liu@intel.com> Acked-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Nicolas Chautru [Mon, 5 Oct 2020 22:12:40 +0000 (15:12 -0700)]
baseband/acc100: introduce PMD for ACC100
Add stubs for the ACC100 PMD
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com> Reviewed-by: Tom Rix <trix@redhat.com> Acked-by: Liu Tianjiao <tianjiao.liu@intel.com> Acked-by: Maxime Coquelin <maxime.coquelin@redhat.com>
In testsuite_setup(), ts_params is configured for first valid device.
The same device should be used as valid device in
test_device_configure_invalid_dev_id test case.
Fixes: 202d375c60bc ("app/test: add cryptodev unit and performance tests") Cc: stable@dpdk.org Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com> Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
A temporary session is created for sessionless crypto operations.
rte_cryptodev_sym_session_create() should be used for creating the
temporary session as it initializes the session structure in the
correct way. Also the session should be set to 0 before freeing it.
Thomas Monjalon [Mon, 28 Sep 2020 00:00:48 +0000 (02:00 +0200)]
eal: simplify exit functions
The option RTE_EAL_ALWAYS_PANIC_ON_ERROR was off by default,
and not customizable with meson. It is completely removed.
The function rte_dump_registers is a trace of the bare metal support
era, and was not supported in userland. It is completely removed.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net> Acked-by: Ray Kinsella <mdr@ashroe.eu> Acked-by: Bruce Richardson <bruce.richardson@intel.com> Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Acked-by: Kevin Traynor <ktraynor@redhat.com> Acked-by: David Marchand <david.marchand@redhat.com>
Harry van Haaren [Thu, 15 Oct 2020 10:32:37 +0000 (11:32 +0100)]
eal: add new prefetch write variants
This commit adds new rte_prefetchX_write() variants, that suggest to the
compiler to use a prefetch instruction with intention to write. As a
compiler builtin, the compiler can choose based on compilation target
what the best implementation for this instruction is.
Three versions are provided, targeting the different levels of cache.
Signed-off-by: Harry van Haaren <harry.van.haaren@intel.com> Reviewed-by: Jerin Jacob <jerinj@marvell.com> Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
Eli Britstein [Thu, 15 Oct 2020 15:10:17 +0000 (15:10 +0000)]
eal: fix build with conflicting libc variable memory_order
The cited commit introduced functions with 'int memory_order' argument.
The C11 standard section 7.17.1.4 defines 'memory_order' as the
"enumerated type whose enumerators identify memory ordering constraints".
A compilation error occurs:
error: declaration of 'memory_order' shadows a global declaration
[-Werror=shadow]
rte_atomic_thread_fence(int memory_order)
This issue was hit when trying to compile OVS with gcc 4.8.5. This
compiler version does not provide stdatomic.h, so enum memory_order is
redefined in OVS code.
In another case, if the compiler does provide stdatomic.h header,
passing -Wsystem-headers in the CFLAGS will also cause that failure.
Fix it by changing the argument name 'memory_order' to 'memorder'.
Fixes: 672a15056380 ("eal: add wrapper for C11 atomic thread fence") Signed-off-by: Eli Britstein <elibr@nvidia.com> Reviewed-by: Asaf Penso <asafp@nvidia.com> Acked-by: Thomas Monjalon <thomas@monjalon.net> Acked-by: David Marchand <david.marchand@redhat.com> Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
gcc 5.4 fails with:
../lib/librte_acl/acl_run_avx512x8.h: In function 'match_process_avx512x8':
../lib/librte_acl/acl_run_avx512x8.h:382:31: error:
pointer targets in passing argument 1 of '_mm256_mask_i32scatter_epi32'
differ in signedness [-Werror=pointer-sign]
Later gcc versions work fine, as for them parameter type was
changed to 'void *'.
Fixed by applying explicit cast for offending argument.
David Marchand [Wed, 14 Oct 2020 08:14:29 +0000 (10:14 +0200)]
eal: add experimental tags for write combining store
Only marking the doxygen declarations is not enough.
Arch specific implementations must be tagged as well since there is no
common declaration of those inlines.
Fixes: 8a00dfc738fe ("eal: add write combining store") Signed-off-by: David Marchand <david.marchand@redhat.com> Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com> Reviewed-by: Radu Nicolau <radu.nicolau@intel.com>
Modify the test_sched application to build the hierarchical scheduler
with default subport bandwidth profile. It also allows to update
a subport with different subport rates dynamically
Modify the softnic drivers to build the hierarchical scheduler
with default subport bandwidth profile. It also allows to update
a subport with different subport rates dynamically.
Modify the ip_pipeline application to build the hierarchical scheduler
with default subport bandwidth profile. It also allows to update
a subport with different subport rates dynamically
Modify the qos_sched application to build the hierarchical scheduler
with default subport bandwidth profile. It also allows to update
a subport with different subport rates dynamically.
Implement terminal handling, input polling, and vdprintf() for Windows.
Because Windows I/O model differs fundamentally from Unix and there is
no concept of character device, polling is simulated depending on the
underlying input device. Supporting non-terminal input is useful for
automated testing.
Windows emulation of VT100 uses "ESC [ E" for newline instead of
standard "ESC E", so add a workaround.
Extend compatibility header system to support librte_cmdline.
pthread.h has to include windows.h, which exposes struct in_addr, etc.
conflicting with compatibility headers. WIN32_LEAN_AND_MEAN macro
is required to disable this behavior. Use rte_windows.h to define
WIN32_LEAN_AND_MEAN for pthread library.
cmdline: add internal wrappers for character input
poll(3) is a purely Unix facility, so it cannot be directly used by
common code. read(2) is limited in device support outside of Unix.
Create wrapper functions and implement them for Unix.
struct cmdline exposes platform-specific members it contains, most
notably struct termios that is only available on Unix. While ABI
considerations prevent from hinding the definition on already supported
platforms, struct cmdline is considered logically opaque from now on.
Add a deprecation notice targeted at 20.11.
* Remove tests checking struct cmdline content as meaningless.
* Fix missing cmdline_free() in unit test.
* Add cmdline_get_rdline() to access history buffer indirectly.
The new function is currently used only in tests.
Implementation is based on waitable timers Win32 API. When timer is set,
a callback and its argument are supplied to the OS, while timer handle
is stored in EAL alarm list. When timer expires, OS wakes up the
interrupt thread and runs the callback. Upon completion it removes the
alarm.
Waitable timers must be set from the thread their callback will run in,
eal_intr_thread_schedule() provides a way to schedule asyncronuous code
execution in the interrupt thread. Alarm module builds synchronous timer
setup on top of it.
Windows alarms are not a type of DPDK interrupt handle and do not
interact with interrupt module beyond executing in the same thread.
Signed-off-by: Dmitry Kozlyuk <dmitry.kozliuk@gmail.com> Acked-by: Narcisa Vasile <navasile@linux.microsoft.com>
Windows interrupt support is based on IO completion ports (IOCP).
Interrupt thread would send the devices requests to notify about
interrupts and then wait for any request completion. Add skeleton code
of this model without any hardware support.
Another way to wake up the interrupt thread is APC (asynchronous procedure
call), scheduled by any other thread via eal_intr_thread_schedule().
This internal API is intended for alarm implementation.
Signed-off-by: Dmitry Kozlyuk <dmitry.kozliuk@gmail.com> Acked-by: Narcisa Vasile <navasile@linux.microsoft.com>
Pallavi Kadam [Thu, 8 Oct 2020 18:56:45 +0000 (11:56 -0700)]
bus/pci: support netuio on Windows
This patch adds implementations to probe PCI devices bound to netuio
with the help of "netuio" class device changes.
Now Windows will support both "netuio" and "net" device class and
can set kernel driver type based on the device class selection.
Note: Few definitions and structures have been copied from
netuio_interface.h file from
("[v5] windows/netuio: add Windows NetUIO kernel driver") series
and this will be fixed once the exact path for netuio source code is known.
Signed-off-by: John Alexander <john.alexander@datapath.co.uk> Signed-off-by: Pallavi Kadam <pallavi.kadam@intel.com> Reviewed-by: Ranjit Menon <ranjit.menon@intel.com> Reviewed-by: Tal Shnaiderman <talshn@nvidia.com> Reviewed-by: Narcisa Vasile <navasile@linux.microsoft.com>
When create softnic hash table with 16 keys, it failed on 32-bit
environment, because the pointer field in structure rte_bucket_4_16
is only 32 bits. Add a padding field in 32-bit environment to keep
the structure to a multiple of 64 bytes. Apply this to 8-byte and
32-byte key hash function as well.
Current rte_acl_classify_avx512x32() and rte_acl_classify_avx512x16()
code paths are very similar. The only differences are due to
256/512 register/instrincts naming conventions.
So to deduplicate the code:
- Move common code into “acl_run_avx512_common.h”
- Use macros to hide difference in naming conventions
Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
With current ACL implementation first field in the rule definition
has always to be one byte long. Though for optimising classify
implementation it might be useful to do 4B reads
(as we do for rest of the fields).
So at build phase, check user provided field definitions to determine
is it safe to do 4B loads for first ACL field.
Then at run-time this information can be used to choose classify
behavior.
Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Introduce classify implementation that uses AVX512 specific ISA.
rte_acl_classify_avx512x32() is able to process up to 32 flows in parallel.
It uses 512-bit width registers/instructions and provides higher
performance then rte_acl_classify_avx512x16(), but can cause
frequency level change.
Note that for now only 64-bit version is supported.
Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
acl: select 256-bit AVX512 classify method by default
On supported platforms, set RTE_ACL_CLASSIFY_AVX512X16 as
default ACL classify algorithm.
Note that AVX512X16 implementation uses 256-bit registers/instincts only
to avoid possibility of frequency drop.
Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Introduce classify implementation that uses AVX512 specific ISA.
rte_acl_classify_avx512x16() is able to process up to 16 flows in parallel.
It uses 256-bit width registers/instructions only
(to avoid frequency level change).
Note that for now only 64-bit version is supported.
Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
acl: add infrastructure for AVX512 classify methods
Add necessary changes to support new AVX512 specific ACL classify
algorithm:
- changes in meson.build to check that build tools
(compiler, assembler, etc.) do properly support AVX512.
- run-time checks to make sure target platform does support AVX512.
- dummy rte_acl_classify_avx512() for targets where AVX512
implementation couldn't be properly supported.
Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Right now ACL library determines best possible (default) classify method
on a given platform with special constructor function rte_acl_init().
This patch makes the following changes:
- Move selection of default classify method into a separate private
function and call it for each ACL context creation (rte_acl_create()).
- Remove library constructor function
- Make rte_acl_set_ctx_classify() to check that requested algorithm
is supported on given platform.
The purpose of these changes to improve and simplify algorithm selection
process and prepare ACL library to be integrated with the
max SIMD bitwidth series in discussion.
Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Removal of unused enum value (RTE_ACL_CLASSIFY_NUM).
This enum value is not used inside DPDK, while it prevents
to add new classify algorithms without causing an ABI breakage.
Note that this change introduce a formal ABI incompatibility
with previous versions of ACL library.
Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
Right now we define dummy version of rte_acl_classify_avx2()
when both X86 and AVX2 are not detected, though it should be
for non-AVX2 case only.
Fixes: e53ce4e41379 ("acl: remove use of weak functions") Cc: stable@dpdk.org Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Reviewed-by: David Marchand <david.marchand@redhat.com>
Jim Harris [Tue, 13 Oct 2020 17:03:16 +0000 (10:03 -0700)]
bus/pci: copy new id for inserted device on Linux
When a device is inserted into an existing BDF slot
that has not been probed, we must overwrite the old
PCI ID with the ID of the new function. Otherwise
we may not probe the function with the correct driver,
if at all.
Signed-off-by: Jim Harris <james.r.harris@intel.com>
This patch enables the optimized calculation of CRC32-Ethernet and
CRC16-CCITT using the AVX512 and VPCLMULQDQ instruction sets. This CRC
implementation is built if the compiler supports the required instruction
sets. It is selected at run-time if the host CPU, again, supports the
required instruction sets.
Signed-off-by: Mairtin o Loingsigh <mairtin.oloingsigh@intel.com> Signed-off-by: David Coyle <david.coyle@intel.com> Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Reviewed-by: Jasvinder Singh <jasvinder.singh@intel.com> Reviewed-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
This patch adds support for run-time selection of the optimal
architecture-specific CRC path, based on the supported instruction set(s)
of the CPU.
The compiler option checks have been moved from the C files to the meson
script. The rte_cpu_get_flag_enabled function is called automatically by
the library at process initialization time to determine which
instructions the CPU supports, with the most optimal supported CRC path
ultimately selected.
Signed-off-by: Mairtin o Loingsigh <mairtin.oloingsigh@intel.com> Signed-off-by: David Coyle <david.coyle@intel.com> Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Reviewed-by: Jasvinder Singh <jasvinder.singh@intel.com> Reviewed-by: Pablo de Lara <pablo.de.lara.guarch@intel.com> Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com> Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Wei Hu (Xavier) [Wed, 19 Aug 2020 10:56:37 +0000 (18:56 +0800)]
eal/arm64: update CPU flags
ARM64 Linux kernel updated the CPU flags using the HWCAP scheme.
The related marco definition can be found in linux kernel:
arch/arm64/include/uapi/asm/hwcap.h
This patch incorporates those changes to the EAL library.
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com> Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
Ruifeng Wang [Fri, 11 Sep 2020 15:39:59 +0000 (23:39 +0800)]
config: remap flags used for Arm platforms
RTE_ARCH_xx flags are used to distinguish platform architectures.
These flags can be used to pick different code paths for different
architectures at compile time.
For Arm platforms, there are 3 flags in use: RTE_ARCH_ARM,
RTE_ARCH_ARMv7 and RTE_ARCH_ARM64.
RTE_ARCH_ARM64 is for 64-bit aarch64 platforms,
and RTE_ARCH_ARM & RTE_ARCH_ARMv7 are for 32-bit platforms.
RTE_ARCH_ARMv7 is for ARMv7 platforms as its name suggested.
The issue is meaning of RTE_ARCH_ARM is not clear enough.
Because no info about platform word length is included in the name.
To make the flag names more clear, a naming scheme is proposed.
RTE_ARCH_ARM (all Arm platforms)
|
+----RTE_ARCH_32 (New. 32-bit platforms of all architectures)
| |
| +----RTE_ARCH_ARMv7 (ARMv7 platforms)
| |
| +----RTE_ARCH_ARMv8_AARCH32 (aarch32 state on aarch64 machine)
|
+----RTE_ARCH_64 (64-bit platforms of all architectures)
|
+----RTE_ARCH_ARM64 (64-bit Arm platforms)
RTE_ARCH_32 will be explicitly defined for 32-bit platforms.
To fit into the new naming scheme, current usage of RTE_ARCH_ARM in
project is mapped to (RTE_ARCH_ARM && RTE_ARCH_32).
Juraj Linkeš [Fri, 9 Oct 2020 09:50:32 +0000 (11:50 +0200)]
config: add -moutline-atomics to default Arm build
-moutline-atomics allows LSE instructions to be used if available when
compiling for ARMv8.0 instruction set. It's enabled by default on newer
compilers, such as gcc-10.1. Enable the option in case an earlier
compiler version is used for the default build that lacks either -mcpu
or -mtune which would otherwise enable it.
Signed-off-by: Juraj Linkeš <juraj.linkes@pantheon.tech>
Radu Nicolau [Wed, 23 Sep 2020 14:22:52 +0000 (14:22 +0000)]
net/ixgbe: use write combining store for tail updates
Performance improvement: use a write combining store
instead of a regular mmio write to update queue tail
registers.
Signed-off-by: Radu Nicolau <radu.nicolau@intel.com> Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Reviewed-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Radu Nicolau [Wed, 23 Sep 2020 14:22:50 +0000 (14:22 +0000)]
net/i40e: use write combining store for tail updates
Performance improvement: use a write combining store
instead of a regular mmio write to update queue tail
registers.
Signed-off-by: Radu Nicolau <radu.nicolau@intel.com> Acked-by: Bruce Richardson <bruce.richardson@intel.com> Reviewed-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Radu Nicolau [Wed, 23 Sep 2020 14:22:49 +0000 (14:22 +0000)]
eal: add write combining store
Add rte_write32_wc and rte_write32_wc_relaxed functions
that implement 32bit stores using write combining memory protocol.
Provided generic stubs and x86 implementation.
Signed-off-by: Radu Nicolau <radu.nicolau@intel.com> Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Nick Connolly [Mon, 12 Oct 2020 19:28:03 +0000 (20:28 +0100)]
mem: fix allocation failure on non-NUMA kernel
Running dpdk-helloworld on Linux with lib numa present, but no kernel
support for NUMA (CONFIG_NUMA=n) causes rte_service_init() to fail with
EAL: error allocating rte services array.
alloc_seg() calls get_mempolicy to verify that the allocation
has happened on the correct socket, but receives ENOSYS from
the kernel and fails the allocation.
The allocated socket should only be verified if check_numa() is true.
Fixes: 2a96c88be83e ("mem: ease init in a docker container") Cc: stable@dpdk.org Signed-off-by: Nick Connolly <nick.connolly@mayadata.io> Reviewed-by: Nicolas Dichtel <nicolas.dichtel@6wind.com> Acked-by: Anatoly Burakov <anatoly.burakov@intel.com>
Min Hu (Connor) [Fri, 9 Oct 2020 13:37:32 +0000 (21:37 +0800)]
maintainers: update for bonding
Adding Connor as additional maintainer to bonding.
Signed-off-by: Min Hu (Connor) <humin29@huawei.com> Reviewed-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Acked-by: Ferruh Yigit <ferruh.yigit@intel.com>
Chas Williams [Thu, 1 Oct 2020 10:22:44 +0000 (06:22 -0400)]
net: check segment pointer in raw checksum processing
If the overall pkt_len and segment lengths are out of agreement,
it is possible for the seg to be NULL after the loop. Add assert
to check this condition in debug builds. Otherwise, return failure.
Fixes: c442fed81bb9 ("net: add function to calculate checksum in mbuf") Cc: stable@dpdk.org Signed-off-by: Chas Williams <3chas3@gmail.com>
When compiling for a slightly different architecture, e.g. 32-bit on 64-bit
systems using CFLAGS rather than a cross-file, the pcap-config utility can
often return parameters that are unusable for the build in question, i.e.
providing the native 64-bit library paths rather than checking for 32-bit
equivalent.
Since many distros now include a version of libpcap with a
pkg-config file, and for those that don't find-library should work ok as a
fallback, we can explicitly just use pkg-config in the dependency search,
causing meson to skip trying to use pcap-config.
Cc: stable@dpdk.org Signed-off-by: Bruce Richardson <bruce.richardson@intel.com> Reviewed-by: Luca Boccassi <bluca@debian.org> Tested-by: David Marchand <david.marchand@redhat.com>
David Marchand [Fri, 9 Oct 2020 07:15:54 +0000 (09:15 +0200)]
eal: fix doxygen for EAL cleanup
Align rte_eal_cleanup return codes description to the rest of dpdk.
Fixes: aec9c13c5257 ("eal: add function to release internal resources") Cc: stable@dpdk.org Signed-off-by: David Marchand <david.marchand@redhat.com> Acked-by: Thomas Monjalon <thomas@monjalon.net>
Min Hu (Connor) [Thu, 8 Oct 2020 10:02:56 +0000 (18:02 +0800)]
app/testpmd: add FEC command
This commit adds testpmd capability to query and config FEC
function of device. This includes:
- show FEC capabilities, example:
testpmd> show port 0 fec capabilities
- show FEC mode, example:
testpmd> show port 0 fec_mode
- config FEC mode, example:
testpmd> set port <port_id> fec_mode auto|off|rs|baser
where:
auto|off|rs|baser are four kinds of FEC mode which dev
support according to MAC link speed.
Signed-off-by: Min Hu (Connor) <humin29@huawei.com> Reviewed-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Reviewed-by: Chengwen Feng <fengchengwen@huawei.com> Reviewed-by: Chengchang Tang <tangchengchang@huawei.com>
Min Hu (Connor) [Thu, 8 Oct 2020 10:02:55 +0000 (18:02 +0800)]
net/hns3: support FEC
Forward error correction (FEC) is a bit error correction mode.
It adds error correction information to data packets at the
transmit end, and uses the error correction information to correct
the bit errors generated during data packet transmission at the
receive end. This improves signal quality but also brings a delay
to signals. This function can be enabled or disabled as required.
This patch adds FEC support for ethdev.Introduce ethdev
operations which support query and config FEC information in
hardware.
Signed-off-by: Min Hu (Connor) <humin29@huawei.com> Reviewed-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Reviewed-by: Chengwen Feng <fengchengwen@huawei.com> Reviewed-by: Chengchang Tang <tangchengchang@huawei.com>
Robin Zhang [Sun, 27 Sep 2020 07:26:23 +0000 (07:26 +0000)]
net/iavf: disable promiscuous mode on close
In scenario of Kernel Driver runs on PF and PMD runs on VF, PMD exit
doesn't disable promiscuous mode, this will cause vlan filter set by
Kernel Driver will not take effect.
This patch will fix it, add promiscuous disable at device disable.
Signed-off-by: Robin Zhang <robinx.zhang@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com>
Robin Zhang [Sun, 27 Sep 2020 07:26:21 +0000 (07:26 +0000)]
net/iavf: re-program promiscuous mode on VF interface
During a kernel PF reset, this event is propagated to the VF.
The DPDK VF PMD will execute the reset task before the PF is done
with his. This results in the admin queue message not being responded
to leaving the port in "promiscuous" mode.
This patch makes sure the promiscuous mode is configured independently
of the current admin state.
Signed-off-by: Robin Zhang <robinx.zhang@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com>
Robin Zhang [Sun, 27 Sep 2020 07:26:20 +0000 (07:26 +0000)]
net/iavf: set min and max MTU for VF
This commit sets the min and max supported MTU values for iavf VF
devices via the iavf_dev_info_get() function. Min MTU supported
is set to RTE_ETHER_MIN_MTU and max MTU is calculated as the max
packet length supported minus the transport overhead.
Signed-off-by: Robin Zhang <robinx.zhang@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com>
git.droids-corp.org / dpdk.git / log