net/hns3: fix VF handling LSC event in secondary process
VF will build two queues (csq: command send queue, crq: command receive
queue) with firmware, the crq may contain the following messages:
1) mailbox response message which was the ack of mailbox sync request.
2) PF's link status change message which may send by PF at anytime;
Currently, any threads in the primary and secondary processes could
send mailbox sync request, so it will need to process the crq messages
in there own thread context.
If the crq hold two messages: a) PF's link status change message, b)
mailbox response message when secondary process deals with the crq
messages, it will lead to report lsc event in secondary process
because it uses the policy of processing all pending messages at once.
We use the following scheme to solve it:
1) threads in secondary process could only process specifics messages
(eg. mailbox response message) in crq, if the message processed, its
opcode will rewrite with zero, then the intr thread in primary
process will not process again.
2) threads other than intr thread in the primary process use the same
processing logic as the threads in secondary process.
3) intr thread in the primary process could process all messages.
Fixes: 76a3836b98c4 ("net/hns3: fix setting default MAC address in bonding of VF") Fixes: 463e748964f5 ("net/hns3: support mailbox") Cc: stable@dpdk.org Signed-off-by: Chengwen Feng <fengchengwen@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
net/hns3: fix possible mismatched response of mailbox
Currently, the mailbox synchronous communication between VF and PF use
the following fields to maintain communication:
1. Req_msg_data which was combined by message code and subcode, used to
match request and response.
2. Head which means the number of requests successfully sent by VF.
3. Tail which means the number of responses successfully received by VF.
4. Lost which means the number of requests which are timeout.
There may possible mismatches of the following situation:
1. VF sends message A with code=1 subcode=1.
Then head=1, tail=0, lost=0.
2. PF was blocked about 500ms when processing the message A.
3. VF will detect message A timeout because it can't get the response
within 500ms.
Then head=1, tail=0, lost=1.
4. VF sends message B with code=1 subcode=1 which equal message A.
Then head=2, tail=0, lost=1.
5. PF processes the first message A and send the response message to VF.
6. VF will update tail field to 1, but the lost field will remain
unchanged because the code/subcode equal message B's, so driver will
return success because now the head(2) equals tail(1) plus lost(1).
This will lead to mismatch of request and response.
To fix the above bug, we use the following scheme:
1. The message sent from VF was labelled with match_id which was a
unique 16-bit non-zero value.
2. The response sent from PF will label with match_id which got from the
request.
3. The VF uses the match_id to match request and response message.
This scheme depends on the PF driver, if the PF driver don't support
then VF will uses the original scheme.
Fixes: 463e748964f5 ("net/hns3: support mailbox") Cc: stable@dpdk.org Signed-off-by: Chengwen Feng <fengchengwen@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
Currently, driver will copy mailbox messages body into arq ring when
process HNS3_MBX_LINK_STAT_CHANGE and HNS3_MBX_LINK_STAT_CHANGE
message, and then call hns3_mbx_handler API which will direct process
pre-copy messages. In the whole process, the arq ring don't have a
substantial effect.
Note: The arq ring is designed for kernel environment which could not
do much job in interrupt context, but for DPDK it's not required.
Also we rename hns3_handle_link_change_event to
hns3pf_handle_link_change_event which add 'pf' suffix to make it
better to distinguish.
Fixes: 463e748964f5 ("net/hns3: support mailbox") Cc: stable@dpdk.org Signed-off-by: Chengwen Feng <fengchengwen@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
Wenzhuo Lu [Wed, 14 Apr 2021 07:34:09 +0000 (15:34 +0800)]
net/iavf: add offload path for Rx AVX512 flex descriptor
Add a specific path for RX AVX512 (flexible descriptor).
In this path, support the HW offload features, like,
checksum, VLAN stripping, RSS hash.
This path is chosen automatically according to the
configuration.
'inline' is used, then the duplicate code is generated
by the compiler.
Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com>
Wenzhuo Lu [Wed, 14 Apr 2021 07:34:08 +0000 (15:34 +0800)]
net/iavf: add offload path for Rx AVX512
Add a specific path for RX AVX512 (traditional).
In this path, support the HW offload features, like,
checksum, VLAN stripping, RSS hash.
This path is chosen automatically according to the
configuration.
'inline' is used, then the duplicate code is generated
by the compiler.
Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com>
Wenzhuo Lu [Wed, 14 Apr 2021 07:34:07 +0000 (15:34 +0800)]
net/iavf: add offload path for Tx AVX512
Add a specific path for TX AVX512.
In this path, support the HW offload features, like,
checksum insertion, VLAN insertion.
This path is chosen automatically according to the
configuration.
'inline' is used, then the duplicate code is generated
by the compiler.
Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com>
Raslan Darawsheh [Tue, 23 Mar 2021 12:11:34 +0000 (14:11 +0200)]
ethdev: update flow item GTP QFI definition
'qfi' field is 8 bits which represent single bit for
PPP (paging Policy Presence) single bit for RQI
(Reflective QoS Indicator) and 6 bits for QFI
(QoS Flow Identifier)
This is based on RFC 38415-g30
https://www.3gpp.org/ftp/Specs/archive/38_series/38.415/38415-g30.zip
Updated the doxygen comment and the mask for 'qfi'
to properly identify the full 8 bits of the field.
note: changing the default mask would cause different
patterns generated by testpmd.
Huisong Li [Wed, 14 Apr 2021 03:02:05 +0000 (11:02 +0800)]
app/testpmd: fix bitmap of link speeds when force speed
Currently, when the user sets force link speed through 'link_speeds',
bit(0) of 'link_speeds' is not set to 1(ETH_LINK_SPEED_FIXED),
which conflicts with the definition.
Fixes: 88fbedcd5e5a ("app/testpmd: move speed and duplex parsing in a function") Cc: stable@dpdk.org Signed-off-by: Huisong Li <lihuisong@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> Acked-by: Ferruh Yigit <ferruh.yigit@intel.com> Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Haifei Luo [Wed, 14 Apr 2021 10:20:00 +0000 (13:20 +0300)]
app/testpmd: add command for single flow dump
Add support for single flow dump.
The CLIs to dump one rule: flow dump PORT rule ID
to dump all: flow dump PORT all
Examples:
testpmd> flow dump 0 all
testpmd> flow dump 0 rule 0
Signed-off-by: Haifei Luo <haifeil@nvidia.com> Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Li Zhang [Tue, 13 Apr 2021 15:59:55 +0000 (18:59 +0300)]
app/testpmd: add meter profile packet mode option
add meter profile packet_mode to the ethernet device.
One example:
add port meter profile rfc2697 (port_id) (profile_id)
(cir) (cbs) (ebs) (packet_mode)
Li Zhang [Tue, 13 Apr 2021 15:59:54 +0000 (18:59 +0300)]
ethdev: add packet mode in meter profile structure
Currently meter algorithms only supports rate is bytes per second (BPS).
Add packet_mode flag in meter profile parameters data structure.
So that it can meter traffic by packet per second.
When packet_mode is 0, the profile rates and bucket sizes are
specified in bytes per second and bytes
when packet_mode is not 0, the profile rates and bucket sizes are
specified in packets and packets per second.
The below structure will be extended:
rte_mtr_meter_profile
rte_mtr_capabilities
Signed-off-by: Li Zhang <lizh@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com> Acked-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com> Acked-by: Jerin Jacob <jerinj@marvell.com> Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Haiyue Wang [Tue, 13 Apr 2021 05:14:59 +0000 (13:14 +0800)]
net/ice: update QinQ switch filter handling
The hardware outer/inner VLAN protocol types are now updated to map to
new interface VLAN protocol types, so update the application to use new
VLAN protocol types when the rte_flow is QinQ filter type.
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com>
net/ice/base: allow GTP-U filter using only inner protocols
Adds a support for switch filter: GTP-U using just inner fields.
If user doesn't specify outer protocol and its fields but wants to
add switch filter for GTP-U using inner protocols and related fields
such as inner L3 and/or inner L4, this patch enables such filtering.
net/ice/base: add inner VLAN protocol type for QinQ filter
Since VLAN protocol type 'ICE_VLAN_OFOS' has been changed to map
the hardware VLAN protocol ID to 'ICE_VLAN_OF_HW (16)' when in Double
VLAN mode, and to 'ICE_VLAN_OL_HW (17)' when in Single VLAN mode.
So 'ICE_VLAN_OFOS' can't be used with 'ICE_VLAN_EX' which is outer VLAN
hardware protocol ID 'ICE_VLAN_OF_HW (16)' to do the QinQ VLAN pattern.
Introduce the new inner VLAN protocol type 'ICE_VLAN_IN', which is inner
VLAN hardware protocol ID 'ICE_VLAN_OL_HW (17)'.
Now for QinQ VLAN pattern, the protocol 'ICE_VLAN_EX' and 'ICE_VLAN_IN'
should be used to set the related protocol header fields like VLAN ID.
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com> Acked-by: Qiming Yang <qiming.yang@intel.com>
Add helper functions to set the GPIO pin state or get the value of a
GPIO signal that's the part of the topology based on AQ commands.
This change is needed to setup GPIO pins state for PTP, SyncE etc.
Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com> Acked-by: Qiming Yang <qiming.yang@intel.com>
Enable I2C read/write AQ commands. They are now required for
controlling the external physical connectors via external I2C
port expander on E810-T adapters.
Signed-off-by: Maciej Machnikowski <maciej.machnikowski@intel.com> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com> Acked-by: Qiming Yang <qiming.yang@intel.com>
Protocol id for first vlan in Double VLAN Mode (DVM) should be
ICE_VLAN_OF_HW = 16, but for Single VLAN Mode (SVM) this should be
ICE_VLAN_OL_HW = 17.
Change protocol id in type to id translation array for outer vlan
to 17 when DVM is enabled, which means the driver, package,
and firmware support DVM.
Signed-off-by: Michal Swiatkowski <michal.swiatkowski@intel.com> Signed-off-by: Haiyue Wang <haiyue.wang@intel.com> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com> Acked-by: Qiming Yang <qiming.yang@intel.com>
net/ice/base: remove unused ptype field in PTT definition
Remove the unused ptype entry, and use the gcc extension for
ranged initializers in arrays for Linux, and explicitly target
each table entry by index when initializing under Linux.
net/ice/base: support removing VSI from flow profile
Adding a function ice_flow_rem_vsi_prof() to remove flow entries
associated to the SW VSI handle. Once complete, clear the vsi index from
the flow profile bitmap. This will ensure that a VSI once removed
can be re-added and the package block rules will be added again.
1. There are a lots of function header mismatch its function name.
2. remove unnecessary header file include.
3. remove unnecessary macro.
4. remove unnecessary comment.
Signed-off-by: Dave Ertman <david.m.ertman@intel.com> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com> Acked-by: Qiming Yang <qiming.yang@intel.com>
Jiawei Wang [Fri, 9 Apr 2021 12:33:28 +0000 (15:33 +0300)]
net/mlx5: fix resource release for mirror flow
The mlx5 PMD allocated the resources of the sample actions, and then
moved these ones to the destination actions array. The original indices
were not cleared and the resources were referenced twice in the
flow object - as the fate actions and in the destination actions array.
This causes the failure on flow destroy because PMD tried to release the
same objects twice.
The patch clears the original indices, add the missed checking for zero
and eliminates multiple object releasing.
Fixes: 00c10c22118a ("net/mlx5: update translate function for mirroring") Cc: stable@dpdk.org Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com> Reviewed-by: Suanming Mou <suanmingm@nvidia.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
If RSS action contains non zero hash key length and NULL
key buffer pointer the default hash key should be used.
The check for the NULL pointer this was missing in the mlx4
PMD causing crash, for example, in testpmd with command:
flow validate 0 ingress group 0
pattern eth / ipv4 / end
actions rss queues 0 end key_len 40 / end
Xiaoyu Min [Tue, 30 Mar 2021 13:40:32 +0000 (21:40 +0800)]
net/mlx5: fix redundant flow after RSS expansion
When RSS expand, if there is no expansion happened but completion
happened because user only input next protocol field instead of item
i.e, ether type == 0x8100 instead of VLAN, an extra flow is created with
missing item in order to filter traffic strictly.
However, after [1] and [2] the rte_flow_item_eth itself is enough to
filter out VLAN traffic, the VLAN item is not needed.
[1]: commit 09315fc83861 ("ethdev: add VLAN attributes to ethernet and VLAN items")
[2]: commit 86b59a1af671 ("net/mlx5: support VLAN matching fields")
This redundant flow will cause failure in some scenarios on group 0 due
to they are the same FTE.
Extend the range of immediate value used in the MODIFY_FIELD action
from 32 to 64 bits to conform to the rte_flow_action_modify_data spec.
Apply appropriate big endian conversion to the immediate value
according to a destination field bit width.
Fixes: 641dbe4fb053 ("net/mlx5: support modify field flow action") Cc: stable@dpdk.org Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Converting modify_field action masks to the big endian format is wrong
for small (less than 4 bytes) fields. Use the BE conversions appropriate
for a field size, not rte_cpu_to_be_32 for everything.
Fixes: 144127ba5660 ("net/mlx5: adjust modify field action endianness") Cc: stable@dpdk.org Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Mellanox hardware can only modify any packet field in 32-bit chunks,
which means 4 such chunks are needed to modify an IPv6 address.
The modification order of these chunks starts from the most significant
bits for the IPv6 address. That leads to confusing results when trying
to modify either source or destination address via the MODIFY_FIELD
action. Fix the order of 32-bit chunks for IPv6 addresses modification
by starting from the least significant bits.
Fixes: 641dbe4fb053 ("net/mlx5: support modify field flow action") Cc: stable@dpdk.org Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Tal Shnaiderman [Tue, 6 Apr 2021 07:31:59 +0000 (10:31 +0300)]
net/mlx5: fix link speed calculation on Windows
In Windows DevX returns the rate of the current link speed
in bit/s, this rate was converted to Mibit/s instead of the Mbit/s
rate expected by DPDK resulting in wrong link speed reporting.
Fixes: 6fbd73709ee4 ("net/mlx5: support link update on Windows") Cc: stable@dpdk.org Signed-off-by: Tal Shnaiderman <talshn@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com>
net/mlx5: check extended metadata for meta modification
The MODIFY_FIELD action requires the extended metadata support
in order to manipulate on METADATA register as well as on MARK register.
Check if it is supported and reject the MODIFY_FIELD action if it is not
just like it was done before for the MARK register modifications.
Fixes: 0588d64ffde3 ("net/mlx5: check extended metadata for mark modification") Cc: stable@dpdk.org Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Wenwu Ma [Fri, 2 Apr 2021 13:52:47 +0000 (13:52 +0000)]
net/ice: fix illegal access when removing MAC filter
When removing the mac filter in ice_remove_all_mac_vlan_filters(),
TAILQ_FOREACH_SAFE should be used instead of TAILQ_FOREACH,
Otherwise, it will result in a illegal pointer access.
Fixes: e0dcf94a0d7f ("net/ice: support VLAN ops") Cc: stable@dpdk.org Signed-off-by: Wenwu Ma <wenwux.ma@intel.com> Tested-by: Zhihong Peng <zhihongx.peng@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com>
According to E1000_ETH_OVERHEAD definition, max_rx_pkt_len contains
one VLAN tag size. Therefore when config RLPML register, if dual VLAN
not enabled there is no need to add VLAN tag size to max_rx_pkt_len,
otherwise only one another VLAN tag size should be added to.
Fixes: e51abef39382 ("igb: fix max RX packet size and support dual VLAN") Cc: stable@dpdk.org Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com> Tested-by: Lingli Chen <linglix.chen@intel.com> Acked-by: Haiyue Wang <haiyue.wang@intel.com>
John Daley [Mon, 12 Apr 2021 20:50:21 +0000 (13:50 -0700)]
net/enic: fix completion pointer calculation
The completion queue index could be implicitly extended past its
uint16_t size when multiplied by the size of the descriptor. While
this should not be a problem, coverity flags it. Do the extension
explicitly by casting the index to uintptr_t.
Coverity issue: 161317 Fixes: 8b428cb5a92e ("net/enic: use 64B completion queue entries if available") Cc: stable@dpdk.org Signed-off-by: John Daley <johndale@cisco.com> Reviewed-by: Hyong Youb Kim <hyonkim@cisco.com>
Ivan Malov [Sat, 10 Apr 2021 00:51:43 +0000 (03:51 +0300)]
common/sfc_efx/base: fix indication of MAE encap support
The indication fields in the MCDI response are individual
bits, but the current code mistakenly compares the larger
dword with 1. This breaks encap. type discovery. Fix that.
Fixes: 891408c45a63 ("common/sfc_efx/base: indicate MAE support for encapsulation") Cc: stable@dpdk.org Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru> Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru> Reviewed-by: Andy Moreton <amoreton@xilinx.com>
net/hns3: fix configure FEC when concurrent with reset
Currently, after the reset is complete, the PMD restores the FEC
according to the FEC configuration reserved in the driver. If there is a
concurrency between the FEC setup operation and the restore operation
after a reset, the FEC status of the last hardware may be unknown.
This patch adds the step of obtaining the lock when setting the FEC to
avoid concurrency between restore operation and setting operation.
Fixes: 9bf2ea8dbc65 ("net/hns3: support FEC") Cc: stable@dpdk.org Signed-off-by: Chengchang Tang <tangchengchang@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
net/hns3: fix queue state when concurrent with reset
At the end of the reset, the state of queues need to be restored
according to the states saved in the driver. If the start and stop
operations of the queues are concurrent at this time, it may cause the
final status to be uncertain.
This patch requires queues to acquire the hw lock before starting and
stopping. If the device is being restored due to reset at this time, it
will block until the reset is completed.
Fixes: fa29fe45a7b4 ("net/hns3: support queue start and stop") Cc: stable@dpdk.org Signed-off-by: Chengchang Tang <tangchengchang@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
During the task queue pairs reset, the getimeofday is used to obtain the
timestamp to determine whether the command execution times out. But
gettimeofday is not monotonous, it can be modified by system
administrators, so the timing may not be accurate or even cause the loop
to wait consistently.
And actually, in this scenario, it is not necessary to obtain the
timestamp.
This patch removes the operation of obtaining the timestamp from the task
queue pairs reset function.
Fixes: bba636698316 ("net/hns3: support Rx/Tx and related operations") Cc: stable@dpdk.org Signed-off-by: Chengchang Tang <tangchengchang@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
Currently, the packet type calculated by
vlan/ovlan/l3id/l4id/ol3id/ol4id fields have the following problems:
1) Identify error when exist VLAN strip which will lead to the data
buffer has non VLAN header but mbuf's ptype have L2_ETHER_VLAN flag.
2) Some packet identifies error, eg: hardware report it's RARP or
unknown packet, but ptype will marked with L2_ETHER .
So driver will calculate packet type only by l3id/l4id/ol3id/ol4id
fields.
Fixes: 0e98d5e6d9c3 ("net/hns3: fix packet type report in Rx") Fixes: bba636698316 ("net/hns3: support Rx/Tx and related operations") Cc: stable@dpdk.org Signed-off-by: Chengwen Feng <fengchengwen@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
Currently, if RAS interrupt and FLR occurred at the same time, FLR will
be detected and corresponding schedule state will be set during RAS
interrupt processing. However, the schedule state value will be
overridden in subsequent RAS processing, resulting in FLR processing
failure. This patch solves this problem.
Fixes: 2790c6464725 ("net/hns3: support device reset") Cc: stable@dpdk.org Signed-off-by: Hongbo Zheng <zhenghongbo3@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
Currently, there are four control variables (rx_simple_allowed,
rx_vec_allowed, tx_simple_allowed and tx_vec_allowed) which are used
to impact the selection of Rx/Tx burst function.
The purpose of the design is to provide a way to control the selection
of Rx/Tx burst function by modifying it's values, but these variables
have no entry to modify unless make intrusive modifications.
Now we already support runtime config to select Rx/Tx function, these
variables could be removed.
Fixes: a124f9e9591b ("net/hns3: add runtime config to select IO burst function") Signed-off-by: Chengwen Feng <fengchengwen@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
Currently, PF driver will report lsc when it detects the link status
change, it's not a generic implementation.
We refactor PF lsc event report by following scheme:
1. PF driver marks RTE_PCI_DRV_INTR_LSC in rte_pci_driver by default.
2. In the init stage, PF driver will detect whether firmware supports
lsc interrupt or not, driver will clear RTE_ETH_DEV_INTR_LSC flag if
firmware doesn't support lsc interrupt.
3. PF driver will report lsc event only when dev_conf.intr_conf.lsc is
set.
Note: If the firmware supports lsc interrupt, we also keep periodic
polling to deal with the interrupt loss.
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
Currently, VF driver periodically obtains link status from PF kernel
driver, and reports lsc event when detects link status change. Because
the period is 1 second, it's probably too late to report especially
in such as bonding scenario.
To solve this problem we use the following scheme:
1. PF kernel driver support immediate push link status to all VFs when
it detects the link status changes.
2. VF driver will detect PF kernel driver whether support push link
status in device init stage by sending request link info mailbox
message to PF, PF then tell VF the push capability by extend
HNS3_MBX_LINK_STAT_CHANGE mailbox message.
3. VF driver marks RTE_PCI_DRV_INTR_LSC in rte_pci_driver by default,
when it detects PF doesn't support push link status then it will clear
RTE_ETH_DEV_INTR_LSC flag.
So if PF kernel driver supports push link status to VF, then VF driver
will have RTE_ETH_DEV_INTR_LSC capability.
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
In GCC compiler, __builtin_constant_p(exp) is a function.
The function returns the integer 1 if the argument is known to be
a compile-time constant.
Therefore, __builtin_constant_p(0xffffff << 8) returned 1.
As the result, rte_flow_item_vxlan_mask was initiated to
{{
{flags = 0x0, rsvd0 = {0x0, 0x0, 0x0},
vni = {0x0, 0x0, 0x0}, rsvd1 = 0x1},
hdr = {vx_flags = 0x0, vx_vni = 0x1000000}}}
}}
GCC fails initialization
rte_flow_item_vxlan_mask.hdr.vni = (0xffffff << 8)
with "initializer element is not a constant expression" error.
Use immediate 0xffffff00 value instead.
buildtools/list-dir-globs.py printed paths with OS directory separator,
which is "/" on Unices and "\" on Windows, while Meson code always
expected "/". This resulted in all drivers being disabled on Windows.
Replace "\" with "/" in script output. Forward slash is a valid,
although non-default, separator on Windows, so no paths can be broken
by this substitution.
Fixes: ab9407c3addd ("build: allow using wildcards to disable drivers") Cc: stable@dpdk.org Signed-off-by: Dmitry Kozlyuk <dmitry.kozliuk@gmail.com> Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Asaf Penso [Wed, 24 Feb 2021 08:53:24 +0000 (08:53 +0000)]
doc: add links for build requirements per OS
To compile with meson some dependencies should be installed.
Section "Getting the Tools" describes what needed, but per
OS there are additional steps to do.
Add links to Linux, FreeBSD, and Windows guide for more info.
Jie Zhou [Wed, 24 Feb 2021 23:36:52 +0000 (15:36 -0800)]
doc: update minimum required Meson version for Windows
Meson with Windows clang generates incorrect linker flag
"--subsystem,console" instead of "/subsystem:console" which
will fail the DPDK build. This is discovered at porting testpmd.
Meson 0.57.0 has the fix and should be used for DPDK Windows build.
Update the WindowsGSG DPDK Build document for the proper meson version.
Signed-off-by: Jie Zhou <jizh@microsoft.com> Acked-by: Dmitry Kozlyuk <dmitry.kozliuk@gmail.com>
Gabriel Ganne [Tue, 23 Mar 2021 09:52:19 +0000 (10:52 +0100)]
build: update minimum required Meson version
Bump Meson required version to 0.49.2 which is chosen so as
to be provided by both redhat-8 and debian-10.
Update documentation and travis setup script accordingly.
This fixes the following warning:
WARNING: Project targeting '>= 0.47.1' but tried to use feature introduced
in '0.48.0': console arg in custom_target
'console' argument is used within kernel/linux/kni/meson.build
Signed-off-by: Gabriel Ganne <gabriel.ganne@6wind.com> Acked-by: Bruce Richardson <bruce.richardson@intel.com> Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
In the example application the key can be provided by the user or
generated randomly by the example application.
Then a validation is done in order to check if the key size is
supported in the algorithm capabilities.
A new feature flag is added in crypto PMDs to allow wrapped keys,
hence, to allow wrapped keys, app should remove the validation of
key size in the application and rely on a PMD key size validation.
The validation is removed in case the key is provided by user and
the RTE_CRYPTODEV_FF_CIPHER_WRAPPED_KEY feature flag is set, and
kept in case the key should be generated by the application or
RTE_CRYPTODEV_FF_CIPHER_WRAPPED_KEY is not set.
The Key Wrap approach is used by applications in order to protect keys
located in untrusted storage or transmitted over untrusted
communications networks. The constructions are typically built from
standard primitives such as block ciphers and cryptographic hash
functions.
The Key Wrap method and its parameters are a secret between the keys
provider and the device, means that the device is preconfigured for
this method using very secured way.
The key wrap method may change the key length and layout.
Add a description for the cipher transformation key to allow wrapped key
to be forwarded by the same API.
Add a new feature flag RTE_CRYPTODEV_FF_CIPHER_WRAPPED_KEY to be enabled
by PMDs support wrapped key in cipher trasformation.
Fan Zhang [Wed, 31 Mar 2021 17:20:38 +0000 (18:20 +0100)]
cryptodev: add dequeue count parameter in raw API
This patch changes the experimental raw data path dequeue burst API.
Originally the API enforces the user to provide callback function
to get maximum dequeue count. This change gives the user one more
option to pass directly the expected dequeue count.
Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com> Acked-by: Akhil Goyal <gakhil@marvell.com>
Adding lookaside IPsec UDP encapsulation support
for NAT traversal.
Application has to add udp-encap option to sa config file
to enable UDP encapsulation on the SA.
In cryptography, a block cipher is a deterministic algorithm operating
on fixed-length groups of bits, called blocks.
A block cipher consists of two paired algorithms, one for encryption
and the other for decryption. Both algorithms accept two inputs:
an input block of size n bits and a key of size k bits; and both yield
an n-bit output block. The decryption algorithm is defined to be the
inverse function of the encryption.
For AES standard the block size is 16 bytes.
For AES in XTS mode, the data to be encrypted\decrypted does not have to
be multiple of 16B size, the unit of data is called data-unit.
The data-unit size can be any size in range [16B, 2^24B], so, in this
case, a data stream is divided into N amount of equal data-units and
must be encrypted\decrypted in the same data-unit resolution.
For ABI compatibility reason, the size is limited to 64K (16-bit field).
The new field dataunit_len is inserted in a struct padding hole,
which is only 2 bytes long in 32-bit build.
It could be moved and extended later during an ABI-breakage window.
The current cryptodev API doesn't allow the user to select a specific
data-unit length supported by the devices.
In addition, there is no definition how the IV is detected per data-unit
when single operation includes more than one data-unit.
That causes applications to use single operation per data-unit even though
all the data is continuous in memory what reduces datapath performance.
Add a new feature flag to support multiple data-unit sizes, called
RTE_CRYPTODEV_FF_CIPHER_MULTIPLE_DATA_UNITS.
Add a new field in cipher capability, called dataunit_set,
where the devices can report the range of the supported data-unit sizes.
Add a new cipher transformation field, called dataunit_len, where the user
can select the data-unit length for all the operations.
All the new fields do not change the size of their structures,
by filling some struct padding holes.
They are added as exceptions in the ABI check file libabigail.abignore.
Using a bitmap to report the supported data-unit sizes capability allows
the devices to report a range simply as same as the user to read it
simply. also, thus sizes are usually common and probably will be shared
among different devices.
examples/l2fwd-crypto: fix packet length while decryption
There were some padding left when a packet gets decrypted. This
patch removes those padding.
This patch also removes the padding left after verifying auth of
the packet.
Fixes: e2cdfbd07c8a ("examples/l2fwd-crypto: fix port id type") Cc: stable@dpdk.org Signed-off-by: Rohit Raj <rohit.raj@nxp.com> Acked-by: Akhil Goyal <gakhil@marvell.com>
examples/l2fwd-crypto: align private data size to cache size
L2fwd-crypto is passing 24b private data size while packet
pool creation. This patch aligns that private data size
to cache line size for better performance results.
Ciara Power [Mon, 1 Mar 2021 11:28:31 +0000 (11:28 +0000)]
doc: fix dpdk-graph-crypto-perf dependencies
The script dependencies list was incomplete,
this patch adds missing modules and removes an unnecessary entry.
The installation command was also added.
Fixes: f400e0b82bf1 ("app/crypto-perf: add script to graph perf results") Cc: stable@dpdk.org Signed-off-by: Ciara Power <ciara.power@intel.com> Acked-by: Akhil Goyal <gakhil@marvell.com>
Ankur Dwivedi [Mon, 1 Mar 2021 05:59:55 +0000 (11:29 +0530)]
crypto/octeontx: fix session-less mode
A temporary session is created for sessionless crypto operations.
rte_cryptodev_sym_session_create() should be used for creating the
temporary session as it initializes the session structure in the
correct way.
David Marchand [Thu, 15 Apr 2021 19:43:01 +0000 (21:43 +0200)]
ci: fix ABI reference generation
The machine=generic is not understood by older version of dpdk.
It is directly passed to gcc as -march=generic.
Since DPDK requires SSE 4.2, this results in an error when configuring
v21.02 sources for generating the reference ABI.
From GHA [1] logs:
"""
Compiler for C supports arguments -Wundef: YES
Compiler for C supports arguments -Wwrite-strings: YES
Compiler for C supports arguments -Wno-address-of-packed-member
-Waddress-of-packed-member: NO
Compiler for C supports arguments -Wno-packed-not-aligned
-Wpacked-not-aligned: NO
Compiler for C supports arguments -Wno-missing-field-initializers
-Wmissing-field-initializers: YES
config/x86/meson.build:14:6: ERROR: Could not get define '__SSE4_2__'
A full log can be found at
/home/runner/work/dpdk/dpdk-v21.02/build/meson-logs/meson-log.txt
Error: Process completed with exit code 1.
"""
Stick to a compatible configuration passing -Dmachine=default.
Note: the breakage was not seen earlier this week as I guess the CI
workers are using a cached ABI reference for v20.11.
Fixes: 5b3a6ca6fd28 ("build: alias default build as generic") Signed-off-by: David Marchand <david.marchand@redhat.com> Reviewed-by: Juraj Linkeš <juraj.linkes@pantheon.tech>
Previous fix has addressed the incorrect handling of `base_frequency`
file, but has added a use-after-free error due to the fact that all
further code paths will lead to an `fclose()` call at the end, so the
additional `fclose()` call right after processing the file was
unnecessary.
Coverity issue: 369901 Fixes: 8a5febaac4f7 ("power: fix P-state base frequency handling") Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com> Reviewed-by: Liang Ma <liangma@liangbit.com> Acked-by: David Hunt <david.hunt@intel.com>
Juraj Linkeš [Wed, 14 Apr 2021 13:41:36 +0000 (15:41 +0200)]
config/arm: fix implementer and its SoCs
Fix the implementer and part number of DPAA and ARMADA SoCs.
The current values of 16 cores and 1 NUMA node don't cover all SoCs from
the Arm implementer, e.g. Taishan 2280 has 64 cores and 4 NUMA nodes.
Increase these to 64 and 4 to widen the coverage.
Also increase the neoverse-n1 MAX_LCORE and MAX_NUMA_NODES to reflect
new available hardware (Amplere Altra).
Add configuration to SoC options where smaller values are needed.
Fixes: 6ec78c2463ac ("build: add meson support for dpaaX platforms") Fixes: dd1cd845c102 ("config: add Marvell ARMADA based on armv8-a") Fixes: d97108a33231 ("config: change defaults of armv8") Signed-off-by: Juraj Linkeš <juraj.linkes@pantheon.tech> Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com> Reviewed-by: Liron Himi <lironh@marvell.com> Acked-by: Pavan Nikhilesh <pbhagavatula@marvell.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Juraj Linkeš [Wed, 14 Apr 2021 13:41:35 +0000 (15:41 +0200)]
config/arm: add platform config option
Add Arm SoC configuration sets to Arm meson.build and add an arch
agnostic meson option, 'platform', to select from these SoC
configurations for meson native builds. This is preferable to
specifying a cross file when doing aarch64 -> aarch64 builds, since the
cross file specifies the toolchain as well.
Signed-off-by: Juraj Linkeš <juraj.linkes@pantheon.tech> Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com> Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com> Tested-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Juraj Linkeš [Wed, 14 Apr 2021 13:41:34 +0000 (15:41 +0200)]
config: enable/disable drivers in Arm builds
Add support for enabling or disabling drivers for Arm cross build. Do
not implement any enable/disable lists yet.
Enabling drivers is useful when building for an SoC where we only want
to build a few drivers. That way the list won't be too long.
Similarly, disabling drivers is useful when we want to disable only a
few drivers.
Both of these are advantageous mainly in aarch64 -> aarch64 (or arch ->
same arch) builds, where the build machine may have the required driver
dependencies, yet we don't want to build drivers for a specific SoC.
If enable_drivers is a non-empty list, build only those drivers,
otherwise build all drivers and add them to enable_drivers. If
disable_drivers is non-empty list, build all drivers specified in
enable_drivers except those in disable_drivers.
There are two drivers, bus/pci and bus/vdev, which break the build if
not enabled. Address this by always enabling these if the user disables
them or doesn't specify in their allowlist.
Also remove the old Makefile arm configuration options which don't do
anything in Meson.
Signed-off-by: Juraj Linkeš <juraj.linkes@pantheon.tech> Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com> Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com> Acked-by: Bruce Richardson <bruce.richardson@intel.com>
The PCI device address is being used for sending mailbox which was
introduced in previous commit which replaced the macros so that
multiple DPI blocks in the hardware can be supported.
This patch fixes a NULL pointer access by assigning the PCI device
structure to dpivf.
git.droids-corp.org / dpdk.git / log