eal/windows: add random function

The file rte_random.c is required to build i40e PMD on Windows.
Add rte_rand variable to export file.

Redefine _m_prefetchw for Clang toolchain due to following error
with respect to conflicting types:

FAILED: lib/76b5a35@@rte_eal@sta/librte_eal_common_rte_random.c.obj
clang @lib/76b5a35@@rte_eal@sta/librte_eal_common_rte_random.c.obj.rsp
In file included from ../lib/librte_eal/common/rte_random.c:13:
In file included from ..\lib/librte_eal/include\rte_eal.h:20:
In file included from ..\lib/librte_eal/include\rte_per_lcore.h:25:
In file included from ..\lib/librte_eal/windows/include\pthread.h:21:
In file included from ..\lib/librte_eal/windows/include\rte_windows.h:27:
In file included from C:\Program Files (x86)\Windows Kits\10\include\
10.0.18362.0\um\windows.h:171:
In file included from C:\Program Files (x86)\Windows Kits\10\include\
10.0.18362.0\shared\windef.h:24:
In file included from C:\Program Files (x86)\Windows Kits\10\include\
10.0.18362.0\shared\minwindef.h:182:
C:\Program Files (x86)\Windows Kits\10\include\10.0.18362.0\um\
winnt.h:3324:1: error: conflicting types for '_m_prefetchw'
_m_prefetchw (
^
C:\Program Files\LLVM\lib\clang\10.0.0\include\prfchwintrin.h:50:1:
note: previous definition is here
_m_prefetchw(void *__P)
^
1 error generated.

Signed-off-by: Pallavi Kadam <pallavi.kadam@intel.com>
Reviewed-by: Ranjit Menon <ranjit.menon@intel.com>

doc: add Windows support for mlx5

Windows is supported by mlx5 PMD.
The mlx5 guide is updated with the needed information.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>

common/mlx5: enable compilation on Windows

Enable mlx5 common driver on Windows with clang compilation.

Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

common/mlx5: fix pointer cast on Windows

While compiling with clang 11 the callers of the
__mlx5_bit_off macro warns on the cast of pointers to
unsigned long which is a smaller int type in Windows.

warning: cast to smaller integer type 'unsigned long'
from 'u8 (*)[16]' [-Wpointer-to-int-cast]

To resolve it the type is changed to uintptr_t to be
compatible for both Linux and Windows.

Fixes: 865a0c15672c ("net/mlx5: add Direct Verbs prepare function")
Cc: stable@dpdk.org
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

common/mlx5: remove doorbell allocation functions

The mlx5_devx_dbr_page structure was used to allocate and release the
umem of the doorbells.
Since doorbell and buffer have used same umem, this structure is
useless.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

net/mlx5: move Rx RQ creation to common

Using common function for Rx RQ creation.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

common/mlx5: share DevX RQ creation

The RQ object in DevX is used currently only in net driver, but it is
shared for future.

Add a structure that contains all the resources, and provide creation
and release functions for it.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

net/mlx5: move ASO SQ creation to common

Using common function for ASO SQ creation.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

net/mlx5: move Tx SQ creation to common

Using common function for Tx SQ creation.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

net/mlx5: move rearm and clock queue SQ creation to common

Using common function for DevX SQ creation for rearm and clock queue.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

regex/mlx5: move DevX SQ creation to common

Using common function for DevX SQ creation.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

common/mlx5: share DevX SQ creation

The SQ object in DevX is created in several places and in several
different drivers.
In all places almost all the details are the same, and in particular the
allocations of the required resources.

Add a structure that contains all the resources, and provide creation
and release functions for it.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

common/mlx5: enhance page size configuration

The PRM calculates page size in 4K, so need to reduce the log_wq_pg_sz
attribute.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

net/mlx5: move Rx CQ creation to common

Using common function for Rx CQ creation.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

net/mlx5: move Tx CQ creation to common

Using common function for Tx CQ creation.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

net/mlx5: move ASO CQ creation to common

Use common function for ASO CQ creation.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

net/mlx5: move rearm and clock queue CQ creation to common

Using common function for CQ creation at rearm queue and clock queue.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

vdpa/mlx5: move DevX CQ creation to common

Using common function for DevX CQ creation.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

regex/mlx5: move DevX CQ creation to common

Using common function for DevX CQ creation.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

common/mlx5: share DevX CQ creation

The CQ object in DevX is created in several places and in several
different drivers.
In all places almost all the details are the same, and in particular the
allocations of the required resources.

Add a structure that contains all the resources, and provide creation
and release functions for it.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

net/mlx5: fix leak on ASO SQ creation failure

In ASO SQ creation, the PMD allocates umem buffer for SQ.

When umem buffer allocation fails, the MR and CQ memory are not freed
what caused a memory leak.

Free it.

Fixes: f935ed4b645a ("net/mlx5: support flow hit action for aging")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

net/mlx5: remove CQE padding device argument

The data-path code doesn't take care on 'rxq_cqe_pad_en' and use padded
CQE for any case when the system cache-line size is 128B.

This makes the argument redundant.

Remove it.

Fixes: bc91e8db12cd ("net/mlx5: add 128B padding of Rx completion entry")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

common/mlx5: fix completion queue entry size configuration

According to the current data-path implementation in the PMD the CQE
size must follow the cache-line size.
So, the configuration of the CQE size should be depended in
RTE_CACHE_LINE_SIZE.

Wrongly, part of the CQE creations didn't follow it exactly what caused
an incompatibility between HW and SW in the data-path when working in
128B cache-line size systems.

Adjust the rule for any CQE creation.
Remove the cqe_size attribute from the DevX CQ creation command and set
it inside the command translation according to the cache-line size.

Fixes: 79a7e409a2f6 ("common/mlx5: prepare support of packet pacing")
Fixes: 5cd0a83f413e ("common/mlx5: support more fields in DevX CQ create")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

net/mlx5: fix hairpin flow split decision

Previously, the identification of hairpin queue was done using
mlx5_rxq_get_type() function.
Recent patch replaced it with use of mlx5_rxq_get_hairpin_conf(),
and check of the return value conf != NULL.
The case of return value is NULL (queue is not hairpin) was not handled.
As result, non-hairpin flows were wrongly handled.
This patch adds the required check for return value is NULL.

Fixes: 509f8470de55 ("net/mlx5: do not split hairpin flow in explicit mode")
Cc: stable@dpdk.org
Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

net/mlx5: split multi-thread flow handling per OS

multi-threaded flows feature uses pthread function pthread_key_create
but for Windows the destruction option in the function is unimplemented.

To resolve it, Windows will implement destruction mechanism to cleanup
mlx5_flow_workspace object for each terminated thread.

Linux flow will keep the current behavior.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Acked-by: Khoa To <khot@microsoft.com>

net/octeontx2: support 24B custom L2 header parsing

Adding support to parse 24B custom L2 header. Added devargs support to
configure the PKIND, and removed the restriction to support custom
headers on non SDP interface.

Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>

net/octeontx2: fix corruption in segments list

On Tx, lastseg->next is not being reset to null for multi segmented
packet and same mbuf can be used on Rx which has a stale mbuf entry into
mbuf->next.

On Rx, application receives mbuf with mbuf->next uninitialized though
mbuf->nb_segs is correct. Application iterates over all segments using
mbuf->next ignoring mbuf->nb_segs which leads to undefined behavior.

So earlier assumption of just having right value in mbuf->nb_segs is
enough, is incorrect. Mbuf must contain valid and synced value in
nb_segs and next pointer.

Fixes: 364eb0e46683 ("net/octeontx2: avoid per packet barrier with multi segment")
Cc: stable@dpdk.org
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>

net/mvneta: check allocation in Rx queue flush

The function rte_malloc() could return NULL, the return value
need to be checked.

Fixes: ce7ea764597e ("net/mvneta: support Rx/Tx")
Cc: stable@dpdk.org
Signed-off-by: Yunjian Wang <wangyunjian@huawei.com>
Acked-by: Liron Himi <lironh@marvell.com>

net/bnxt: check chip reset in stop and close

While the error recovery thread is running, an application
can invoke dev_stop or dev_close_op thus triggering a race
and unwanted consequences if dev_close is invoked while the
recovery is not yet completed.
Fix by having another lock to synchronize between the 2 threads and
return EGAIN if adapter is in the middle of recovery when dev_stop
or dev_close ops are invoked

Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>

net/bnxt: fix error handling in device start

Call bnxt_dev_stop in error path of bnxt_dev_start_op() to keep
it simple and consistent

Fixes: c09f57b49c13 ("net/bnxt: add start/stop/link update operations")
Cc: stable@dpdk.org
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>

net/bnxt: fix lock init and destroy

Invoking init/uninit locks in init_resources and uninit_resources
would end up initializing and destroying locks on every port start
stop which is not desired.
Move the 2 routines to dev_init and dev_close respectively as
locks need to be initialized and destroyed only once during the
lifetime of the driver.

Fixes: 1cb3d39a48f7 ("net/bnxt: synchronize between flow related functions")
Cc: stable@dpdk.org
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>

net/bnxt: add Rx logic for 58818 chips

1. On the new 58818 chips, the RX completion is largely the same except
   for the new completion opcode and the stripped VLAN format and
   checksum status. Added bnxt_parse_csum_v2(), bnxt_parse_pkt_type_v2()
   and bnxt_rx_vlan_v2() to support the new RX completion logic.
2. Disable vector mode RX/TX for 58818 chips for now.
3. The cfa_code format on 58818 chips is different than legacy chips.
   So skip cfa_code parsing logic on 58818 chips for now.

Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>

net/bnxt: modify context memory allocation

Newer devices like SR2 may have chip backing store and do not require
host backed memory allocation.

In these cases, HWRM_FUNC_BACKING_STORE_QCAPS will return a zero entry
size to indicate contexts for which the host should not allocate backing
store.

Selectively allocate context memory based on device capabilities and
only enable backing store for the appropriate contexts

Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>

net/bnxt: support LRO for SR2 chip

Add the new chip specific TPA v2 logic to bnxt_tpa_start() to fully
support TPA on the new chip.

Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>

net/bnxt: modify VNIC accounting

Modify VNIC accounting when enabling RFS on newer chips.
Unlike legacy chips, newer chips don't need additional VNIC resources
for ntuple filter. Fix the code accordingly so that we don't reserve
and allocate additional VNICs on newer chips.

Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>

net/bnxt: add new Rx checksum mode

The 58818 chips support two different checksum modes.
Host driver has to register with FW which checksum mode it
prefers to use. DPDK driver want to use "cs_all_ok_mode=1".
FW advertises the support of the different checksum modes
on per VNIC basis in the HWRM_VNIC_QCAPS response.
Driver should use HWRM_VNIC_CFG to configure the needed
checksum mode.

Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>

net/bnxt: support 58818 chip family

The new chip (Stingray 2) is part of the P5 chip family with a number
of changes:

1. Implement the epoch doorbell bit for 58818 chip. With the new
   doorbell infrastructure and the unbounded index logic, now set the
   epoch doorbell bit to support proper doorbell operation on the new
   chip.  Toggle epoch bit of all rings when it's wrapped to support
   doorbell overflow checking.
2. Get the legacy doorbell size from firmware. Legacy doorbell support
   has been removed in Stingray 2. So, the fast path doorbell pages
   start from the base of the BAR. Drivers need to use
   legacy_l2_db_space_size_kb field in the hwrm_func_qcfg_output
   response to get the legacy doorbell page offset from the BAR.
3. Set VALID doorbell bit on 58818 chip family. This class of chip has a
   valid doorbell bit added and it needs to be set.
4. Use "chip_num" returned by firmware. The "chip_num" field in the
   HWRM_VER_GET output returns the chip number. Use this value to
   identify chip category for 58818 chip family.
5. Added device ids for Stingray2 PF/VF devices.

Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>

net/ice: refactor packet type parsing

If the capability of a PTYPE within a specific package could be
negotiated, no need to maintain a different PTYPE list for each
type of the package when parsing PTYPE. So refactor the PTYPE
parsing mechanism for each flow engines.

Signed-off-by: Jeff Guo <jia.guo@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>

net/ice/base: add more packet type values

Add some macros for some PType value.

Signed-off-by: Jeff Guo <jia.guo@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>

net/i40e: add null input checks

Pointer 'NULL' check for 'mac_addr' or 'conf' within i40e PMD APIs.

Fixes: 66c78f4799ff ("net/i40e: add support for packet template to flow director")
Fixes: 04b443fb2c43 ("net/i40e: fix port id type")
Cc: stable@dpdk.org
Signed-off-by: Murphy Yang <murphyx.yang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>

net/iavf: support new VLAN capabilities

The new VLAN virtchnl opcodes introduce new capabilities like VLAN
filtering, stripping and insertion.

The AVF needs to query the VLAN capabilities based on current device
configuration firstly.

AVF is able to configure inner VLAN filter when port VLAN is enabled
base on negotiation; and AVF is able to configure outer VLAN (0x8100)
if port VLAN is disabled to be compatible with legacy mode.

When port VLAN is updated by DCF, the AVF needs to reset to query the
new VLAN capabilities.

Signed-off-by: Qiming Yang <qiming.yang@intel.com>
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>

net/ice: add DCF VLAN handling

Add the DCF port representor infrastructure for the VFs of DCF attached
PF. Then the standard ethdev API like VLAN can be used to configure the
VFs.

Signed-off-by: Qiming Yang <qiming.yang@intel.com>
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>

net/iavf: support CRC strip disabling

The VF will check the PF's CRC strip capability firstly, then set the
'CRC strip disable' value in the queue configuration according to the
RX CRC offload setting.

Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>

common/iavf: update copyright date

Updated the Copyright for 2021.
Updated FreeBSD IAVF driver of version.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>

common/iavf: support VLAN offload by DCF

Add new opcode VIRTCHNL_OP_DCF_VLAN_OFFLOAD to set VLAN offload
by DCF, the virtchnl message includes:
1. A valid target VF
2. Type of VLAN to be supported: outer or inner
3. Ethertype of the VLAN (either 0x8100 or 0x88A8 or 0x9100)
4. VLAN insert settings
   a). No insert offload, VLAN ID in the packet (default)
   b). Offload via transmit descriptor
   c). Insert as a port VLAN (via VSI)
5. VLAN strip settings
   a). Strip (and discard)
   b). Strip and place in descriptor
   c). No Strip
6. VLAN ID for the target VF

Signed-off-by: Qiming Yang <qiming.yang@intel.com>
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>

common/iavf: support new VLAN capabilities

Currently VIRTCHNL only allows for VLAN filtering and offloads to happen
on a single 802.1Q VLAN. Add support to filter and offload on inner,
outer, and/or inner + outer VLANs.

This is done by introducing the new capability
VIRTCHNL_VF_OFFLOAD_VLAN_V2. The flow to negotiate this new capability
is shown below.

1. VF - sets the VIRTCHNL_VF_OFFLOAD_VLAN_V2 bit in the
   virtchnl_vf_resource.vf_caps_flags during the
   VIRTCHNL_OP_GET_VF_RESOURCES request message. The VF should also set
   the VIRTCHNL_VF_OFFLOAD_VLAN bit in case the PF driver doesn't
   support the new capability.

2. PF - sets the VLAN capability bit it supports in the
   VIRTCHNL_OP_GET_VF_RESOURCES response message. This will either be
   VIRTCHNL_VF_OFFLOAD_VLAN_V2, VIRTCHNL_VF_OFFLOAD_VLAN, or none.

3. VF - If the VIRTCHNL_VF_OFFLOAD_VLAN_V2 capability was ACK'd by the
   PF, then the VF needs to request the VLAN capabilities of the
   PF/Device by issuing a VIRTCHNL_OP_GET_OFFLOAD_VLAN_V2_CAPS request.
   If the VIRTCHNL_VF_OFFLOAD_VLAN capability was ACK'd then the VF
   knows only single 802.1Q VLAN filtering/offloads are supported. If no
   VLAN capability is ACK'd then the PF/Device doesn't support hardware
   VLAN filtering/offloads for this VF.

4. PF - Populates the virtchnl_vlan_caps structure based on what it
   allows/supports for that VF and sends that response via
   VIRTCHNL_OP_GET_OFFLOAD_VLAN_V2_CAPS.

After VIRTCHNL_OP_GET_OFFLOAD_VLAN_V2_CAPS is successfully negotiated
the VF driver needs to interpret the capabilities supported by the
underlying PF/Device. The VF will be allowed to filter/offload the
inner 802.1Q, outer (various ethertype), inner 802.1Q + outer
(various ethertypes), or none based on which fields are set.

The VF will also need to interpret where the VLAN tag should be inserted
and/or stripped based on the negotiated capabilities.

Also, update the virtchnl_op_str() function to support the added opcodes.

Signed-off-by: Brett Creeley <brett.creeley@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>

net/ice: enlarge Rx queue rearm threshold to 64

We observe performance drop on ice AVX512 data path after stop and
start by using testpmd.

As CPU polling is faster in AVX512 path, L3 contested accesses is
intensified when rxrearm_start is a random value after testpmd
stop/start.

Enlarge ICE_RXQ_REARM_THRESH to 64 to ease the contested accesses and
fix the performance drop issue.

Cc: stable@dpdk.org
Signed-off-by: Leyi Rong <leyi.rong@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>

net/ice: disable IPv4 checksum offload in vector Tx

ICE choices vector TX path or basic TX path by macro
'ICE_NO_VECTOR_FLAGS'.

This patch adds 'DEV_TX_OFFLOAD_IPV4_CKSUM' in 'ICE_NO_VECTOR_FLAGS'
to make IPv4 checksum offload processed by basic TX path.

Fixes: a22483208800 ("net/ice: disable TSO offload in vector path")
Cc: stable@dpdk.org
Signed-off-by: Murphy Yang <murphyx.yang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>

net/ice: fix RSS lookup table initialization

RSS look-up table initialization is done incorrectly due to
divide-by-zero error.
Add a check to rx-queue count.

Fixes: 50370662b727 ("net/ice: support device and queue ops")
Cc: stable@dpdk.org
Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com>
Tested-by: Wei Xie <weix.xie@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>

net/iavf: fix conflicting RSS combination rules

Currently, when use 'flow' command to create a rule with following
invalid RSS type combination, it can be created successfully.

Invalid RSS combinations list:
 - ETH_RSS_IPV4 | ETH_RSS_NONFRAG_IPV4_TCP
 - ETH_RSS_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP

This patch adds these combinations in 'invalid_rss_comb' array to do
valid check, if the combination check failed, the rule will be created
unsuccessful.

Fixes: 91f27b2e39ab ("net/iavf: refactor RSS")
Cc: stable@dpdk.org
Signed-off-by: Murphy Yang <murphyx.yang@intel.com>
Acked-by: Jeff Guo <jia.guo@intel.com>

net/txgbe: add security type in flow action

Add security type in flow action.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: add security offload in Rx and Tx

Add security offload in Rx and Tx process.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: destroy security session

Add support to clear a security session's private data,
get the size of a security session,
add update the mbuf with provided metadata.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: add security session create operation

Add support to configure a security session.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: add IPsec context creation

Initialize securiry context, and add support to get
security capabilities.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: add TM hierarchy commit

Add traffic manager hierarchy commit.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: support TM node add and delete

Support traffic manager node add and delete operations.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: support TM shaper profile add and delete

Support traffic manager profile add and delete operations.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: add TM capabilities get operation

Add support to get traffic manager capabilities.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: add TM configuration init and uninit

Add traffic manager configuration init and uninit operations.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: support UDP tunnel port add and delete

Support UDP tunnel port add and delete operations.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: flush all filters

Add support to flush all the filters.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: support destroying consistent filter

Add a function to destroy the flow filter.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: support creating consistent filter

Create a flow rule, to use the matched filter which the rule hit first.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: parse RSS filter

Check if the rule is a RSS filter rule, and get the RSS info.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: restore RSS filter

Add support to restore RSS filter.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: parse flow director filter

Check if the rule is a flow director rule, and get the flow director info.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: support flow director filter add and delete

Support add and delete operations on flow director filter.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: configure flow director filter

Configure flow director filter with it enabled.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: add flow director filter init and uninit

Add flow director filter init and uninit operations.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: parse L2 tunnel filter

Check if the rule is a L2 tunnel rule, and get the L2 tunnel info.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: support L2 tunnel filter add and delete

Support L2 tunnel filter add and delete operations.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: config L2 tunnel filter with e-tag

Config L2 tunnel filter with e-tag.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: add L2 tunnel filter init and uninit

Add L2 tunnel filter init and uninit.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: parse syn filter

Check if the rule is a TCP SYN rule, and get the SYN info.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: support syn filter add and delete

Support add and delete operations on syn filter.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: parse ethertype filter

Check if the rule is a ethertype rule, and get the ethertype info.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: support ethertype filter add and delete

Support add and delete operations on ethertype filter.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: parse n-tuple filter

Check if the rule is a n-tuple rule, and get the n-tuple info.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: support ntuple filter add and delete

Support add and delete operations on ntuple filter.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: add ntuple filter init and uninit

Add ntuple filter init and uninit.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/txgbe: add generic flow API

Introduce rte_flow with its validate, create, destroy and flush
operations into txgbe PMD.

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>

net/ionic: stop queues when LIF is stopped

Otherwise they cannot be restarted, because the FW will reject INIT
or ENA commands on queues which are already running.

Signed-off-by: Andrew Boyer <aboyer@pensando.io>

net/ionic: improve queue state handling

Skip ionic_lif_[rxq|txq]_init() in queue start if it's already done.
Move ionic_lif_[rxq|txq]_deinit() from queue stop to queue release.

This allows the queues to be restarted.

Signed-off-by: Andrew Boyer <aboyer@pensando.io>

net/ionic: improve link state handling

Add UP and FW_RESET state flags.
Update the stack info when the link state changes.
Convert set_link_up/set_link_down to lif_start/lif_stop.
Condition reported link state on UP flag.

Signed-off-by: Andrew Boyer <aboyer@pensando.io>

net/ionic: complete release on close

ionic_dev_close() is responsible for destroying the ethdev, lif, and
adapter. eth_ionic_dev_remove() calls ionic_dev_close().

Remove-on-close is now required behavior for a PMD.
Remove the UNMAINTAINED flag.

Signed-off-by: Andrew Boyer <aboyer@pensando.io>

net/ionic: remove multi-LIF support

This feature is unused, so remove it.

There is exactly one adapter / lif / ethdev per port.

Signed-off-by: Andrew Boyer <aboyer@pensando.io>

net/ionic: preserve Rx mode across LIF stop/start

Otherwise, non-default settings (like PROMISC) get reset.
This will become important when link toggling is tied to LIF stop/start.

Signed-off-by: Andrew Boyer <aboyer@pensando.io>

net/ionic: preserve RSS state unless RETA size changes

This preserves settings across a LIF stop/start.
This will become important when link toggling is tied to LIF stop/start.

Signed-off-by: Andrew Boyer <aboyer@pensando.io>

vhost: enhance async enqueue for small packets

Async enqueue offloads large copies to DMA devices, and small copies
are still performed by the CPU. However, it requires users to get
enqueue completed packets by rte_vhost_poll_enqueue_completed(), even
if they are completed by the CPU when rte_vhost_submit_enqueue_burst()
returns. This design incurs extra overheads of tracking completed
pktmbufs and function calls, thus degrading performance on small packets.

This patch enhances async enqueue for small packets by enabling
rte_vhost_submit_enqueue_burst() to return completed packets.

Signed-off-by: Jiayu Hu <jiayu.hu@intel.com>
Tested-by: Yinan Wang <yinan.wang@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>

vhost: cleanup async enqueue

This patch removes unnecessary check and function calls, and it changes
appropriate types for internal variables and fixes typos.

Signed-off-by: Jiayu Hu <jiayu.hu@intel.com>
Tested-by: Yinan Wang <yinan.wang@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>

net/virtio: fix memory init with vDPA backend

This patch fixes an overhead met with mlx5-vdpa Kernel
driver, where for every page in the mapped area, all the
memory tables gets updated. For example, with 2MB hugepages,
a single IOTLB_UPDATE for a 1GB region causes 512 memory
updates on mlx5-vdpa side.

Using batching mode, the mlx5 driver will only trigger a
single memory update for all the IOTLB updates that happen
between the batch begin and batch end commands.

Fixes: 6b901437056e ("net/virtio: introduce vhost-vDPA backend")
Cc: stable@dpdk.org
Signed-off-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Reviewed-by: Chenbo Xia <chenbo.xia@intel.com>

net/virtio: add missing backend features negotiation

This patch adds missing backend features negotiation for
in Vhost-vDPA. Without it, IOTLB messages v2 could be sent
by Virtio-user PMD while not supported by the backend.

Fixes: 6b901437056e ("net/virtio: introduce vhost-vDPA backend")
Cc: stable@dpdk.org
Signed-off-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Reviewed-by: Chenbo Xia <chenbo.xia@intel.com>

net/cxgbe: accept VLAN flow items without ethertype

When apps pass the RTE_FLOW_ITEM_TYPE_VLAN without setting the
ethertype field in RTE_FLOW_ITEM_TYPE_ETH, then assume 0x8100
VLAN by default and don't reject the rule.

Fixes: 55f003d8884c ("net/cxgbe: support flow API for matching QinQ VLAN")
Cc: stable@dpdk.org
Signed-off-by: Karra Satwik <kaara.satwik@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>

net/enic: remove deprecated flow director code

The Flow Director (FDIR) API was removed in release 20.11.
This patch removes the remainder of the FDIR code in the
PMD.

Signed-off-by: John Daley <johndale@cisco.com>
Reviewed-by: Hyong Youb Kim <hyonkim@cisco.com>

net/axgbe: support reading FW version

Added support for fw_version_get API

Signed-off-by: Selwin Sebastian <selwin.sebastian@amd.com>
Acked-by: Somalapuram Amaranath <asomalap@amd.com>

net/ice: refactor PF RSS

This patch refactors the PF RSS code based on the below design:
1. ice_pattern_match_item->input_set_mask is the superset of
   ETH_RSS_xxx.
2. ice_pattern_match_item->meta is the ice_rss_hash_cfg template.
3. ice_hash_parse_pattern will generate pattern hint.
4. ice_hash_parse_action will refine the ice_rss_hash_cfg based on
   the pattern hint and rss_type.
5. The refine process includes:
   1)  refine protocol headers(VLAN/PPPOE/GTPU).
   2)  refine hash bit fields of l2, l3, l4.
   3)  refine hash bit fields for gtpu header.

Signed-off-by: Xuan Ding <xuan.ding@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>

config/arm: add Neoverse N2

Add Arm Neoverse N2 cpu support.

Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>

common/octeontx2: fix build with SVE

Building with gcc 10.2 with SVE extension enabled got error:

{standard input}: Assembler messages:
{standard input}:4002: Error: selected processor does not support `mov z3.b,#0'
{standard input}:4003: Error: selected processor does not support `whilelo p1.b,xzr,x7'
{standard input}:4005: Error: selected processor does not support `ld1b z0.b,p1/z,[x8]'
{standard input}:4006: Error: selected processor does not support `whilelo p4.s,wzr,w7'

This is because inline assembly code explicitly resets cpu model to
not have SVE support. Thus SVE instructions generated by compiler
auto vectorization got rejected by assembler.

Added SVE to the cpu model specified by inline assembly for SVE support.
Not replacing the inline assembly with C atomics because the driver relies
on specific LSE instruction to interface to co-processor [1].

Fixes: 8a4f835971f5 ("common/octeontx2: add IO handling APIs")
Cc: stable@dpdk.org
[1] https://mails.dpdk.org/archives/dev/2021-January/196092.html

Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>

net/octeontx: fix build with SVE

Building with gcc 10.2 with SVE extension enabled got error:

{standard input}: Assembler messages:
{standard input}:91: Error: selected processor does not support `addvl x4,x8,#-1'
{standard input}:95: Error: selected processor does not support `ptrue p1.d,all'
{standard input}:135: Error: selected processor does not support `whilelo p2.d,xzr,x5'
{standard input}:137: Error: selected processor does not support `decb x1'

This is because inline assembly code explicitly resets cpu model to
not have SVE support. Thus SVE instructions generated by compiler
auto vectorization got rejected by assembler.

Added SVE to the cpu model specified by inline assembly for SVE support.
Not replacing the inline assembly with C atomics because the driver relies
on specific LSE instruction to interface to co-processor [1].

Fixes: f0c7bb1bf778 ("net/octeontx/base: add octeontx IO operations")
Cc: stable@dpdk.org
[1] https://mails.dpdk.org/archives/dev/2021-January/196092.html

Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>