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(parent: d772d44) | patch
net/mlx5: fix inline logic
authorNélio Laranjeiro <nelio.laranjeiro@6wind.com>
Wed, 14 Sep 2016 11:53:55 +0000 (13:53 +0200)
committerBruce Richardson <bruce.richardson@intel.com>
Fri, 30 Sep 2016 10:27:18 +0000 (12:27 +0200)
commit0e8679fcddc45902cd8aa1d0fbfa542fee11b074
treedfc137d1de89856a62a72c403f71d1d2658f08bdtree | snapshot
parentd772d4408d3f71d89ab2c50bf02c553c9e11d4dbcommit | diff
net/mlx5: fix inline logic

To improve performance the NIC expects for large packets to have a pointer
to a cache aligned address, old inline code could break this assumption
which hurts performance.

Fixes: 2a66cf378954 ("net/mlx5: support inline send")

Signed-off-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
Signed-off-by: Vasily Philipov <vasilyf@mellanox.com>
drivers/net/mlx5/mlx5_ethdev.c diff | blob | history
drivers/net/mlx5/mlx5_rxtx.c diff | blob | history
drivers/net/mlx5/mlx5_rxtx.h diff | blob | history
drivers/net/mlx5/mlx5_txq.c diff | blob | history
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