i40e: disable setting of PHY configuration

i40e: disable setting of PHY configuration

There was a known link issue on 40G ports on NVM version (FVL3E),
when setting phy configuration. As a workaround, setting of phy
configuration should be disabled. The impact is that the link cannot
be forcedly configured, which doesn't affect any feature functions.
The workaround can be removed when a formal fix is ready later.

Test report: http://www.dpdk.org/ml/archives/dev/2015-May/017384.html

Signed-off-by: Helin Zhang <helin.zhang@intel.com>
Acked-by: Jingjing Wu <jingjing.wu@intel.com>
Acked-by: Jijiang Liu <jijiang.liu@intel.com>
Tested-by: Min Cao <min.cao@intel.com>