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(parent: 658cf5b) | patch
eal/ppc: fix memory barrier for IBM POWER
authorChao Zhu <chaozhu@linux.vnet.ibm.com>
Fri, 15 Jul 2016 02:30:19 +0000 (10:30 +0800)
committerThomas Monjalon <thomas.monjalon@6wind.com>
Thu, 21 Jul 2016 14:25:31 +0000 (16:25 +0200)
commitd23a6bd04d728226c99d6995c8bd65d49d7e61d1
tree7d516b97a3868ec73cd53e7797786a3e798bc7f8tree | snapshot
parent658cf5bc54fa44b13714d0fc6840985db2d7f331commit | diff
eal/ppc: fix memory barrier for IBM POWER

On weak memory order architecture like POWER, rte_smp_wmb/rte_smp_rmb
need to use CPU instructions, not compiler barrier. This patch fixes
this. Also, to improve performance on PPC64, use light weight sync
instruction instead of sync instruction.

Signed-off-by: Chao Zhu <chaozhu@linux.vnet.ibm.com>
lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h diff | blob | history
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