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(parent: 10c6d94) | patch
net/cxgbe: update Rx path for Chelsio T6
authorRahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Sat, 27 May 2017 03:46:25 +0000 (09:16 +0530)
committerFerruh Yigit <ferruh.yigit@intel.com>
Mon, 12 Jun 2017 09:41:27 +0000 (10:41 +0100)
commitedd04c619685bdb47af787ffd48565111f3a4ab9
tree020c8545b8e51ba355f3501a0244aa1560053f39tree | snapshot
parent10c6d94761e55ae192f5f270ac7fab25c9d6591ccommit | diff
net/cxgbe: update Rx path for Chelsio T6

Update RX path to reflect Chelsio T6 register value changes.
Update ingress pack boundary value based on maximum payload size
that can be accommodated by underlying PCI.  Update ingress pad
boundary value based on smallest memory controller bus width
possible.  Enforce alignment for free list pointer start address.

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
drivers/net/cxgbe/base/adapter.h diff | blob | history
drivers/net/cxgbe/base/common.h diff | blob | history
drivers/net/cxgbe/base/t4_hw.c diff | blob | history
drivers/net/cxgbe/base/t4_regs_values.h diff | blob | history
drivers/net/cxgbe/sge.c diff | blob | history
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