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common/iavf: support new VLAN capabilities
2021-01-13 Qi Zhangcommon/iavf: support new VLAN capabilities
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: update copyright date
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: update add scheduler node counter
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: cleanup style
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: support GTPU inner for AVF flow director
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: limit forced overrides based on FW version
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: fix memory handling
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: add package ptype enable information
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: remove deprecated field
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: align add VSI and update VSI AQ command...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: refactor structure field
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: remove unused struct member
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: support eCPRI over UDP type 0 flow
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: support eCPRI over MAC type 0 flow
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: align macro names to specification
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: use report default config to get PHY...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: fix null pointer dereference
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: modify recursive way of adding nodes
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: change get PHY capability log level
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: resend some AQ commands when EBUSY
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: support checking double VLAN mode
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: fix tunnel destroy
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: support VXLAN VNI field in flow director
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: add interface to support configuring...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: add condition to copy module info into...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: add function for NVM checksum verification
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: add definitions for FW health status...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: cleanup some macros
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: add GTP filtering via advanced switch...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: implement inactive NVM version get
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: read option ROM combo version from CIVD
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: allow flash read with arbitrary size
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: allow reading inactive flash security...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: refactor interface for flash read
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: read more security revision options
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: increase control queue timeout
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangnet/ice/base: modify ptype map for UDP
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2021-01-08 Qi Zhangdoc: fix some statements for ice vector PMD
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-26 Qi Zhangdoc: update ice user guide
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: update version
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: specify global RSS LUT id in get/set...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: refactor RSS configure API
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: use macro to get variable size array...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: remove duplicated AQ command flag setting
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: support extended GPIO access
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: fix parameter name in comment
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: recognize 860 as iSCSI port in CEE mode
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: implement shared rate limiter
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: return error directly
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: support class 5+ modules
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: use malloc instead of calloc
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: use package info from ice segment metadata
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: add more capability to admin queue
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: allocate and free RSS global lookup table
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: read security revision
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: move sched function prototypes
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: rename ptype bitmap
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: modify ptype bitmap for outer MAC
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: add NVM write response flags
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-11-03 Qi Zhangnet/ice/base: support tunnel for flow director
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-10-16 Qi Zhangcommon/iavf: support VF with more than 16 queues
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-10-16 Qi Zhangcommon/iavf: replace macro for MAC address length
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-21 Qi Zhangnet/iavf: fix iterator for RSS LUT
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice: support new devices
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/iavf: reject floating RSS attribute
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: preserve default aggregator VSI information
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: rename ACL priority values
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: remove unnecessary conditional
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: rename function
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: cache NVM module bank information
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: cleanup code
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: remove unused parameter
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: separate NVM version struct
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: enable QinQ filter for switch advanced...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: adjust rate limit profile ids runtime...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: change misc ACL style
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: preserve NVM capabilities in safe mode
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: remove function ACL count query
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: remove repeated words
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: check failed acts allocation
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: move a function
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: clear advanced rules in reset preparation
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: move a function
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: filter for GTPU outer IP without inner IP
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: support outer IP filter for GTPC
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: refactor DCB related variables
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: reduce profile to recip info get from...
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: introduce Tx rate limiting on port level
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: join format strings to same line
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: support GTP-U type switch rule
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: add AQ LLDP filter control command
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: fix abbreviations
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: introduce and use for each bit iterator
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: add function header
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: introduce and use bitmap hamming weight API
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: introduce and use bitmap set API
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: replace single-element array hack
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: silence static analysis warning
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: cleanup misleading comment
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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2020-09-18 Qi Zhangnet/ice/base: clean code wrapping
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
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