mbuf: add rte prefix to offload flags

[dpdk.git] / drivers / net / mlx5 / mlx5_rxtx_vec_neon.h

diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h
index 5ff792f..aa36df2 100644 (file)
--- a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h
+++ b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h
@@ -220,12 +220,12 @@ rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
                                const uint32x4_t ft_mask =
                                        vdupq_n_u32(MLX5_FLOW_MARK_DEFAULT);
                                const uint32x4_t fdir_flags =
-                                       vdupq_n_u32(PKT_RX_FDIR);
+                                       vdupq_n_u32(RTE_MBUF_F_RX_FDIR);
                                const uint32x4_t fdir_all_flags =
-                                       vdupq_n_u32(PKT_RX_FDIR |
-                                                   PKT_RX_FDIR_ID);
+                                       vdupq_n_u32(RTE_MBUF_F_RX_FDIR |
+                                                   RTE_MBUF_F_RX_FDIR_ID);
                                uint32x4_t fdir_id_flags =
-                                       vdupq_n_u32(PKT_RX_FDIR_ID);
+                                       vdupq_n_u32(RTE_MBUF_F_RX_FDIR_ID);
                                uint32x4_t invalid_mask, ftag;
 
                                __asm__ volatile
@@ -240,7 +240,7 @@ rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
                                invalid_mask = vceqzq_u32(ftag);
                                ol_flags_mask = vorrq_u32(ol_flags_mask,
                                                          fdir_all_flags);
-                               /* Set PKT_RX_FDIR if flow tag is non-zero. */
+                               /* Set RTE_MBUF_F_RX_FDIR if flow tag is non-zero. */
                                ol_flags = vorrq_u32(ol_flags,
                                        vbicq_u32(fdir_flags, invalid_mask));
                                /* Mask out invalid entries. */
@@ -276,8 +276,8 @@ rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
                                const uint8_t pkt_hdr3 =
                                        mcq[pos % 8 + 3].hdr_type;
                                const uint32x4_t vlan_mask =
-                                       vdupq_n_u32(PKT_RX_VLAN |
-                                                   PKT_RX_VLAN_STRIPPED);
+                                       vdupq_n_u32(RTE_MBUF_F_RX_VLAN |
+                                                   RTE_MBUF_F_RX_VLAN_STRIPPED);
                                const uint32x4_t cv_mask =
                                        vdupq_n_u32(MLX5_CQE_VLAN_STRIPPED);
                                const uint32x4_t pkt_cv = {
@@ -317,7 +317,7 @@ rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,
                                }
                        }
                        const uint32x4_t hash_flags =
-                               vdupq_n_u32(PKT_RX_RSS_HASH);
+                               vdupq_n_u32(RTE_MBUF_F_RX_RSS_HASH);
                        const uint32x4_t rearm_flags =
                                vdupq_n_u32((uint32_t)t_pkt->ol_flags);
 
@@ -396,22 +396,22 @@ rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq,
        uint16x4_t ptype;
        uint32x4_t pinfo, cv_flags;
        uint32x4_t ol_flags =
-               vdupq_n_u32(rxq->rss_hash * PKT_RX_RSS_HASH |
+               vdupq_n_u32(rxq->rss_hash * RTE_MBUF_F_RX_RSS_HASH |
                            rxq->hw_timestamp * rxq->timestamp_rx_flag);
        const uint32x4_t ptype_ol_mask = { 0x106, 0x106, 0x106, 0x106 };
        const uint8x16_t cv_flag_sel = {
                0,
-               (uint8_t)(PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED),
-               (uint8_t)(PKT_RX_IP_CKSUM_GOOD >> 1),
+               (uint8_t)(RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED),
+               (uint8_t)(RTE_MBUF_F_RX_IP_CKSUM_GOOD >> 1),
                0,
-               (uint8_t)(PKT_RX_L4_CKSUM_GOOD >> 1),
+               (uint8_t)(RTE_MBUF_F_RX_L4_CKSUM_GOOD >> 1),
                0,
-               (uint8_t)((PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1),
+               (uint8_t)((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1),
                0, 0, 0, 0, 0, 0, 0, 0, 0
        };
        const uint32x4_t cv_mask =
-               vdupq_n_u32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD |
-                           PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED);
+               vdupq_n_u32(RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD |
+                           RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED);
        const uint64x2_t mbuf_init = vld1q_u64
                                ((const uint64_t *)&rxq->mbuf_initializer);
        uint64x2_t rearm0, rearm1, rearm2, rearm3;
@@ -419,11 +419,11 @@ rxq_cq_to_ptype_oflags_v(struct mlx5_rxq_data *rxq,
 
        if (rxq->mark) {
                const uint32x4_t ft_def = vdupq_n_u32(MLX5_FLOW_MARK_DEFAULT);
-               const uint32x4_t fdir_flags = vdupq_n_u32(PKT_RX_FDIR);
-               uint32x4_t fdir_id_flags = vdupq_n_u32(PKT_RX_FDIR_ID);
+               const uint32x4_t fdir_flags = vdupq_n_u32(RTE_MBUF_F_RX_FDIR);
+               uint32x4_t fdir_id_flags = vdupq_n_u32(RTE_MBUF_F_RX_FDIR_ID);
                uint32x4_t invalid_mask;
 
-               /* Check if flow tag is non-zero then set PKT_RX_FDIR. */
+               /* Check if flow tag is non-zero then set RTE_MBUF_F_RX_FDIR. */
                invalid_mask = vceqzq_u32(flow_tag);
                ol_flags = vorrq_u32(ol_flags,
                                     vbicq_u32(fdir_flags, invalid_mask));