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(parent: 90a02fc) | patch
net/ixgbe/base: add bit for enabling L3/L4 filtering
authorWenzhuo Lu <wenzhuo.lu@intel.com>
Wed, 1 Mar 2017 06:04:47 +0000 (14:04 +0800)
committerFerruh Yigit <ferruh.yigit@intel.com>
Tue, 4 Apr 2017 13:52:51 +0000 (15:52 +0200)
commit04e395f20a45ab5e81b6945bc92ab981da06ccfa
tree0c67a6dd1d228d3475f61cefc90ab7096efc320dtree | snapshot
parent90a02fce708b74dfdc022dc9328efb128f33e62ecommit | diff
net/ixgbe/base: add bit for enabling L3/L4 filtering

Add a L3/L4 filtering definition of Multiple Receive Queues Command
(MRQC) register for the future use.

Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
drivers/net/ixgbe/base/ixgbe_type.h diff | blob | history
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