+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-
-
-
-/* available timers */
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW_TOTAL_NUM 0
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* VCOTUNE */
-#define VCOTUNE0_REG VCOTUNE
-#define VCOTUNE1_REG VCOTUNE
-#define VCOTUNE2_REG VCOTUNE
-#define VCOTUNE3_REG VCOTUNE
-#define VCOTUNE4_REG VCOTUNE
-#define VCOVDET0_REG VCOTUNE
-#define VCOVDET1_REG VCOTUNE
-
-/* BL_CONFIG */
-#define BL0_REG BL_CONFIG
-#define BL1_REG BL_CONFIG
-#define BL2_REG BL_CONFIG
-#define BL3_REG BL_CONFIG
-#define BL4_REG BL_CONFIG
-#define BL5_REG BL_CONFIG
-#define BLV_REG BL_CONFIG
-#define BL_REG BL_CONFIG
-
-/* DEEDR */
-#define ED0_REG DEEDR
-#define ED1_REG DEEDR
-#define ED2_REG DEEDR
-#define ED3_REG DEEDR
-#define ED4_REG DEEDR
-#define ED5_REG DEEDR
-#define ED6_REG DEEDR
-#define ED7_REG DEEDR
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDTOE_REG WDTCR
-
-/* DEEAR */
-#define BA0_REG DEEAR
-#define BA1_REG DEEAR
-#define BA2_REG DEEAR
-#define PA3_REG DEEAR
-#define PA4_REG DEEAR
-#define PA5_REG DEEAR
-#define PA6_REG DEEAR
-
-/* AVR_CONFIG */
-#define BBM_REG AVR_CONFIG
-#define SLEEP_REG AVR_CONFIG
-#define BLI_REG AVR_CONFIG
-#define BD_REG AVR_CONFIG
-#define TM_REG AVR_CONFIG
-#define ACS0_REG AVR_CONFIG
-#define ACS1_REG AVR_CONFIG
-
-/* B_DET */
-#define BD0_REG B_DET
-#define BD1_REG B_DET
-#define BD2_REG B_DET
-#define BD3_REG B_DET
-#define BD4_REG B_DET
-#define BD5_REG B_DET
-
-/* LOCKDET2 */
-#define LC0_REG LOCKDET2
-#define LC1_REG LOCKDET2
-#define LC2_REG LOCKDET2
-#define ULC0_REG LOCKDET2
-#define ULC1_REG LOCKDET2
-#define ULC2_REG LOCKDET2
-#define LAT_REG LOCKDET2
-#define EUD_REG LOCKDET2
-
-/* TX_CNTL */
-#define LOC_REG TX_CNTL
-#define TXK_REG TX_CNTL
-#define TXE_REG TX_CNTL
-#define FSK_REG TX_CNTL
-
-/* BTCNT */
-#define C0_REG BTCNT
-#define C1_REG BTCNT
-#define C2_REG BTCNT
-#define C3_REG BTCNT
-#define C4_REG BTCNT
-#define C5_REG BTCNT
-#define C6_REG BTCNT
-#define C7_REG BTCNT
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* BTCR */
-#define F0_REG BTCR
-#define DATA_REG BTCR
-#define F2_REG BTCR
-#define IE_REG BTCR
-#define M0_REG BTCR
-#define M1_REG BTCR
-#define C8_REG BTCR
-#define C9_REG BTCR
-
-/* IO_DATIN */
-#define IOI0_REG IO_DATIN
-#define IOI1_REG IO_DATIN
-#define IOI2_REG IO_DATIN
-#define IOI3_REG IO_DATIN
-#define IOI4_REG IO_DATIN
-#define IOI5_REG IO_DATIN
-
-/* IO_ENAB */
-#define IOE0_REG IO_ENAB
-#define IOE1_REG IO_ENAB
-#define IOE2_REG IO_ENAB
-#define IOE3_REG IO_ENAB
-#define IOE4_REG IO_ENAB
-#define IOE5_REG IO_ENAB
-
-/* LOCKDET1 */
-#define CS0_REG LOCKDET1
-#define CS1_REG LOCKDET1
-#define BOD_REG LOCKDET1
-#define ENKO_REG LOCKDET1
-#define UPOK_REG LOCKDET1
-
-/* IO_DATOUT */
-#define IOO0_REG IO_DATOUT
-#define IOO1_REG IO_DATOUT
-#define IOO2_REG IO_DATOUT
-#define IOO3_REG IO_DATOUT
-#define IOO4_REG IO_DATOUT
-#define IOO5_REG IO_DATOUT
-
-/* DEECR */
-#define EER_REG DEECR
-#define EEL_REG DEECR
-#define EEU_REG DEECR
-#define BSY_REG DEECR
-
-/* PWR_ATTEN */
-#define PCF0_REG PWR_ATTEN
-#define PCF1_REG PWR_ATTEN
-#define PCF2_REG PWR_ATTEN
-#define PCC0_REG PWR_ATTEN
-#define PCC1_REG PWR_ATTEN
-#define PCC2_REG PWR_ATTEN
-
-/* pins mapping */
-