+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM_TOTAL_NUM 4
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* LINBTR */
-#define LBT0_REG LINBTR
-#define LBT1_REG LINBTR
-#define LBT2_REG LINBTR
-#define LBT3_REG LINBTR
-#define LBT4_REG LINBTR
-#define LBT5_REG LINBTR
-#define LDISR_REG LINBTR
-
-/* POCR1RAL */
-#define POCR1RA_0_REG POCR1RAL
-#define POCR1RA_1_REG POCR1RAL
-#define POCR1RA_2_REG POCR1RAL
-#define POCR1RA_3_REG POCR1RAL
-#define POCR1RA_4_REG POCR1RAL
-#define POCR1RA_5_REG POCR1RAL
-#define POCR1RA_6_REG POCR1RAL
-#define POCR1RA_7_REG POCR1RAL
-
-/* LINIDR */
-#define LID0_REG LINIDR
-#define LID1_REG LINIDR
-#define LID2_REG LINIDR
-#define LID3_REG LINIDR
-#define LID4_REG LINIDR
-#define LID5_REG LINIDR
-#define LP0_REG LINIDR
-#define LP1_REG LINIDR
-
-/* POCR1RAH */
-#define POCR1RA_8_REG POCR1RAH
-#define POCR1RA_9_REG POCR1RAH
-#define POCR1RA_00_REG POCR1RAH
-#define POCR1RA_01_REG POCR1RAH
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR0B */
-/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
-
-/* LINSEL */
-#define LINDX0_REG LINSEL
-#define LINDX1_REG LINSEL
-#define LINDX2_REG LINSEL
-#define LAINC_REG LINSEL
-
-/* LINCR */
-#define LCMD0_REG LINCR
-#define LCMD1_REG LINCR
-#define LCMD2_REG LINCR
-#define LENA_REG LINCR
-#define LCONF0_REG LINCR
-#define LCONF1_REG LINCR
-#define LIN13_REG LINCR
-#define LSWRES_REG LINCR
-
-/* PIM */
-#define PEOPE_REG PIM
-#define PEVE0_REG PIM
-#define PEVE1_REG PIM
-#define PEVE2_REG PIM
-
-/* POCR2SBL */
-#define POCR2SB_0_REG POCR2SBL
-#define POCR2SB_1_REG POCR2SBL
-#define POCR2SB_2_REG POCR2SBL
-#define POCR2SB_3_REG POCR2SBL
-#define POCR2SB_4_REG POCR2SBL
-#define POCR2SB_5_REG POCR2SBL
-#define POCR2SB_6_REG POCR2SBL
-#define POCR2SB_7_REG POCR2SBL
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* POCR2SBH */
-#define POCR2SB_8_REG POCR2SBH
-#define POCR2SB_9_REG POCR2SBH
-#define POCR2SB_00_REG POCR2SBH
-#define POCR2SB_01_REG POCR2SBH
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* AC1CON */
-#define AC1M0_REG AC1CON
-#define AC1M1_REG AC1CON
-#define AC1M2_REG AC1CON
-#define AC1ICE_REG AC1CON
-#define AC1IS0_REG AC1CON
-#define AC1IS1_REG AC1CON
-#define AC1IE_REG AC1CON
-#define AC1EN_REG AC1CON
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRLIN_REG PRR
-#define PRSPI_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM1_REG PRR
-#define PRPSC_REG PRR
-#define PRCAN_REG PRR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* LINBRRL */
-#define LDIV0_REG LINBRRL
-#define LDIV1_REG LINBRRL
-#define LDIV2_REG LINBRRL
-#define LDIV3_REG LINBRRL
-#define LDIV4_REG LINBRRL
-#define LDIV5_REG LINBRRL
-#define LDIV6_REG LINBRRL
-#define LDIV7_REG LINBRRL
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-
-/* LINBRRH */
-#define LDIV8_REG LINBRRH
-#define LDIV9_REG LINBRRH
-#define LDIV10_REG LINBRRH
-#define LDIV11_REG LINBRRH
-
-/* CANGSTA */
-#define ERRP_REG CANGSTA
-#define BOFF_REG CANGSTA
-#define ENFG_REG CANGSTA
-#define RXBSY_REG CANGSTA
-#define TXBSY_REG CANGSTA
-#define OVFG_REG CANGSTA
-
-/* CANGCON */
-#define SWRES_REG CANGCON
-#define ENASTB_REG CANGCON
-#define TEST_REG CANGCON
-#define LISTEN_REG CANGCON
-#define SYNTTC_REG CANGCON
-#define TTC_REG CANGCON
-#define OVRQ_REG CANGCON
-#define ABRQ_REG CANGCON
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* PORTE */
-#define PORTE0_REG PORTE
-#define PORTE1_REG PORTE
-#define PORTE2_REG PORTE
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC0_REG PORTC
-#define PORTC1_REG PORTC
-#define PORTC2_REG PORTC
-#define PORTC3_REG PORTC
-#define PORTC4_REG PORTC
-#define PORTC5_REG PORTC
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* AMP1CSR */
-#define AMP1TS0_REG AMP1CSR
-#define AMP1TS1_REG AMP1CSR
-#define AMP1TS2_REG AMP1CSR
-#define AMPCMP1_REG AMP1CSR
-#define AMP1G0_REG AMP1CSR
-#define AMP1G1_REG AMP1CSR
-#define AMP1IS_REG AMP1CSR
-#define AMP1EN_REG AMP1CSR
-
-/* AC2CON */
-#define AC2M0_REG AC2CON
-#define AC2M1_REG AC2CON
-#define AC2M2_REG AC2CON
-#define AC2IS0_REG AC2CON
-#define AC2IS1_REG AC2CON
-#define AC2IE_REG AC2CON
-#define AC2EN_REG AC2CON
-
-/* CANPAGE */
-#define INDX0_REG CANPAGE
-#define INDX1_REG CANPAGE
-#define INDX2_REG CANPAGE
-#define AINC_REG CANPAGE
-#define MOBNB0_REG CANPAGE
-#define MOBNB1_REG CANPAGE
-#define MOBNB2_REG CANPAGE
-#define MOBNB3_REG CANPAGE
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-
-/* LINENIR */
-#define LENRXOK_REG LINENIR
-#define LENTXOK_REG LINENIR
-#define LENIDOK_REG LINENIR
-#define LENERR_REG LINENIR
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* POCR2RAL */
-#define POCR2RA_0_REG POCR2RAL
-#define POCR2RA_1_REG POCR2RAL
-#define POCR2RA_2_REG POCR2RAL
-#define POCR2RA_3_REG POCR2RAL
-#define POCR2RA_4_REG POCR2RAL
-#define POCR2RA_5_REG POCR2RAL
-#define POCR2RA_6_REG POCR2RAL
-#define POCR2RA_7_REG POCR2RAL
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define ADC8D_REG DIDR1
-#define ADC9D_REG DIDR1
-#define ADC10D_REG DIDR1
-#define AMP0ND_REG DIDR1
-#define AMP0PD_REG DIDR1
-#define ACMP0D_REG DIDR1
-#define AMP2PD_REG DIDR1
-
-/* POCR2RAH */
-#define POCR2RA_8_REG POCR2RAH
-#define POCR2RA_9_REG POCR2RAH
-#define POCR2RA_00_REG POCR2RAH
-#define POCR2RA_01_REG POCR2RAH
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* POCR1SAH */
-#define POCR1SA_8_REG POCR1SAH
-#define POCR1SA_9_REG POCR1SAH
-#define POCR1SA_00_REG POCR1SAH
-#define POCR1SA_01_REG POCR1SAH
-
-/* POCR1SAL */
-#define POCR1SA_0_REG POCR1SAL
-#define POCR1SA_1_REG POCR1SAL
-#define POCR1SA_2_REG POCR1SAL
-#define POCR1SA_3_REG POCR1SAL
-#define POCR1SA_4_REG POCR1SAL
-#define POCR1SA_5_REG POCR1SAL
-#define POCR1SA_6_REG POCR1SAL
-#define POCR1SA_7_REG POCR1SAL
-
-/* CANIDM1 */
-#define IDMSK21_REG CANIDM1
-#define IDMSK22_REG CANIDM1
-#define IDMSK23_REG CANIDM1
-#define IDMSK24_REG CANIDM1
-#define IDMSK25_REG CANIDM1
-#define IDMSK26_REG CANIDM1
-#define IDMSK27_REG CANIDM1
-#define IDMSK28_REG CANIDM1
-
-/* CANIDM3 */
-#define IDMSK5_REG CANIDM3
-#define IDMSK6_REG CANIDM3
-#define IDMSK7_REG CANIDM3
-#define IDMSK8_REG CANIDM3
-#define IDMSK9_REG CANIDM3
-#define IDMSK10_REG CANIDM3
-#define IDMSK11_REG CANIDM3
-#define IDMSK12_REG CANIDM3
-
-/* CANIDM2 */
-#define IDMSK13_REG CANIDM2
-#define IDMSK14_REG CANIDM2
-#define IDMSK15_REG CANIDM2
-#define IDMSK16_REG CANIDM2
-#define IDMSK17_REG CANIDM2
-#define IDMSK18_REG CANIDM2
-#define IDMSK19_REG CANIDM2
-#define IDMSK20_REG CANIDM2
-
-/* CANIDM4 */
-#define IDEMSK_REG CANIDM4
-#define RTRMSK_REG CANIDM4
-#define IDMSK0_REG CANIDM4
-#define IDMSK1_REG CANIDM4
-#define IDMSK2_REG CANIDM4
-#define IDMSK3_REG CANIDM4
-#define IDMSK4_REG CANIDM4
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* DDRC */
-#define DDC0_REG DDRC
-#define DDC1_REG DDRC
-#define DDC2_REG DDRC
-#define DDC3_REG DDRC
-#define DDC4_REG DDRC
-#define DDC5_REG DDRC
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* PMIC2 */
-#define PRFM20_REG PMIC2
-#define PRFM21_REG PMIC2
-#define PRFM22_REG PMIC2
-#define PAOC2_REG PMIC2
-#define PFLTE2_REG PMIC2
-#define PELEV2_REG PMIC2
-#define PISEL2_REG PMIC2
-#define POVEN2_REG PMIC2
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* PMIC1 */
-#define PRFM10_REG PMIC1
-#define PRFM11_REG PMIC1
-#define PRFM12_REG PMIC1
-#define PAOC1_REG PMIC1
-#define PFLTE1_REG PMIC1
-#define PELEV1_REG PMIC1
-#define PISEL1_REG PMIC1
-#define POVEN1_REG PMIC1
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* PCTL */
-#define PRUN_REG PCTL
-#define PCCYC_REG PCTL
-#define PCLKSEL_REG PCTL
-#define PPRE0_REG PCTL
-#define PPRE1_REG PCTL
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* CANGIT */
-#define AERG_REG CANGIT
-#define FERG_REG CANGIT
-#define CERG_REG CANGIT
-#define SERG_REG CANGIT
-#define BXOK_REG CANGIT
-#define OVRTIM_REG CANGIT
-#define BOFFIT_REG CANGIT
-#define CANIT_REG CANGIT
-
-/* AC3CON */
-#define AC3M0_REG AC3CON
-#define AC3M1_REG AC3CON
-#define AC3M2_REG AC3CON
-#define AC3IS0_REG AC3CON
-#define AC3IS1_REG AC3CON
-#define AC3IE_REG AC3CON
-#define AC3EN_REG AC3CON
-
-/* LINERR */
-#define LBERR_REG LINERR
-#define LCERR_REG LINERR
-#define LPERR_REG LINERR
-#define LSERR_REG LINERR
-#define LFERR_REG LINERR
-#define LOVERR_REG LINERR
-#define LTOERR_REG LINERR
-#define LABORT_REG LINERR
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-#define PCIE2_REG PCICR
-#define PCIE3_REG PCICR
-
-/* CANGIE */
-#define ENOVRT_REG CANGIE
-#define ENERG_REG CANGIE
-#define ENBX_REG CANGIE
-#define ENERR_REG CANGIE
-#define ENTX_REG CANGIE
-#define ENRX_REG CANGIE
-#define ENBOFF_REG CANGIE
-#define ENIT_REG CANGIE
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* CANIE2 */
-#define IEMOB0_REG CANIE2
-#define IEMOB1_REG CANIE2
-#define IEMOB2_REG CANIE2
-#define IEMOB3_REG CANIE2
-#define IEMOB4_REG CANIE2
-#define IEMOB5_REG CANIE2
-
-/* POCR0RAL */
-#define POCR0RA_0_REG POCR0RAL
-#define POCR0RA_1_REG POCR0RAL
-#define POCR0RA_2_REG POCR0RAL
-#define POCR0RA_3_REG POCR0RAL
-#define POCR0RA_4_REG POCR0RAL
-#define POCR0RA_5_REG POCR0RAL
-#define POCR0RA_6_REG POCR0RAL
-#define POCR0RA_7_REG POCR0RAL
-
-/* CANSIT2 */
-#define SIT0_REG CANSIT2
-#define SIT1_REG CANSIT2
-#define SIT2_REG CANSIT2
-#define SIT3_REG CANSIT2
-#define SIT4_REG CANSIT2
-#define SIT5_REG CANSIT2
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* POCR0RAH */
-#define POCR0RA_8_REG POCR0RAH
-#define POCR0RA_9_REG POCR0RAH
-#define POCR0RA_00_REG POCR0RAH
-#define POCR0RA_01_REG POCR0RAH
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* POCR2SAH */
-#define POCR2SA_8_REG POCR2SAH
-#define POCR2SA_9_REG POCR2SAH
-#define POCR2SA_00_REG POCR2SAH
-#define POCR2SA_01_REG POCR2SAH
-
-/* POCR2SAL */
-#define POCR2SA_0_REG POCR2SAL
-#define POCR2SA_1_REG POCR2SAL
-#define POCR2SA_2_REG POCR2SAL
-#define POCR2SA_3_REG POCR2SAL
-#define POCR2SA_4_REG POCR2SAL
-#define POCR2SA_5_REG POCR2SAL
-#define POCR2SA_6_REG POCR2SAL
-#define POCR2SA_7_REG POCR2SAL
-
-/* DDRE */
-#define DDE0_REG DDRE
-#define DDE1_REG DDRE
-#define DDE2_REG DDRE
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* CANIDT4 */
-#define RB0TAG_REG CANIDT4
-#define RB1TAG_REG CANIDT4
-#define RTRTAG_REG CANIDT4
-#define IDT0_REG CANIDT4
-#define IDT1_REG CANIDT4
-#define IDT2_REG CANIDT4
-#define IDT3_REG CANIDT4
-#define IDT4_REG CANIDT4
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* CANIDT2 */
-#define IDT13_REG CANIDT2
-#define IDT14_REG CANIDT2
-#define IDT15_REG CANIDT2
-#define IDT16_REG CANIDT2
-#define IDT17_REG CANIDT2
-#define IDT18_REG CANIDT2
-#define IDT19_REG CANIDT2
-#define IDT20_REG CANIDT2
-
-/* CANIDT3 */
-#define IDT5_REG CANIDT3
-#define IDT6_REG CANIDT3
-#define IDT7_REG CANIDT3
-#define IDT8_REG CANIDT3
-#define IDT9_REG CANIDT3
-#define IDT10_REG CANIDT3
-#define IDT11_REG CANIDT3
-#define IDT12_REG CANIDT3
-
-/* CANIDT1 */
-#define IDT21_REG CANIDT1
-#define IDT22_REG CANIDT1
-#define IDT23_REG CANIDT1
-#define IDT24_REG CANIDT1
-#define IDT25_REG CANIDT1
-#define IDT26_REG CANIDT1
-#define IDT27_REG CANIDT1
-#define IDT28_REG CANIDT1
-
-/* PSYNC */
-#define PSYNC00_REG PSYNC
-#define PSYNC01_REG PSYNC
-#define PSYNC10_REG PSYNC
-#define PSYNC11_REG PSYNC
-#define PSYNC20_REG PSYNC
-#define PSYNC21_REG PSYNC
-
-/* GTCCR */
-#define PSR10_REG GTCCR
-#define ICPSEL1_REG GTCCR
-#define TSM_REG GTCCR
-#define PSRSYNC_REG GTCCR
-
-/* CANCDMOB */
-#define DLC0_REG CANCDMOB
-#define DLC1_REG CANCDMOB
-#define DLC2_REG CANCDMOB
-#define DLC3_REG CANCDMOB
-#define IDE_REG CANCDMOB
-#define RPLV_REG CANCDMOB
-#define CONMOB0_REG CANCDMOB
-#define CONMOB1_REG CANCDMOB
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* CANHPMOB */
-#define CGP0_REG CANHPMOB
-#define CGP1_REG CANHPMOB
-#define CGP2_REG CANHPMOB
-#define CGP3_REG CANHPMOB
-#define HPMOB0_REG CANHPMOB
-#define HPMOB1_REG CANHPMOB
-#define HPMOB2_REG CANHPMOB
-#define HPMOB3_REG CANHPMOB
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEWE_REG EECR
-#define EEMWE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* POCR1SBL */
-#define POCR1SB_0_REG POCR1SBL
-#define POCR1SB_1_REG POCR1SBL
-#define POCR1SB_2_REG POCR1SBL
-#define POCR1SB_3_REG POCR1SBL
-#define POCR1SB_4_REG POCR1SBL
-#define POCR1SB_5_REG POCR1SBL
-#define POCR1SB_6_REG POCR1SBL
-#define POCR1SB_7_REG POCR1SBL
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PLLF_REG PLLCSR
-
-/* POCR1SBH */
-#define POCR1SB_8_REG POCR1SBH
-#define POCR1SB_9_REG POCR1SBH
-#define POCR1SB_00_REG POCR1SBH
-#define POCR1SB_01_REG POCR1SBH
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-#define PCIF2_REG PCIFR
-#define PCIF3_REG PCIFR
-
-/* AMP2CSR */
-#define AMP2TS0_REG AMP2CSR
-#define AMP2TS1_REG AMP2CSR
-#define AMP2TS2_REG AMP2CSR
-#define AMPCMP2_REG AMP2CSR
-#define AMP2G0_REG AMP2CSR
-#define AMP2G1_REG AMP2CSR
-#define AMP2IS_REG AMP2CSR
-#define AMP2EN_REG AMP2CSR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* LINDAT */
-#define LDATA0_REG LINDAT
-#define LDATA1_REG LINDAT
-#define LDATA2_REG LINDAT
-#define LDATA3_REG LINDAT
-#define LDATA4_REG LINDAT
-#define LDATA5_REG LINDAT
-#define LDATA6_REG LINDAT
-#define LDATA7_REG LINDAT
-
-/* POCR0SAH */
-#define POCR0SA_8_REG POCR0SAH
-#define POCR0SA_9_REG POCR0SAH
-#define POCR0SA_00_REG POCR0SAH
-#define POCR0SA_01_REG POCR0SAH
-
-/* POCR_RBL */
-#define POCR_RB_0_REG POCR_RBL
-#define POCR_RB_1_REG POCR_RBL
-#define POCR_RB_2_REG POCR_RBL
-#define POCR_RB_3_REG POCR_RBL
-#define POCR_RB_4_REG POCR_RBL
-#define POCR_RB_5_REG POCR_RBL
-#define POCR_RB_6_REG POCR_RBL
-#define POCR_RB_7_REG POCR_RBL
-
-/* POCR0SAL */
-#define POCR0SA_0_REG POCR0SAL
-#define POCR0SA_1_REG POCR0SAL
-#define POCR0SA_2_REG POCR0SAL
-#define POCR0SA_3_REG POCR0SAL
-#define POCR0SA_4_REG POCR0SAL
-#define POCR0SA_5_REG POCR0SAL
-#define POCR0SA_6_REG POCR0SAL
-#define POCR0SA_7_REG POCR0SAL
-
-/* POCR_RBH */
-#define POCR_RB_8_REG POCR_RBH
-#define POCR_RB_9_REG POCR_RBH
-#define POCR_RB_00_REG POCR_RBH
-#define POCR_RB_01_REG POCR_RBH
-
-/* LINDLR */
-#define LRXDL0_REG LINDLR
-#define LRXDL1_REG LINDLR
-#define LRXDL2_REG LINDLR
-#define LRXDL3_REG LINDLR
-#define LTXDL0_REG LINDLR
-#define LTXDL1_REG LINDLR
-#define LTXDL2_REG LINDLR
-#define LTXDL3_REG LINDLR
-
-/* MCUCR */
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-#define SPIPS_REG MCUCR
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-
-/* CANSTMOB */
-#define AERR_REG CANSTMOB
-#define FERR_REG CANSTMOB
-#define CERR_REG CANSTMOB
-#define SERR_REG CANSTMOB
-#define BERR_REG CANSTMOB
-#define RXOK_REG CANSTMOB
-#define TXOK_REG CANSTMOB
-#define DLCW_REG CANSTMOB
-
-/* PIFR */
-#define PEOP_REG PIFR
-#define PEV0_REG PIFR
-#define PEV1_REG PIFR
-#define PEV2_REG PIFR
-
-/* LINSIR */
-#define LRXOK_REG LINSIR
-#define LTXOK_REG LINSIR
-#define LIDOK_REG LINSIR
-#define LERR_REG LINSIR
-#define LBUSY_REG LINSIR
-#define LIDST0_REG LINSIR
-#define LIDST1_REG LINSIR
-#define LIDST2_REG LINSIR
-
-/* DACH */
-#define DACH0_REG DACH
-#define DACH1_REG DACH
-#define DACH2_REG DACH
-#define DACH3_REG DACH
-#define DACH4_REG DACH
-#define DACH5_REG DACH
-#define DACH6_REG DACH
-#define DACH7_REG DACH
-
-/* DACL */
-#define DACL0_REG DACL
-#define DACL1_REG DACL
-#define DACL2_REG DACL
-#define DACL3_REG DACL
-#define DACL4_REG DACL
-#define DACL5_REG DACL
-#define DACL6_REG DACL
-#define DACL7_REG DACL
-
-/* CANEN2 */
-#define ENMOB0_REG CANEN2
-#define ENMOB1_REG CANEN2
-#define ENMOB2_REG CANEN2
-#define ENMOB3_REG CANEN2
-#define ENMOB4_REG CANEN2
-#define ENMOB5_REG CANEN2
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ADTS3_REG ADCSRB
-#define AREFEN_REG ADCSRB
-#define ISRCEN_REG ADCSRB
-#define ADHSM_REG ADCSRB
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* OCR0A */
-/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
-
-/* POCR0SBL */
-#define POCR0SB_0_REG POCR0SBL
-#define POCR0SB_1_REG POCR0SBL
-#define POCR0SB_2_REG POCR0SBL
-#define POCR0SB_3_REG POCR0SBL
-#define POCR0SB_4_REG POCR0SBL
-#define POCR0SB_5_REG POCR0SBL
-#define POCR0SB_6_REG POCR0SBL
-#define POCR0SB_7_REG POCR0SBL
-
-/* ACSR */
-#define AC0O_REG ACSR
-#define AC1O_REG ACSR
-#define AC2O_REG ACSR
-#define AC3O_REG ACSR
-#define AC0IF_REG ACSR
-#define AC1IF_REG ACSR
-#define AC2IF_REG ACSR
-#define AC3IF_REG ACSR
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PMIC0 */
-#define PRFM00_REG PMIC0
-#define PRFM01_REG PMIC0
-#define PRFM02_REG PMIC0
-#define PAOC0_REG PMIC0
-#define PFLTE0_REG PMIC0
-#define PELEV0_REG PMIC0
-#define PISEL0_REG PMIC0
-#define POVEN0_REG PMIC0
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* POC */
-#define POEN0A_REG POC
-#define POEN0B_REG POC
-#define POEN1A_REG POC
-#define POEN1B_REG POC
-#define POEN2A_REG POC
-#define POEN2B_REG POC
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* PCNF */
-#define POPA_REG PCNF
-#define POPB_REG PCNF
-#define PMODE_REG PCNF
-#define PULOCK_REG PCNF
-
-/* CANBT2 */
-#define PRS0_REG CANBT2
-#define PRS1_REG CANBT2
-#define PRS2_REG CANBT2
-#define SJW0_REG CANBT2
-#define SJW1_REG CANBT2
-
-/* CANBT3 */
-#define SMP_REG CANBT3
-#define PHS10_REG CANBT3
-#define PHS11_REG CANBT3
-#define PHS12_REG CANBT3
-#define PHS20_REG CANBT3
-#define PHS21_REG CANBT3
-#define PHS22_REG CANBT3
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* CANBT1 */
-#define BRP0_REG CANBT1
-#define BRP1_REG CANBT1
-#define BRP2_REG CANBT1
-#define BRP3_REG CANBT1
-#define BRP4_REG CANBT1
-#define BRP5_REG CANBT1
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* AMP0CSR */
-#define AMP0TS0_REG AMP0CSR
-#define AMP0TS1_REG AMP0CSR
-#define AMP0TS2_REG AMP0CSR
-#define AMPCMP0_REG AMP0CSR
-#define AMP0G0_REG AMP0CSR
-#define AMP0G1_REG AMP0CSR
-#define AMP0IS_REG AMP0CSR
-#define AMP0EN_REG AMP0CSR
-
-/* DACON */
-#define DAEN_REG DACON
-#define DALA_REG DACON
-#define DATS0_REG DACON
-#define DATS1_REG DACON
-#define DATS2_REG DACON
-#define DAATE_REG DACON
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* PCMSK2 */
-#define PCINT16_REG PCMSK2
-#define PCINT17_REG PCMSK2
-#define PCINT18_REG PCMSK2
-#define PCINT19_REG PCMSK2
-#define PCINT20_REG PCMSK2
-#define PCINT21_REG PCMSK2
-#define PCINT22_REG PCMSK2
-#define PCINT23_REG PCMSK2
-
-/* PCMSK3 */
-#define PCINT24_REG PCMSK3
-#define PCINT25_REG PCMSK3
-#define PCINT26_REG PCMSK3
-
-/* PINC */
-#define PINC0_REG PINC
-#define PINC1_REG PINC
-#define PINC2_REG PINC
-#define PINC3_REG PINC
-#define PINC4_REG PINC
-#define PINC5_REG PINC
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* AC0CON */
-#define AC0M0_REG AC0CON
-#define AC0M1_REG AC0CON
-#define AC0M2_REG AC0CON
-#define ACCKSEL_REG AC0CON
-#define AC0IS0_REG AC0CON
-#define AC0IS1_REG AC0CON
-#define AC0IE_REG AC0CON
-#define AC0EN_REG AC0CON
-
-/* PINE */
-#define PINE0_REG PINE
-#define PINE1_REG PINE
-#define PINE2_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* POCR0SBH */
-#define POCR0SB_8_REG POCR0SBH
-#define POCR0SB_9_REG POCR0SBH
-#define POCR0SB_00_REG POCR0SBH
-#define POCR0SB_01_REG POCR0SBH
-
-/* pins mapping */
-#define MISO_PORT PORTB
-#define MISO_BIT 0
-#define PSCOUT2A_PORT PORTB
-#define PSCOUT2A_BIT 0
-#define PCINT0_PORT PORTB
-#define PCINT0_BIT 0
-
-#define MOSI_PORT PORTB
-#define MOSI_BIT 1
-#define PSCOUT2B_PORT PORTB
-#define PSCOUT2B_BIT 1
-#define PCINT1_PORT PORTB
-#define PCINT1_BIT 1
-
-#define ADC5_PORT PORTB
-#define ADC5_BIT 2
-#define INT1_PORT PORTB
-#define INT1_BIT 2
-#define ACMPN0_PORT PORTB
-#define ACMPN0_BIT 2
-#define PCINT2_PORT PORTB
-#define PCINT2_BIT 2
-
-#define AMP0-_PORT PORTB
-#define AMP0-_BIT 3
-#define PCINT3_PORT PORTB
-#define PCINT3_BIT 3
-
-#define AMP0+_PORT PORTB
-#define AMP0+_BIT 4
-#define PCINT4_PORT PORTB
-#define PCINT4_BIT 4
-
-#define ADC6_PORT PORTB
-#define ADC6_BIT 5
-#define INT2_PORT PORTB
-#define INT2_BIT 5
-#define ACMPN1_PORT PORTB
-#define ACMPN1_BIT 5
-#define AMP2-_PORT PORTB
-#define AMP2-_BIT 5
-#define PCINT5_PORT PORTB
-#define PCINT5_BIT 5
-
-#define ADC7_PORT PORTB
-#define ADC7_BIT 6
-#define PSCOUT1B_PORT PORTB
-#define PSCOUT1B_BIT 6
-#define PCINT6_PORT PORTB
-#define PCINT6_BIT 6
-
-#define ADC4_PORT PORTB
-#define ADC4_BIT 7
-#define PSCOUT0B_PORT PORTB
-#define PSCOUT0B_BIT 7
-#define SCK_PORT PORTB
-#define SCK_BIT 7
-#define PCINT7_PORT PORTB
-#define PCINT7_BIT 7
-
-#define INT3_PORT PORTC
-#define INT3_BIT 0
-#define PSCOUT1A_PORT PORTC
-#define PSCOUT1A_BIT 0
-#define PCINT8_PORT PORTC
-#define PCINT8_BIT 0
-
-#define PSCIN1_PORT PORTC
-#define PSCIN1_BIT 1
-#define OC1B_PORT PORTC
-#define OC1B_BIT 1
-#define SS_A_PORT PORTC
-#define SS_A_BIT 1
-#define PCINT9_PORT PORTC
-#define PCINT9_BIT 1
-
-#define T0_PORT PORTC
-#define T0_BIT 2
-#define TXCAN_PORT PORTC
-#define TXCAN_BIT 2
-#define PCINT10_PORT PORTC
-#define PCINT10_BIT 2
-
-#define T1_PORT PORTC
-#define T1_BIT 3
-#define RXCAN_PORT PORTC
-#define RXCAN_BIT 3
-#define ICP1B_PORT PORTC
-#define ICP1B_BIT 3
-#define PCINT11_PORT PORTC
-#define PCINT11_BIT 3
-
-#define ADC8_PORT PORTC
-#define ADC8_BIT 4
-#define AMP1-_PORT PORTC
-#define AMP1-_BIT 4
-#define ACMPN3_PORT PORTC
-#define ACMPN3_BIT 4
-#define PCINT12_PORT PORTC
-#define PCINT12_BIT 4
-
-#define ADC9_PORT PORTC
-#define ADC9_BIT 5
-#define AMP1+_PORT PORTC
-#define AMP1+_BIT 5
-#define ACMP3_PORT PORTC
-#define ACMP3_BIT 5
-#define PCINT13_PORT PORTC
-#define PCINT13_BIT 5
-
-#define ADC10_PORT PORTC
-#define ADC10_BIT 6
-#define ACMP1_PORT PORTC
-#define ACMP1_BIT 6
-#define PCINT14_PORT PORTC
-#define PCINT14_BIT 6
-
-#define D2A_PORT PORTC
-#define D2A_BIT 7
-#define AMP2+_PORT PORTC
-#define AMP2+_BIT 7
-#define PCINT15_PORT PORTC
-#define PCINT15_BIT 7
-
-#define PSCOUT0A_PORT PORTD
-#define PSCOUT0A_BIT 0
-#define PCINT16_PORT PORTD
-#define PCINT16_BIT 0
-
-#define PSCIN0_PORT PORTD
-#define PSCIN0_BIT 1
-#define CLK0_PORT PORTD
-#define CLK0_BIT 1
-#define PCINT17_PORT PORTD
-#define PCINT17_BIT 1
-
-#define PSCIN2_PORT PORTD
-#define PSCIN2_BIT 2
-#define OC1A_PORT PORTD
-#define OC1A_BIT 2
-#define MISO_A_PORT PORTD
-#define MISO_A_BIT 2
-#define PCINT18_PORT PORTD
-#define PCINT18_BIT 2
-
-#define TXD_PORT PORTD
-#define TXD_BIT 3
-#define TXLIN_PORT PORTD
-#define TXLIN_BIT 3
-#define OC0A_PORT PORTD
-#define OC0A_BIT 3
-#define SS_PORT PORTD
-#define SS_BIT 3
-#define MOSI_A_PORT PORTD
-#define MOSI_A_BIT 3
-#define PCINT19_PORT PORTD
-#define PCINT19_BIT 3
-
-#define ADC1_PORT PORTD
-#define ADC1_BIT 4
-#define RXD_PORT PORTD
-#define RXD_BIT 4
-#define RXLIN_PORT PORTD
-#define RXLIN_BIT 4
-#define ICP1A_PORT PORTD
-#define ICP1A_BIT 4
-#define SCK_A_PORT PORTD
-#define SCK_A_BIT 4
-#define PCINT20_PORT PORTD
-#define PCINT20_BIT 4
-
-#define ADC2_PORT PORTD
-#define ADC2_BIT 5
-#define ACMP2_PORT PORTD
-#define ACMP2_BIT 5
-#define PCINT21_PORT PORTD
-#define PCINT21_BIT 5
-
-#define ADC3_PORT PORTD
-#define ADC3_BIT 6
-#define ACMPN2_PORT PORTD
-#define ACMPN2_BIT 6
-#define INT0_PORT PORTD
-#define INT0_BIT 6
-#define PCINT22_PORT PORTD
-#define PCINT22_BIT 6
-
-#define ACMP0_PORT PORTD
-#define ACMP0_BIT 7
-#define PCINT23_PORT PORTD
-#define PCINT23_BIT 7
-
-#define RESET_PORT PORTE
-#define RESET_BIT 0
-#define OCD_PORT PORTE
-#define OCD_BIT 0
-#define PCINT24_PORT PORTE
-#define PCINT24_BIT 0
-
-#define OC0B_PORT PORTE
-#define OC0B_BIT 1
-#define XTAL1_PORT PORTE
-#define XTAL1_BIT 1
-#define PCINT25_PORT PORTE
-#define PCINT25_BIT 1
-
-#define ADC0_PORT PORTE
-#define ADC0_BIT 2
-#define XTAL2_PORT PORTE
-#define XTAL2_BIT 2
-#define PCINT26_PORT PORTE
-#define PCINT26_BIT 2
-
-
git.droids-corp.org / protos / xbee-avr.git / blobdiff