+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-/* prescalers timer 3 */
-#define TIMER3_PRESCALER_DIV_0 0
-#define TIMER3_PRESCALER_DIV_1 1
-#define TIMER3_PRESCALER_DIV_8 2
-#define TIMER3_PRESCALER_DIV_64 3
-#define TIMER3_PRESCALER_DIV_256 4
-#define TIMER3_PRESCALER_DIV_1024 5
-#define TIMER3_PRESCALER_DIV_FALL 6
-#define TIMER3_PRESCALER_DIV_RISE 7
-
-#define TIMER3_PRESCALER_REG_0 0
-#define TIMER3_PRESCALER_REG_1 1
-#define TIMER3_PRESCALER_REG_2 8
-#define TIMER3_PRESCALER_REG_3 64
-#define TIMER3_PRESCALER_REG_4 256
-#define TIMER3_PRESCALER_REG_5 1024
-#define TIMER3_PRESCALER_REG_6 -1
-#define TIMER3_PRESCALER_REG_7 -2
-
-/* prescalers timer 4 */
-
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-#define TIMER1C_AVAILABLE
-#define TIMER3_AVAILABLE
-#define TIMER3A_AVAILABLE
-#define TIMER3B_AVAILABLE
-#define TIMER3C_AVAILABLE
-#define TIMER4_AVAILABLE
-#define TIMER4A_AVAILABLE
-#define TIMER4B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW3_NUM 2
-#define SIG_OVERFLOW4_NUM 3
-#define SIG_OVERFLOW_TOTAL_NUM 4
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1A_NUM 2
-#define SIG_OUTPUT_COMPARE1B_NUM 3
-#define SIG_OUTPUT_COMPARE1C_NUM 4
-#define SIG_OUTPUT_COMPARE3A_NUM 5
-#define SIG_OUTPUT_COMPARE3B_NUM 6
-#define SIG_OUTPUT_COMPARE3C_NUM 7
-#define SIG_OUTPUT_COMPARE4_NUM 8
-#define SIG_OUTPUT_COMPARE4A_NUM 9
-#define SIG_OUTPUT_COMPARE4B_NUM 10
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 11
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1A_NUM 2
-#define PWM1B_NUM 3
-#define PWM1C_NUM 4
-#define PWM3A_NUM 5
-#define PWM3B_NUM 6
-#define PWM3C_NUM 7
-#define PWM4_NUM 8
-#define PWM4A_NUM 9
-#define PWM4B_NUM 10
-#define PWM_TOTAL_NUM 11
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE3_NUM 1
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 2
-
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* UDIEN */
-#define SUSPE_REG UDIEN
-#define SOFE_REG UDIEN
-#define EORSTE_REG UDIEN
-#define WAKEUPE_REG UDIEN
-#define EORSME_REG UDIEN
-#define UPRSME_REG UDIEN
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDCE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* OCR0B */
-#define OCR0B_0_REG OCR0B
-#define OCR0B_1_REG OCR0B
-#define OCR0B_2_REG OCR0B
-#define OCR0B_3_REG OCR0B
-#define OCR0B_4_REG OCR0B
-#define OCR0B_5_REG OCR0B
-#define OCR0B_6_REG OCR0B
-#define OCR0B_7_REG OCR0B
-
-/* UDINT */
-#define SUSPI_REG UDINT
-#define SOFI_REG UDINT
-#define EORSTI_REG UDINT
-#define WAKEUPI_REG UDINT
-#define EORSMI_REG UDINT
-#define UPRSMI_REG UDINT
-
-/* UERST */
-#define EPRST0_REG UERST
-#define EPRST1_REG UERST
-#define EPRST2_REG UERST
-#define EPRST3_REG UERST
-#define EPRST4_REG UERST
-#define EPRST5_REG UERST
-#define EPRST6_REG UERST
-
-/* RAMPZ */
-#define RAMPZ0_REG RAMPZ
-
-/* UECFG1X */
-#define ALLOC_REG UECFG1X
-#define EPBK0_REG UECFG1X
-#define EPBK1_REG UECFG1X
-#define EPSIZE0_REG UECFG1X
-#define EPSIZE1_REG UECFG1X
-#define EPSIZE2_REG UECFG1X
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* EEARH */
-#define EEAR8_REG EEARH
-#define EEAR9_REG EEARH
-#define EEAR10_REG EEARH
-#define EEAR11_REG EEARH
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* PORTD */
-#define PORTD0_REG PORTD
-#define PORTD1_REG PORTD
-#define PORTD2_REG PORTD
-#define PORTD3_REG PORTD
-#define PORTD4_REG PORTD
-#define PORTD5_REG PORTD
-#define PORTD6_REG PORTD
-#define PORTD7_REG PORTD
-
-/* PORTE */
-#define PORTE2_REG PORTE
-#define PORTE6_REG PORTE
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* PORTC */
-#define PORTC6_REG PORTC
-#define PORTC7_REG PORTC
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-#define INT2_REG EIMSK
-#define INT3_REG EIMSK
-#define INT4_REG EIMSK
-#define INT5_REG EIMSK
-#define INT6_REG EIMSK
-#define INT7_REG EIMSK
-
-/* UDR1 */
-#define UDR1_0_REG UDR1
-#define UDR1_1_REG UDR1
-#define UDR1_2_REG UDR1
-#define UDR1_3_REG UDR1
-#define UDR1_4_REG UDR1
-#define UDR1_5_REG UDR1
-#define UDR1_6_REG UDR1
-#define UDR1_7_REG UDR1
-
-/* EICRB */
-#define ISC40_REG EICRB
-#define ISC41_REG EICRB
-#define ISC50_REG EICRB
-#define ISC51_REG EICRB
-#define ISC60_REG EICRB
-#define ISC61_REG EICRB
-#define ISC70_REG EICRB
-#define ISC71_REG EICRB
-
-/* UEDATX */
-#define DAT0_REG UEDATX
-#define DAT1_REG UEDATX
-#define DAT2_REG UEDATX
-#define DAT3_REG UEDATX
-#define DAT4_REG UEDATX
-#define DAT5_REG UEDATX
-#define DAT6_REG UEDATX
-#define DAT7_REG UEDATX
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-#define ISC20_REG EICRA
-#define ISC21_REG EICRA
-#define ISC30_REG EICRA
-#define ISC31_REG EICRA
-
-/* UECFG0X */
-#define EPDIR_REG UECFG0X
-#define EPTYPE0_REG UECFG0X
-#define EPTYPE1_REG UECFG0X
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define AIN0D_REG DIDR1
-#define AIN1D_REG DIDR1
-
-/* DIDR2 */
-#define ADC8D_REG DIDR2
-#define ADC9D_REG DIDR2
-#define ADC10D_REG DIDR2
-#define ADC11D_REG DIDR2
-#define ADC12D_REG DIDR2
-#define ADC13D_REG DIDR2
-
-/* DDRF */
-#define DDF0_REG DDRF
-#define DDF1_REG DDRF
-#define DDF4_REG DDRF
-#define DDF5_REG DDRF
-#define DDF6_REG DDRF
-#define DDF7_REG DDRF
-
-/* CLKSEL1 */
-#define EXCKSEL0_REG CLKSEL1
-#define EXCKSEL1_REG CLKSEL1
-#define EXCKSEL2_REG CLKSEL1
-#define EXCKSEL3_REG CLKSEL1
-#define RCCKSEL0_REG CLKSEL1
-#define RCCKSEL1_REG CLKSEL1
-#define RCCKSEL2_REG CLKSEL1
-#define RCCKSEL3_REG CLKSEL1
-
-/* CLKSEL0 */
-#define CLKS_REG CLKSEL0
-#define EXTE_REG CLKSEL0
-#define RCE_REG CLKSEL0
-#define EXSUT0_REG CLKSEL0
-#define EXSUT1_REG CLKSEL0
-#define RCSUT0_REG CLKSEL0
-#define RCSUT1_REG CLKSEL0
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* UENUM */
-#define UENUM_0_REG UENUM
-#define UENUM_1_REG UENUM
-#define UENUM_2_REG UENUM
-
-/* UBRR1L */
-#define UBRR_0_REG UBRR1L
-#define UBRR_1_REG UBRR1L
-#define UBRR_2_REG UBRR1L
-#define UBRR_3_REG UBRR1L
-#define UBRR_4_REG UBRR1L
-#define UBRR_5_REG UBRR1L
-#define UBRR_6_REG UBRR1L
-#define UBRR_7_REG UBRR1L
-
-/* DDRC */
-#define DDC6_REG DDRC
-#define DDC7_REG DDRC
-
-/* OCR3AL */
-#define OCR3AL0_REG OCR3AL
-#define OCR3AL1_REG OCR3AL
-#define OCR3AL2_REG OCR3AL
-#define OCR3AL3_REG OCR3AL
-#define OCR3AL4_REG OCR3AL
-#define OCR3AL5_REG OCR3AL
-#define OCR3AL6_REG OCR3AL
-#define OCR3AL7_REG OCR3AL
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1C0_REG TCCR1A
-#define COM1C1_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* OCR3AH */
-#define OCR3AH0_REG OCR3AH
-#define OCR3AH1_REG OCR3AH
-#define OCR3AH2_REG OCR3AH
-#define OCR3AH3_REG OCR3AH
-#define OCR3AH4_REG OCR3AH
-#define OCR3AH5_REG OCR3AH
-#define OCR3AH6_REG OCR3AH
-#define OCR3AH7_REG OCR3AH
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* DDRD */
-#define DDD0_REG DDRD
-#define DDD1_REG DDRD
-#define DDD2_REG DDRD
-#define DDD3_REG DDRD
-#define DDD4_REG DDRD
-#define DDD5_REG DDRD
-#define DDD6_REG DDRD
-#define DDD7_REG DDRD
-
-/* OCR4A */
-#define OCR4A0_REG OCR4A
-#define OCR4A1_REG OCR4A
-#define OCR4A2_REG OCR4A
-#define OCR4A3_REG OCR4A
-#define OCR4A4_REG OCR4A
-#define OCR4A5_REG OCR4A
-#define OCR4A6_REG OCR4A
-#define OCR4A7_REG OCR4A
-
-/* OCR4C */
-#define OCR4C0_REG OCR4C
-#define OCR4C1_REG OCR4C
-#define OCR4C2_REG OCR4C
-#define OCR4C3_REG OCR4C
-#define OCR4C4_REG OCR4C
-#define OCR4C5_REG OCR4C
-#define OCR4C6_REG OCR4C
-#define OCR4C7_REG OCR4C
-
-/* OCR4B */
-#define OCR4B0_REG OCR4B
-#define OCR4B1_REG OCR4B
-#define OCR4B2_REG OCR4B
-#define OCR4B3_REG OCR4B
-#define OCR4B4_REG OCR4B
-#define OCR4B5_REG OCR4B
-#define OCR4B6_REG OCR4B
-#define OCR4B7_REG OCR4B
-
-/* OCR4D */
-#define OCR4D0_REG OCR4D
-#define OCR4D1_REG OCR4D
-#define OCR4D2_REG OCR4D
-#define OCR4D3_REG OCR4D
-#define OCR4D4_REG OCR4D
-#define OCR4D5_REG OCR4D
-#define OCR4D6_REG OCR4D
-#define OCR4D7_REG OCR4D
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* RCCTRL */
-#define RCFREQ_REG RCCTRL
-
-/* UDCON */
-#define DETACH_REG UDCON
-#define RMWKUP_REG UDCON
-#define LSM_REG UDCON
-#define RSTCPU_REG UDCON
-
-/* PCICR */
-#define PCIE0_REG PCICR
-
-/* USBINT */
-#define VBUSTI_REG USBINT
-
-/* TCNT0 */
-#define TCNT0_0_REG TCNT0
-#define TCNT0_1_REG TCNT0
-#define TCNT0_2_REG TCNT0
-#define TCNT0_3_REG TCNT0
-#define TCNT0_4_REG TCNT0
-#define TCNT0_5_REG TCNT0
-#define TCNT0_6_REG TCNT0
-#define TCNT0_7_REG TCNT0
-
-/* TCNT4 */
-#define TC40_REG TCNT4
-#define TC41_REG TCNT4
-#define TC42_REG TCNT4
-#define TC43_REG TCNT4
-#define TC44_REG TCNT4
-#define TC45_REG TCNT4
-#define TC46_REG TCNT4
-#define TC47_REG TCNT4
-
-/* TC4H */
-#define TC48_REG TC4H
-#define TC49_REG TC4H
-#define TC410_REG TC4H
-
-/* UHWCON */
-#define UVREGE_REG UHWCON
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define FOC0B_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* UDMFN */
-#define FNCERR_REG UDMFN
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* TIFR4 */
-#define TOV4_REG TIFR4
-#define OCF4B_REG TIFR4
-#define OCF4A_REG TIFR4
-#define OCF4D_REG TIFR4
-
-/* TIFR3 */
-#define TOV3_REG TIFR3
-#define OCF3A_REG TIFR3
-#define OCF3B_REG TIFR3
-#define OCF3C_REG TIFR3
-#define ICF3_REG TIFR3
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define OCF1C_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* UEBCLX */
-#define BYCT0_REG UEBCLX
-#define BYCT1_REG UEBCLX
-#define BYCT2_REG UEBCLX
-#define BYCT3_REG UEBCLX
-#define BYCT4_REG UEBCLX
-#define BYCT5_REG UEBCLX
-#define BYCT6_REG UEBCLX
-#define BYCT7_REG UEBCLX
-
-/* OCR3CH */
-#define OCR3CH0_REG OCR3CH
-#define OCR3CH1_REG OCR3CH
-#define OCR3CH2_REG OCR3CH
-#define OCR3CH3_REG OCR3CH
-#define OCR3CH4_REG OCR3CH
-#define OCR3CH5_REG OCR3CH
-#define OCR3CH6_REG OCR3CH
-#define OCR3CH7_REG OCR3CH
-
-/* UESTA1X */
-#define CURRBK0_REG UESTA1X
-#define CURRBK1_REG UESTA1X
-#define CTRLDIR_REG UESTA1X
-
-/* OCR3CL */
-#define OCR3CL0_REG OCR3CL
-#define OCR3CL1_REG OCR3CL
-#define OCR3CL2_REG OCR3CL
-#define OCR3CL3_REG OCR3CL
-#define OCR3CL4_REG OCR3CL
-#define OCR3CL5_REG OCR3CL
-#define OCR3CL6_REG OCR3CL
-#define OCR3CL7_REG OCR3CL
-
-/* GTCCR */
-#define PSRSYNC_REG GTCCR
-#define TSM_REG GTCCR
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* TCCR3C */
-#define FOC3C_REG TCCR3C
-#define FOC3B_REG TCCR3C
-#define FOC3A_REG TCCR3C
-
-/* TCCR3B */
-#define CS30_REG TCCR3B
-#define CS31_REG TCCR3B
-#define CS32_REG TCCR3B
-#define WGM32_REG TCCR3B
-#define WGM33_REG TCCR3B
-#define ICES3_REG TCCR3B
-#define ICNC3_REG TCCR3B
-
-/* TCCR3A */
-#define WGM30_REG TCCR3A
-#define WGM31_REG TCCR3A
-#define COM3C0_REG TCCR3A
-#define COM3C1_REG TCCR3A
-#define COM3B0_REG TCCR3A
-#define COM3B1_REG TCCR3A
-#define COM3A0_REG TCCR3A
-#define COM3A1_REG TCCR3A
-
-/* UEINTX */
-#define TXINI_REG UEINTX
-#define STALLEDI_REG UEINTX
-#define RXOUTI_REG UEINTX
-#define RXSTPI_REG UEINTX
-#define NAKOUTI_REG UEINTX
-#define RWAL_REG UEINTX
-#define NAKINI_REG UEINTX
-#define FIFOCON_REG UEINTX
-
-/* OCR1BL */
-#define OCR1BL0_REG OCR1BL
-#define OCR1BL1_REG OCR1BL
-#define OCR1BL2_REG OCR1BL
-#define OCR1BL3_REG OCR1BL
-#define OCR1BL4_REG OCR1BL
-#define OCR1BL5_REG OCR1BL
-#define OCR1BL6_REG OCR1BL
-#define OCR1BL7_REG OCR1BL
-
-/* TCNT3H */
-#define TCNT3H0_REG TCNT3H
-#define TCNT3H1_REG TCNT3H
-#define TCNT3H2_REG TCNT3H
-#define TCNT3H3_REG TCNT3H
-#define TCNT3H4_REG TCNT3H
-#define TCNT3H5_REG TCNT3H
-#define TCNT3H6_REG TCNT3H
-#define TCNT3H7_REG TCNT3H
-
-/* OCR1BH */
-#define OCR1BH0_REG OCR1BH
-#define OCR1BH1_REG OCR1BH
-#define OCR1BH2_REG OCR1BH
-#define OCR1BH3_REG OCR1BH
-#define OCR1BH4_REG OCR1BH
-#define OCR1BH5_REG OCR1BH
-#define OCR1BH6_REG OCR1BH
-#define OCR1BH7_REG OCR1BH
-
-/* TCNT3L */
-#define TCNT3L0_REG TCNT3L
-#define TCNT3L1_REG TCNT3L
-#define TCNT3L2_REG TCNT3L
-#define TCNT3L3_REG TCNT3L
-#define TCNT3L4_REG TCNT3L
-#define TCNT3L5_REG TCNT3L
-#define TCNT3L6_REG TCNT3L
-#define TCNT3L7_REG TCNT3L
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* USBCON */
-#define VBUSTE_REG USBCON
-#define OTGPADE_REG USBCON
-#define FRZCLK_REG USBCON
-#define USBE_REG USBCON
-
-/* MCUSR */
-#define JTRF_REG MCUSR
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-
-/* UECONX */
-#define EPEN_REG UECONX
-#define RSTDT_REG UECONX
-#define STALLRQC_REG UECONX
-#define STALLRQ_REG UECONX
-
-/* PLLFRQ */
-#define PDIV0_REG PLLFRQ
-#define PDIV1_REG PLLFRQ
-#define PDIV2_REG PLLFRQ
-#define PDIV3_REG PLLFRQ
-#define PLLTM0_REG PLLFRQ
-#define PLLTM1_REG PLLFRQ
-#define PLLUSB_REG PLLFRQ
-#define PINMUX_REG PLLFRQ
-
-/* UEINT */
-#define EPINT0_REG UEINT
-#define EPINT1_REG UEINT
-#define EPINT2_REG UEINT
-#define EPINT3_REG UEINT
-#define EPINT4_REG UEINT
-#define EPINT5_REG UEINT
-#define EPINT6_REG UEINT
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* MCUCR */
-#define JTD_REG MCUCR
-#define IVCE_REG MCUCR
-#define IVSEL_REG MCUCR
-#define PUD_REG MCUCR
-
-/* OCR1CL */
-#define OCR1CL0_REG OCR1CL
-#define OCR1CL1_REG OCR1CL
-#define OCR1CL2_REG OCR1CL
-#define OCR1CL3_REG OCR1CL
-#define OCR1CL4_REG OCR1CL
-#define OCR1CL5_REG OCR1CL
-#define OCR1CL6_REG OCR1CL
-#define OCR1CL7_REG OCR1CL
-
-/* OCR1CH */
-#define OCR1CH0_REG OCR1CH
-#define OCR1CH1_REG OCR1CH
-#define OCR1CH2_REG OCR1CH
-#define OCR1CH3_REG OCR1CH
-#define OCR1CH4_REG OCR1CH
-#define OCR1CH5_REG OCR1CH
-#define OCR1CH6_REG OCR1CH
-#define OCR1CH7_REG OCR1CH
-
-/* OCDR */
-#define OCDR0_REG OCDR
-#define OCDR1_REG OCDR
-#define OCDR2_REG OCDR
-#define OCDR3_REG OCDR
-#define OCDR4_REG OCDR
-#define OCDR5_REG OCDR
-#define OCDR6_REG OCDR
-#define OCDR7_REG OCDR
-
-/* USBSTA */
-#define VBUS_REG USBSTA
-#define SPEED_REG USBSTA
-
-/* UEIENX */
-#define TXINE_REG UEIENX
-#define STALLEDE_REG UEIENX
-#define RXOUTE_REG UEIENX
-#define RXSTPE_REG UEIENX
-#define NAKOUTE_REG UEIENX
-#define NAKINE_REG UEIENX
-#define FLERRE_REG UEIENX
-
-/* UCSR1B */
-#define TXB81_REG UCSR1B
-#define RXB81_REG UCSR1B
-#define UCSZ12_REG UCSR1B
-#define TXEN1_REG UCSR1B
-#define RXEN1_REG UCSR1B
-#define UDRIE1_REG UCSR1B
-#define TXCIE1_REG UCSR1B
-#define RXCIE1_REG UCSR1B
-
-/* UCSR1C */
-#define UCPOL1_REG UCSR1C
-#define UCSZ10_REG UCSR1C
-#define UCSZ11_REG UCSR1C
-#define USBS1_REG UCSR1C
-#define UPM10_REG UCSR1C
-#define UPM11_REG UCSR1C
-#define UMSEL10_REG UCSR1C
-#define UMSEL11_REG UCSR1C
-
-/* UCSR1A */
-#define MPCM1_REG UCSR1A
-#define U2X1_REG UCSR1A
-#define UPE1_REG UCSR1A
-#define DOR1_REG UCSR1A
-#define FE1_REG UCSR1A
-#define UDRE1_REG UCSR1A
-#define TXC1_REG UCSR1A
-#define RXC1_REG UCSR1A
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* EIND */
-#define EIND0_REG EIND
-
-/* UDFNUML */
-#define FNUM0_REG UDFNUML
-#define FNUM1_REG UDFNUML
-#define FNUM2_REG UDFNUML
-#define FNUM3_REG UDFNUML
-#define FNUM4_REG UDFNUML
-#define FNUM5_REG UDFNUML
-#define FNUM6_REG UDFNUML
-#define FNUM7_REG UDFNUML
-
-/* UDFNUMH */
-#define FNUM8_REG UDFNUMH
-#define FNUM9_REG UDFNUMH
-#define FNUM10_REG UDFNUMH
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define ADTS3_REG ADCSRB
-#define MUX5_REG ADCSRB
-#define ADHSM_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* PRR0 */
-#define PRADC_REG PRR0
-#define PRUSART0_REG PRR0
-#define PRSPI_REG PRR0
-#define PRTIM1_REG PRR0
-#define PRTIM0_REG PRR0
-#define PRTIM2_REG PRR0
-#define PRTWI_REG PRR0
-
-/* UBRR1H */
-#define UBRR_8_REG UBRR1H
-#define UBRR_9_REG UBRR1H
-#define UBRR_10_REG UBRR1H
-#define UBRR_11_REG UBRR1H
-
-/* OCR0A */
-#define OCROA_0_REG OCR0A
-#define OCROA_1_REG OCR0A
-#define OCROA_2_REG OCR0A
-#define OCROA_3_REG OCR0A
-#define OCROA_4_REG OCR0A
-#define OCROA_5_REG OCR0A
-#define OCROA_6_REG OCR0A
-#define OCROA_7_REG OCR0A
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACBG_REG ACSR
-#define ACD_REG ACSR
-
-/* PORTF */
-#define PORTF0_REG PORTF
-#define PORTF1_REG PORTF
-#define PORTF4_REG PORTF
-#define PORTF5_REG PORTF
-#define PORTF6_REG PORTF
-#define PORTF7_REG PORTF
-
-/* TCCR1C */
-#define FOC1C_REG TCCR1C
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* ICR3H */
-#define ICR3H0_REG ICR3H
-#define ICR3H1_REG ICR3H
-#define ICR3H2_REG ICR3H
-#define ICR3H3_REG ICR3H
-#define ICR3H4_REG ICR3H
-#define ICR3H5_REG ICR3H
-#define ICR3H6_REG ICR3H
-#define ICR3H7_REG ICR3H
-
-/* DDRE */
-#define DDE2_REG DDRE
-#define DDE6_REG DDRE
-
-/* UDADDR */
-#define UADD0_REG UDADDR
-#define UADD1_REG UDADDR
-#define UADD2_REG UDADDR
-#define UADD3_REG UDADDR
-#define UADD4_REG UDADDR
-#define UADD5_REG UDADDR
-#define UADD6_REG UDADDR
-#define ADDEN_REG UDADDR
-
-/* ICR3L */
-#define ICR3L0_REG ICR3L
-#define ICR3L1_REG ICR3L
-#define ICR3L2_REG ICR3L
-#define ICR3L3_REG ICR3L
-#define ICR3L4_REG ICR3L
-#define ICR3L5_REG ICR3L
-#define ICR3L6_REG ICR3L
-#define ICR3L7_REG ICR3L
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define BLBSET_REG SPMCSR
-#define RWWSRE_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-#define SPMIE_REG SPMCSR
-
-/* UESTA0X */
-#define NBUSYBK0_REG UESTA0X
-#define NBUSYBK1_REG UESTA0X
-#define DTSEQ0_REG UESTA0X
-#define DTSEQ1_REG UESTA0X
-#define UNDERFI_REG UESTA0X
-#define OVERFI_REG UESTA0X
-#define CFGOK_REG UESTA0X
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* OCR3BL */
-#define OCR3BL0_REG OCR3BL
-#define OCR3BL1_REG OCR3BL
-#define OCR3BL2_REG OCR3BL
-#define OCR3BL3_REG OCR3BL
-#define OCR3BL4_REG OCR3BL
-#define OCR3BL5_REG OCR3BL
-#define OCR3BL6_REG OCR3BL
-#define OCR3BL7_REG OCR3BL
-
-/* OCR3BH */
-#define OCR3BH0_REG OCR3BH
-#define OCR3BH1_REG OCR3BH
-#define OCR3BH2_REG OCR3BH
-#define OCR3BH3_REG OCR3BH
-#define OCR3BH4_REG OCR3BH
-#define OCR3BH5_REG OCR3BH
-#define OCR3BH6_REG OCR3BH
-#define OCR3BH7_REG OCR3BH
-
-/* TIMSK3 */
-#define TOIE3_REG TIMSK3
-#define OCIE3A_REG TIMSK3
-#define OCIE3B_REG TIMSK3
-#define OCIE3C_REG TIMSK3
-#define ICIE3_REG TIMSK3
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define OCIE1C_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* CLKSTA */
-#define EXTON_REG CLKSTA
-#define RCON_REG CLKSTA
-
-/* TIMSK4 */
-#define TOIE4_REG TIMSK4
-#define OCIE4B_REG TIMSK4
-#define OCIE4A_REG TIMSK4
-#define OCIE4D_REG TIMSK4
-
-/* TCCR4B */
-#define CS40_REG TCCR4B
-#define CS41_REG TCCR4B
-#define CS42_REG TCCR4B
-#define CS43_REG TCCR4B
-#define DTPS40_REG TCCR4B
-#define DTPS41_REG TCCR4B
-#define PSR4_REG TCCR4B
-#define PWM4X_REG TCCR4B
-
-/* TCCR4C */
-#define PWM4D_REG TCCR4C
-#define FOC4D_REG TCCR4C
-#define COM4D0_REG TCCR4C
-#define COM4D1_REG TCCR4C
-#define COM4B0S_REG TCCR4C
-#define COM4B1S_REG TCCR4C
-#define COM4A0S_REG TCCR4C
-#define COM4A1S_REG TCCR4C
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PINDIV_REG PLLCSR
-
-/* TCCR4A */
-#define PWM4B_REG TCCR4A
-#define PWM4A_REG TCCR4A
-#define FOC4B_REG TCCR4A
-#define FOC4A_REG TCCR4A
-#define COM4B0_REG TCCR4A
-#define COM4B1_REG TCCR4A
-#define COM4A0_REG TCCR4A
-#define COM4A1_REG TCCR4A
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* TCCR4D */
-#define WGM40_REG TCCR4D
-#define WGM41_REG TCCR4D
-#define FPF4_REG TCCR4D
-#define FPAC4_REG TCCR4D
-#define FPES4_REG TCCR4D
-#define FPNC4_REG TCCR4D
-#define FPEN4_REG TCCR4D
-#define FPIE4_REG TCCR4D
-
-/* TCCR4E */
-#define OC4OE0_REG TCCR4E
-#define OC4OE1_REG TCCR4E
-#define OC4OE2_REG TCCR4E
-#define OC4OE3_REG TCCR4E
-#define OC4OE4_REG TCCR4E
-#define OC4OE5_REG TCCR4E
-#define ENHC4_REG TCCR4E
-#define TLOCK4_REG TCCR4E
-
-/* PINC */
-#define PINC6_REG PINC
-#define PINC7_REG PINC
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-#define INTF2_REG EIFR
-#define INTF3_REG EIFR
-#define INTF4_REG EIFR
-#define INTF5_REG EIFR
-#define INTF6_REG EIFR
-#define INTF7_REG EIFR
-
-/* PINF */
-#define PINF0_REG PINF
-#define PINF1_REG PINF
-#define PINF4_REG PINF
-#define PINF5_REG PINF
-#define PINF6_REG PINF
-#define PINF7_REG PINF
-
-/* PINE */
-#define PINE2_REG PINE
-#define PINE6_REG PINE
-
-/* PIND */
-#define PIND0_REG PIND
-#define PIND1_REG PIND
-#define PIND2_REG PIND
-#define PIND3_REG PIND
-#define PIND4_REG PIND
-#define PIND5_REG PIND
-#define PIND6_REG PIND
-#define PIND7_REG PIND
-
-/* OCR1AH */
-#define OCR1AH0_REG OCR1AH
-#define OCR1AH1_REG OCR1AH
-#define OCR1AH2_REG OCR1AH
-#define OCR1AH3_REG OCR1AH
-#define OCR1AH4_REG OCR1AH
-#define OCR1AH5_REG OCR1AH
-#define OCR1AH6_REG OCR1AH
-#define OCR1AH7_REG OCR1AH
-
-/* OCR1AL */
-#define OCR1AL0_REG OCR1AL
-#define OCR1AL1_REG OCR1AL
-#define OCR1AL2_REG OCR1AL
-#define OCR1AL3_REG OCR1AL
-#define OCR1AL4_REG OCR1AL
-#define OCR1AL5_REG OCR1AL
-#define OCR1AL6_REG OCR1AL
-#define OCR1AL7_REG OCR1AL
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-
-/* PRR1 */
-#define PRUSART1_REG PRR1
-#define PRTIM3_REG PRR1
-#define PRUSB_REG PRR1
-
-/* DT4 */
-#define DT4L0_REG DT4
-#define DT4L1_REG DT4
-#define DT4L2_REG DT4
-#define DT4L3_REG DT4
-#define DT4L4_REG DT4
-#define DT4L5_REG DT4
-#define DT4L6_REG DT4
-#define DT4L7_REG DT4
-
-/* pins mapping */
-
git.droids-corp.org / protos / xbee-avr.git / blobdiff