+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-
-/* available timers */
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW_TOTAL_NUM 0
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
-
-/* Pwm nums */
-#define PWM_TOTAL_NUM 0
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 0
-
-
-/* CLKPSR */
-#define CLKPS0_REG CLKPSR
-#define CLKPS1_REG CLKPSR
-#define CLKPS2_REG CLKPSR
-#define CLKPS3_REG CLKPSR
-
-/* VLMCSR */
-#define VLM0_REG VLMCSR
-#define VLM1_REG VLMCSR
-#define VLMIE_REG VLMCSR
-#define VLMF_REG VLMCSR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-
-/* TCNT0H */
-#define TCNT0_8_REG TCNT0H
-#define TCNT0_9_REG TCNT0H
-#define TCNT0_10_REG TCNT0H
-#define TCNT0_11_REG TCNT0H
-#define TCNT0_12_REG TCNT0H
-#define TCNT0_13_REG TCNT0H
-#define TCNT0_14_REG TCNT0H
-#define TCNT0_15_REG TCNT0H
-
-/* PORTCR */
-#define BBMB_REG PORTCR
-
-/* CCP */
-#define CCP0_REG CCP
-#define CCP1_REG CCP
-#define CCP2_REG CCP
-#define CCP3_REG CCP
-#define CCP4_REG CCP
-#define CCP5_REG CCP
-#define CCP6_REG CCP
-#define CCP7_REG CCP
-
-/* TCNT0L */
-#define TCNT0_0_REG TCNT0L
-#define TCNT0_1_REG TCNT0L
-#define TCNT0_2_REG TCNT0L
-#define TCNT0_3_REG TCNT0L
-#define TCNT0_4_REG TCNT0L
-#define TCNT0_5_REG TCNT0L
-#define TCNT0_6_REG TCNT0L
-#define TCNT0_7_REG TCNT0L
-
-/* WDTCSR */
-#define WDP0_REG WDTCSR
-#define WDP1_REG WDTCSR
-#define WDP2_REG WDTCSR
-#define WDE_REG WDTCSR
-#define WDP3_REG WDTCSR
-#define WDIE_REG WDTCSR
-#define WDIF_REG WDTCSR
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACD_REG ACSR
-
-/* GTCCR */
-#define PSR_REG GTCCR
-#define TSM_REG GTCCR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-
-/* RSTFLR */
-#define PORF_REG RSTFLR
-#define EXTRF_REG RSTFLR
-#define WDRF_REG RSTFLR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-#define SP11_REG SPH
-#define SP12_REG SPH
-#define SP13_REG SPH
-#define SP14_REG SPH
-#define SP15_REG SPH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-
-/* PRR */
-#define PRTIM0_REG PRR
-#define PRADC_REG PRR
-
-/* OCR0BL */
-#define OCR0B0_REG OCR0BL
-#define OCR0B1_REG OCR0BL
-#define OCR0B2_REG OCR0BL
-#define OCR0B3_REG OCR0BL
-#define OCR0B4_REG OCR0BL
-#define OCR0B5_REG OCR0BL
-#define OCR0B6_REG OCR0BL
-#define OCR0B7_REG OCR0BL
-
-/* PCMSK */
-#define PCINT0_REG PCMSK
-#define PCINT1_REG PCMSK
-#define PCINT2_REG PCMSK
-#define PCINT3_REG PCMSK
-
-/* ADCL */
-#define ADC0_REG ADCL
-#define ADC1_REG ADCL
-#define ADC2_REG ADCL
-#define ADC3_REG ADCL
-#define ADC4_REG ADCL
-#define ADC5_REG ADCL
-#define ADC6_REG ADCL
-#define ADC7_REG ADCL
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-#define SM2_REG SMCR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-
-/* PCICR */
-#define PCIE0_REG PCICR
-
-/* NVMCSR */
-#define NVMBSY_REG NVMCSR
-
-/* EIMSK */
-#define INT0_REG EIMSK
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-#define OCIE0B_REG TIMSK0
-#define ICIE0_REG TIMSK0
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define WGM02_REG TCCR0B
-#define WGM03_REG TCCR0B
-#define ICES0_REG TCCR0B
-#define ICNC0_REG TCCR0B
-
-/* TCCR0C */
-#define FOC0B_REG TCCR0C
-#define FOC0A_REG TCCR0C
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0B0_REG TCCR0A
-#define COM0B1_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* CLKMSR */
-#define CLKMS0_REG CLKMSR
-#define CLKMS1_REG CLKMSR
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-
-/* EIFR */
-#define INTF0_REG EIFR
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define AIN0D_REG DIDR0
-#define AIN1D_REG DIDR0
-
-/* OCR0AL */
-#define OCR0A0_REG OCR0AL
-#define OCR0A1_REG OCR0AL
-#define OCR0A2_REG OCR0AL
-#define OCR0A3_REG OCR0AL
-#define OCR0A4_REG OCR0AL
-#define OCR0A5_REG OCR0AL
-#define OCR0A6_REG OCR0AL
-#define OCR0A7_REG OCR0AL
-
-/* NVMCMD */
-#define NVMCMD0_REG NVMCMD
-#define NVMCMD1_REG NVMCMD
-#define NVMCMD2_REG NVMCMD
-#define NVMCMD3_REG NVMCMD
-#define NVMCMD4_REG NVMCMD
-#define NVMCMD5_REG NVMCMD
-
-/* ICR0L */
-#define ICR0_0_REG ICR0L
-#define ICR0_1_REG ICR0L
-#define ICR0_2_REG ICR0L
-#define ICR0_3_REG ICR0L
-#define ICR0_4_REG ICR0L
-#define ICR0_5_REG ICR0L
-#define ICR0_6_REG ICR0L
-#define ICR0_7_REG ICR0L
-
-/* OCR0AH */
-#define OCR0A8_REG OCR0AH
-#define OCR0A9_REG OCR0AH
-#define OCR0A10_REG OCR0AH
-#define OCR0A11_REG OCR0AH
-#define OCR0A12_REG OCR0AH
-#define OCR0A13_REG OCR0AH
-#define OCR0A14_REG OCR0AH
-#define OCR0A15_REG OCR0AH
-
-/* ICR0H */
-#define ICR0_8_REG ICR0H
-#define ICR0_9_REG ICR0H
-#define ICR0_10_REG ICR0H
-#define ICR0_11_REG ICR0H
-#define ICR0_12_REG ICR0H
-#define ICR0_13_REG ICR0H
-#define ICR0_14_REG ICR0H
-#define ICR0_15_REG ICR0H
-
-/* PUEB */
-#define PUEB0_REG PUEB
-#define PUEB1_REG PUEB
-#define PUEB2_REG PUEB
-#define PUEB3_REG PUEB
-
-/* OCR0BH */
-#define OCR0B8_REG OCR0BH
-#define OCR0B9_REG OCR0BH
-#define OCR0B10_REG OCR0BH
-#define OCR0B11_REG OCR0BH
-#define OCR0B12_REG OCR0BH
-#define OCR0B13_REG OCR0BH
-#define OCR0B14_REG OCR0BH
-#define OCR0B15_REG OCR0BH
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-#define OCF0B_REG TIFR0
-#define ICF0_REG TIFR0
-
-/* pins mapping */
-
git.droids-corp.org / protos / xbee-avr.git / blobdiff