+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_32 3
-#define TIMER0_PRESCALER_DIV_64 4
-#define TIMER0_PRESCALER_DIV_128 5
-#define TIMER0_PRESCALER_DIV_256 6
-#define TIMER0_PRESCALER_DIV_1024 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 32
-#define TIMER0_PRESCALER_REG_4 64
-#define TIMER0_PRESCALER_REG_5 128
-#define TIMER0_PRESCALER_REG_6 256
-#define TIMER0_PRESCALER_REG_7 1024
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_8 2
-#define TIMER1_PRESCALER_DIV_64 3
-#define TIMER1_PRESCALER_DIV_256 4
-#define TIMER1_PRESCALER_DIV_1024 5
-#define TIMER1_PRESCALER_DIV_FALL 6
-#define TIMER1_PRESCALER_DIV_RISE 7
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 8
-#define TIMER1_PRESCALER_REG_3 64
-#define TIMER1_PRESCALER_REG_4 256
-#define TIMER1_PRESCALER_REG_5 1024
-#define TIMER1_PRESCALER_REG_6 -1
-#define TIMER1_PRESCALER_REG_7 -2
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE1A_NUM 1
-#define SIG_OUTPUT_COMPARE1B_NUM 2
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 3
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM1A_NUM 1
-#define PWM1B_NUM 2
-#define PWM_TOTAL_NUM 3
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE1_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* LINIDR */
-#define LID0_REG LINIDR
-#define LID1_REG LINIDR
-#define LID2_REG LINIDR
-#define LID3_REG LINIDR
-#define LID4_REG LINIDR
-#define LID5_REG LINIDR
-#define LP0_REG LINIDR
-#define LP1_REG LINIDR
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-#define SP10_REG SPH
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-#define WDP3_REG WDTCR
-#define WDIE_REG WDTCR
-#define WDIF_REG WDTCR
-
-/* PCIFR */
-#define PCIF0_REG PCIFR
-#define PCIF1_REG PCIFR
-
-/* LINBTR */
-#define LBT0_REG LINBTR
-#define LBT1_REG LINBTR
-#define LBT2_REG LINBTR
-#define LBT3_REG LINBTR
-#define LBT4_REG LINBTR
-#define LBT5_REG LINBTR
-#define LDISR_REG LINBTR
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* EICRA */
-#define ISC00_REG EICRA
-#define ISC01_REG EICRA
-#define ISC10_REG EICRA
-#define ISC11_REG EICRA
-
-/* PORTCR */
-#define PUDA_REG PORTCR
-#define PUDB_REG PORTCR
-#define BBMA_REG PORTCR
-#define BBMB_REG PORTCR
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* AMISCR */
-#define XREFEN_REG AMISCR
-#define AREFEN_REG AMISCR
-#define ISRCEN_REG AMISCR
-
-/* CLKSELR */
-#define CSEL0_REG CLKSELR
-#define CSEL1_REG CLKSELR
-#define CSEL2_REG CLKSELR
-#define CSEL3_REG CLKSELR
-#define CSUT0_REG CLKSELR
-#define CSUT1_REG CLKSELR
-#define COUT_REG CLKSELR
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* TCCR1D */
-#define OC1AU_REG TCCR1D
-#define OC1AV_REG TCCR1D
-#define OC1AW_REG TCCR1D
-#define OC1AX_REG TCCR1D
-#define OC1BU_REG TCCR1D
-#define OC1BV_REG TCCR1D
-#define OC1BW_REG TCCR1D
-#define OC1BX_REG TCCR1D
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* TCCR1A */
-#define WGM10_REG TCCR1A
-#define WGM11_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* LINSEL */
-#define LINDX0_REG LINSEL
-#define LINDX1_REG LINSEL
-#define LINDX2_REG LINSEL
-#define LAINC_REG LINSEL
-
-/* TCCR1C */
-#define FOC1B_REG TCCR1C
-#define FOC1A_REG TCCR1C
-
-/* LINCR */
-#define LCMD0_REG LINCR
-#define LCMD1_REG LINCR
-#define LCMD2_REG LINCR
-#define LENA_REG LINCR
-#define LCONF0_REG LINCR
-#define LCONF1_REG LINCR
-#define LIN13_REG LINCR
-#define LSWRES_REG LINCR
-
-/* TIFR1 */
-#define TOV1_REG TIFR1
-#define OCF1A_REG TIFR1
-#define OCF1B_REG TIFR1
-#define ICF1_REG TIFR1
-
-/* ICR1H */
-#define ICR1H0_REG ICR1H
-#define ICR1H1_REG ICR1H
-#define ICR1H2_REG ICR1H
-#define ICR1H3_REG ICR1H
-#define ICR1H4_REG ICR1H
-#define ICR1H5_REG ICR1H
-#define ICR1H6_REG ICR1H
-#define ICR1H7_REG ICR1H
-
-/* GTCCR */
-#define PSR1_REG GTCCR
-#define PSR0_REG GTCCR
-#define TSM_REG GTCCR
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define BIN_REG ADCSRB
-#define ACIR0_REG ADCSRB
-#define ACIR1_REG ADCSRB
-#define ACME_REG ADCSRB
-
-/* SPDR */
-#define SPDR0_REG SPDR
-#define SPDR1_REG SPDR
-#define SPDR2_REG SPDR
-#define SPDR3_REG SPDR
-#define SPDR4_REG SPDR
-#define SPDR5_REG SPDR
-#define SPDR6_REG SPDR
-#define SPDR7_REG SPDR
-
-/* OCR0A */
-#define OCR00_REG OCR0A
-#define OCR01_REG OCR0A
-#define OCR02_REG OCR0A
-#define OCR03_REG OCR0A
-#define OCR04_REG OCR0A
-#define OCR05_REG OCR0A
-#define OCR06_REG OCR0A
-#define OCR07_REG OCR0A
-
-/* SPSR */
-#define SPI2X_REG SPSR
-#define WCOL_REG SPSR
-#define SPIF_REG SPSR
-
-/* ACSR */
-#define ACIS0_REG ACSR
-#define ACIS1_REG ACSR
-#define ACIC_REG ACSR
-#define ACIE_REG ACSR
-#define ACI_REG ACSR
-#define ACO_REG ACSR
-#define ACIRS_REG ACSR
-#define ACD_REG ACSR
-
-/* USIPP */
-#define USIPOS_REG USIPP
-
-/* OCR1BL */
-/* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */
-/* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */
-
-/* ICR1L */
-#define ICR1L0_REG ICR1L
-#define ICR1L1_REG ICR1L
-#define ICR1L2_REG ICR1L
-#define ICR1L3_REG ICR1L
-#define ICR1L4_REG ICR1L
-#define ICR1L5_REG ICR1L
-#define ICR1L6_REG ICR1L
-#define ICR1L7_REG ICR1L
-
-/* OCR1BH */
-/* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */
-/* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSI_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM1_REG PRR
-#define PRSPI_REG PRR
-#define PRLIN_REG PRR
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define RFLB_REG SPMCSR
-#define CTPB_REG SPMCSR
-#define SIGRD_REG SPMCSR
-#define RWWSB_REG SPMCSR
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* LINBRRL */
-#define LDIV0_REG LINBRRL
-#define LDIV1_REG LINBRRL
-#define LDIV2_REG LINBRRL
-#define LDIV3_REG LINBRRL
-#define LDIV4_REG LINBRRL
-#define LDIV5_REG LINBRRL
-#define LDIV6_REG LINBRRL
-#define LDIV7_REG LINBRRL
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SMCR */
-#define SE_REG SMCR
-#define SM0_REG SMCR
-#define SM1_REG SMCR
-
-/* LINBRRH */
-#define LDIV8_REG LINBRRH
-#define LDIV9_REG LINBRRH
-#define LDIV10_REG LINBRRH
-#define LDIV11_REG LINBRRH
-
-/* LINDAT */
-#define LDATA0_REG LINDAT
-#define LDATA1_REG LINDAT
-#define LDATA2_REG LINDAT
-#define LDATA3_REG LINDAT
-#define LDATA4_REG LINDAT
-#define LDATA5_REG LINDAT
-#define LDATA6_REG LINDAT
-#define LDATA7_REG LINDAT
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* TCNT1L */
-#define TCNT1L0_REG TCNT1L
-#define TCNT1L1_REG TCNT1L
-#define TCNT1L2_REG TCNT1L
-#define TCNT1L3_REG TCNT1L
-#define TCNT1L4_REG TCNT1L
-#define TCNT1L5_REG TCNT1L
-#define TCNT1L6_REG TCNT1L
-#define TCNT1L7_REG TCNT1L
-
-/* TCNT1H */
-#define TCNT1H0_REG TCNT1H
-#define TCNT1H1_REG TCNT1H
-#define TCNT1H2_REG TCNT1H
-#define TCNT1H3_REG TCNT1H
-#define TCNT1H4_REG TCNT1H
-#define TCNT1H5_REG TCNT1H
-#define TCNT1H6_REG TCNT1H
-#define TCNT1H7_REG TCNT1H
-
-/* LINENIR */
-#define LENRXOK_REG LINENIR
-#define LENTXOK_REG LINENIR
-#define LENIDOK_REG LINENIR
-#define LENERR_REG LINENIR
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* LINERR */
-#define LBERR_REG LINERR
-#define LCERR_REG LINERR
-#define LPERR_REG LINERR
-#define LSERR_REG LINERR
-#define LFERR_REG LINERR
-#define LOVERR_REG LINERR
-#define LTOERR_REG LINERR
-#define LABORT_REG LINERR
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* TIFR0 */
-#define TOV0_REG TIFR0
-#define OCF0A_REG TIFR0
-
-/* TCNT0 */
-#define TCNT00_REG TCNT0
-#define TCNT01_REG TCNT0
-#define TCNT02_REG TCNT0
-#define TCNT03_REG TCNT0
-#define TCNT04_REG TCNT0
-#define TCNT05_REG TCNT0
-#define TCNT06_REG TCNT0
-#define TCNT07_REG TCNT0
-
-/* PCICR */
-#define PCIE0_REG PCICR
-#define PCIE1_REG PCICR
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* TIMSK0 */
-#define TOIE0_REG TIMSK0
-#define OCIE0A_REG TIMSK0
-
-/* TIMSK1 */
-#define TOIE1_REG TIMSK1
-#define OCIE1A_REG TIMSK1
-#define OCIE1B_REG TIMSK1
-#define ICIE1_REG TIMSK1
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define FOC0A_REG TCCR0B
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define WGM01_REG TCCR0A
-#define COM0A0_REG TCCR0A
-#define COM0A1_REG TCCR0A
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* LINDLR */
-#define LRXDL0_REG LINDLR
-#define LRXDL1_REG LINDLR
-#define LRXDL2_REG LINDLR
-#define LRXDL3_REG LINDLR
-#define LTXDL0_REG LINDLR
-#define LTXDL1_REG LINDLR
-#define LTXDL2_REG LINDLR
-#define LTXDL3_REG LINDLR
-
-/* DWDR */
-#define DWDR0_REG DWDR
-#define DWDR1_REG DWDR
-#define DWDR2_REG DWDR
-#define DWDR3_REG DWDR
-#define DWDR4_REG DWDR
-#define DWDR5_REG DWDR
-#define DWDR6_REG DWDR
-#define DWDR7_REG DWDR
-
-/* EIFR */
-#define INTF0_REG EIFR
-#define INTF1_REG EIFR
-
-/* LINSIR */
-#define LRXOK_REG LINSIR
-#define LTXOK_REG LINSIR
-#define LIDOK_REG LINSIR
-#define LERR_REG LINSIR
-#define LBUSY_REG LINSIR
-#define LIDST0_REG LINSIR
-#define LIDST1_REG LINSIR
-#define LIDST2_REG LINSIR
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-#define ADC7D_REG DIDR0
-
-/* DIDR1 */
-#define ADC8D_REG DIDR1
-#define ADC9D_REG DIDR1
-#define ADC10D_REG DIDR1
-
-/* CLKCSR */
-#define CLKC0_REG CLKCSR
-#define CLKC1_REG CLKCSR
-#define CLKC2_REG CLKCSR
-#define CLKC3_REG CLKCSR
-#define CLKRDY_REG CLKCSR
-#define CLKCCE_REG CLKCSR
-
-/* MCUCR */
-#define PUD_REG MCUCR
-#define BODS_REG MCUCR
-#define BODSE_REG MCUCR
-
-/* OCR1AH */
-/* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */
-/* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */
-
-/* OCR1AL */
-/* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */
-/* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */
-
-/* SPCR */
-#define SPR0_REG SPCR
-#define SPR1_REG SPCR
-#define CPHA_REG SPCR
-#define CPOL_REG SPCR
-#define MSTR_REG SPCR
-#define DORD_REG SPCR
-#define SPE_REG SPCR
-#define SPIE_REG SPCR
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* USIBR */
-#define USIBR0_REG USIBR
-#define USIBR1_REG USIBR
-#define USIBR2_REG USIBR
-#define USIBR3_REG USIBR
-#define USIBR4_REG USIBR
-#define USIBR5_REG USIBR
-#define USIBR6_REG USIBR
-#define USIBR7_REG USIBR
-
-/* EIMSK */
-#define INT0_REG EIMSK
-#define INT1_REG EIMSK
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define WGM12_REG TCCR1B
-#define WGM13_REG TCCR1B
-#define ICES1_REG TCCR1B
-#define ICNC1_REG TCCR1B
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* ASSR */
-#define TCR0BUB_REG ASSR
-#define TCR0AUB_REG ASSR
-#define OCR0AUB_REG ASSR
-#define TCN0UB_REG ASSR
-#define AS0_REG ASSR
-#define EXCLK_REG ASSR
-
-/* pins mapping */
-
git.droids-corp.org / protos / xbee-avr.git / blobdiff