+++ /dev/null
-/*
- * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Revision : $Id $
- *
- */
-
-/* WARNING : this file is automatically generated by scripts.
- * You should not edit it. If you find something wrong in it,
- * write to zer0@droids-corp.org */
-
-
-/* prescalers timer 0 */
-#define TIMER0_PRESCALER_DIV_0 0
-#define TIMER0_PRESCALER_DIV_1 1
-#define TIMER0_PRESCALER_DIV_8 2
-#define TIMER0_PRESCALER_DIV_64 3
-#define TIMER0_PRESCALER_DIV_256 4
-#define TIMER0_PRESCALER_DIV_1024 5
-#define TIMER0_PRESCALER_DIV_FALL 6
-#define TIMER0_PRESCALER_DIV_RISE 7
-
-#define TIMER0_PRESCALER_REG_0 0
-#define TIMER0_PRESCALER_REG_1 1
-#define TIMER0_PRESCALER_REG_2 8
-#define TIMER0_PRESCALER_REG_3 64
-#define TIMER0_PRESCALER_REG_4 256
-#define TIMER0_PRESCALER_REG_5 1024
-#define TIMER0_PRESCALER_REG_6 -1
-#define TIMER0_PRESCALER_REG_7 -2
-
-/* prescalers timer 1 */
-#define TIMER1_PRESCALER_DIV_0 0
-#define TIMER1_PRESCALER_DIV_1 1
-#define TIMER1_PRESCALER_DIV_2 2
-#define TIMER1_PRESCALER_DIV_4 3
-#define TIMER1_PRESCALER_DIV_8 4
-#define TIMER1_PRESCALER_DIV_16 5
-#define TIMER1_PRESCALER_DIV_32 6
-#define TIMER1_PRESCALER_DIV_64 7
-#define TIMER1_PRESCALER_DIV_128 8
-#define TIMER1_PRESCALER_DIV_256 9
-#define TIMER1_PRESCALER_DIV_512 10
-#define TIMER1_PRESCALER_DIV_1024 11
-#define TIMER1_PRESCALER_DIV_2048 12
-#define TIMER1_PRESCALER_DIV_4096 13
-#define TIMER1_PRESCALER_DIV_8192 14
-#define TIMER1_PRESCALER_DIV_16384 15
-
-#define TIMER1_PRESCALER_REG_0 0
-#define TIMER1_PRESCALER_REG_1 1
-#define TIMER1_PRESCALER_REG_2 2
-#define TIMER1_PRESCALER_REG_3 4
-#define TIMER1_PRESCALER_REG_4 8
-#define TIMER1_PRESCALER_REG_5 16
-#define TIMER1_PRESCALER_REG_6 32
-#define TIMER1_PRESCALER_REG_7 64
-#define TIMER1_PRESCALER_REG_8 128
-#define TIMER1_PRESCALER_REG_9 256
-#define TIMER1_PRESCALER_REG_10 512
-#define TIMER1_PRESCALER_REG_11 1024
-#define TIMER1_PRESCALER_REG_12 2048
-#define TIMER1_PRESCALER_REG_13 4096
-#define TIMER1_PRESCALER_REG_14 8192
-#define TIMER1_PRESCALER_REG_15 16384
-
-
-/* available timers */
-#define TIMER0_AVAILABLE
-#define TIMER0A_AVAILABLE
-#define TIMER0B_AVAILABLE
-#define TIMER1_AVAILABLE
-#define TIMER1A_AVAILABLE
-#define TIMER1B_AVAILABLE
-
-/* overflow interrupt number */
-#define SIG_OVERFLOW0_NUM 0
-#define SIG_OVERFLOW1_NUM 1
-#define SIG_OVERFLOW_TOTAL_NUM 2
-
-/* output compare interrupt number */
-#define SIG_OUTPUT_COMPARE0A_NUM 0
-#define SIG_OUTPUT_COMPARE0B_NUM 1
-#define SIG_OUTPUT_COMPARE1_NUM 2
-#define SIG_OUTPUT_COMPARE1A_NUM 3
-#define SIG_OUTPUT_COMPARE1B_NUM 4
-#define SIG_OUTPUT_COMPARE_TOTAL_NUM 5
-
-/* Pwm nums */
-#define PWM0A_NUM 0
-#define PWM0B_NUM 1
-#define PWM1_NUM 2
-#define PWM1A_NUM 3
-#define PWM1B_NUM 4
-#define PWM_TOTAL_NUM 5
-
-/* input capture interrupt number */
-#define SIG_INPUT_CAPTURE0_NUM 0
-#define SIG_INPUT_CAPTURE_TOTAL_NUM 1
-
-
-/* CLKPR */
-#define CLKPS0_REG CLKPR
-#define CLKPS1_REG CLKPR
-#define CLKPS2_REG CLKPR
-#define CLKPS3_REG CLKPR
-#define CLKPCE_REG CLKPR
-
-/* WDTCR */
-#define WDP0_REG WDTCR
-#define WDP1_REG WDTCR
-#define WDP2_REG WDTCR
-#define WDE_REG WDTCR
-#define WDCE_REG WDTCR
-#define WDP3_REG WDTCR
-#define WDIE_REG WDTCR
-#define WDIF_REG WDTCR
-
-/* GIMSK */
-#define PCIE0_REG GIMSK
-#define PCIE1_REG GIMSK
-#define INT0_REG GIMSK
-#define INT1_REG GIMSK
-
-/* DIDR0 */
-#define ADC0D_REG DIDR0
-#define ADC1D_REG DIDR0
-#define ADC2D_REG DIDR0
-#define AREFD_REG DIDR0
-#define ADC3D_REG DIDR0
-#define ADC4D_REG DIDR0
-#define ADC5D_REG DIDR0
-#define ADC6D_REG DIDR0
-
-/* ADMUX */
-#define MUX0_REG ADMUX
-#define MUX1_REG ADMUX
-#define MUX2_REG ADMUX
-#define MUX3_REG ADMUX
-#define MUX4_REG ADMUX
-#define ADLAR_REG ADMUX
-#define REFS0_REG ADMUX
-#define REFS1_REG ADMUX
-
-/* TCNT0H */
-/* #define TCNT0_0_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_1_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_2_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_3_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_4_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_5_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_6_REG TCNT0H */ /* dup in TCNT0L */
-/* #define TCNT0_7_REG TCNT0H */ /* dup in TCNT0L */
-
-/* TCNT0L */
-/* #define TCNT0_0_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_1_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_2_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_3_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_4_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_5_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_6_REG TCNT0L */ /* dup in TCNT0H */
-/* #define TCNT0_7_REG TCNT0L */ /* dup in TCNT0H */
-
-/* DDRB */
-#define DDB0_REG DDRB
-#define DDB1_REG DDRB
-#define DDB2_REG DDRB
-#define DDB3_REG DDRB
-#define DDB4_REG DDRB
-#define DDB5_REG DDRB
-#define DDB6_REG DDRB
-#define DDB7_REG DDRB
-
-/* EEDR */
-#define EEDR0_REG EEDR
-#define EEDR1_REG EEDR
-#define EEDR2_REG EEDR
-#define EEDR3_REG EEDR
-#define EEDR4_REG EEDR
-#define EEDR5_REG EEDR
-#define EEDR6_REG EEDR
-#define EEDR7_REG EEDR
-
-/* TCCR1D */
-#define WGM10_REG TCCR1D
-#define WGM11_REG TCCR1D
-#define FPF1_REG TCCR1D
-#define FPAC1_REG TCCR1D
-#define FPES1_REG TCCR1D
-#define FPNC1_REG TCCR1D
-#define FPEN1_REG TCCR1D
-#define FPIE1_REG TCCR1D
-
-/* MCUCR */
-#define ISC00_REG MCUCR
-#define ISC01_REG MCUCR
-#define SM0_REG MCUCR
-#define SM1_REG MCUCR
-#define SE_REG MCUCR
-#define PUD_REG MCUCR
-
-/* TCCR1A */
-#define PWM1B_REG TCCR1A
-#define PWM1A_REG TCCR1A
-#define FOC1B_REG TCCR1A
-#define FOC1A_REG TCCR1A
-#define COM1B0_REG TCCR1A
-#define COM1B1_REG TCCR1A
-#define COM1A0_REG TCCR1A
-#define COM1A1_REG TCCR1A
-
-/* TCCR1C */
-#define PWM1D_REG TCCR1C
-#define FOC1D_REG TCCR1C
-#define COM1D0_REG TCCR1C
-#define COM1D1_REG TCCR1C
-#define COM1B0S_REG TCCR1C
-#define COM1B1S_REG TCCR1C
-#define COM1A0S_REG TCCR1C
-#define COM1A1S_REG TCCR1C
-
-/* TCCR1B */
-#define CS10_REG TCCR1B
-#define CS11_REG TCCR1B
-#define CS12_REG TCCR1B
-#define CS13_REG TCCR1B
-#define DTPS10_REG TCCR1B
-#define DTPS11_REG TCCR1B
-#define PSR1_REG TCCR1B
-
-/* GIFR */
-#define PCIF_REG GIFR
-#define INTF0_REG GIFR
-#define INTF1_REG GIFR
-
-/* TIMSK */
-#define TICIE0_REG TIMSK
-#define TOIE0_REG TIMSK
-#define OCIE0B_REG TIMSK
-#define OCIE0A_REG TIMSK
-#define TOIE1_REG TIMSK
-#define OCIE1B_REG TIMSK
-#define OCIE1A_REG TIMSK
-#define OCIE1D_REG TIMSK
-
-/* DDRA */
-#define DDA0_REG DDRA
-#define DDA1_REG DDRA
-#define DDA2_REG DDRA
-#define DDA3_REG DDRA
-#define DDA4_REG DDRA
-#define DDA5_REG DDRA
-#define DDA6_REG DDRA
-#define DDA7_REG DDRA
-
-/* ADCSRA */
-#define ADPS0_REG ADCSRA
-#define ADPS1_REG ADCSRA
-#define ADPS2_REG ADCSRA
-#define ADIE_REG ADCSRA
-#define ADIF_REG ADCSRA
-#define ADATE_REG ADCSRA
-#define ADSC_REG ADCSRA
-#define ADEN_REG ADCSRA
-
-/* ACSRB */
-#define ACM0_REG ACSRB
-#define ACM1_REG ACSRB
-#define ACM2_REG ACSRB
-#define HLEV_REG ACSRB
-#define HSEL_REG ACSRB
-
-/* ADCSRB */
-#define ADTS0_REG ADCSRB
-#define ADTS1_REG ADCSRB
-#define ADTS2_REG ADCSRB
-#define MUX5_REG ADCSRB
-#define REFS2_REG ADCSRB
-#define IPR_REG ADCSRB
-#define GSEL_REG ADCSRB
-#define BIN_REG ADCSRB
-
-/* TC1H */
-#define TC18_REG TC1H
-#define TC19_REG TC1H
-
-/* TCCR1E */
-#define OC1OE0_REG TCCR1E
-#define OC1OE1_REG TCCR1E
-#define OC1OE2_REG TCCR1E
-#define OC1OE3_REG TCCR1E
-#define OC1OE4_REG TCCR1E
-#define OC1OE5_REG TCCR1E
-
-/* OCR0A */
-/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
-/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
-
-/* OCR0B */
-/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
-/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
-
-/* SPH */
-#define SP8_REG SPH
-#define SP9_REG SPH
-
-/* SPL */
-#define SP0_REG SPL
-#define SP1_REG SPL
-#define SP2_REG SPL
-#define SP3_REG SPL
-#define SP4_REG SPL
-#define SP5_REG SPL
-#define SP6_REG SPL
-#define SP7_REG SPL
-
-/* PRR */
-#define PRADC_REG PRR
-#define PRUSI_REG PRR
-#define PRTIM0_REG PRR
-#define PRTIM1_REG PRR
-
-/* GPIOR1 */
-#define GPIOR10_REG GPIOR1
-#define GPIOR11_REG GPIOR1
-#define GPIOR12_REG GPIOR1
-#define GPIOR13_REG GPIOR1
-#define GPIOR14_REG GPIOR1
-#define GPIOR15_REG GPIOR1
-#define GPIOR16_REG GPIOR1
-#define GPIOR17_REG GPIOR1
-
-/* GPIOR0 */
-#define GPIOR00_REG GPIOR0
-#define GPIOR01_REG GPIOR0
-#define GPIOR02_REG GPIOR0
-#define GPIOR03_REG GPIOR0
-#define GPIOR04_REG GPIOR0
-#define GPIOR05_REG GPIOR0
-#define GPIOR06_REG GPIOR0
-#define GPIOR07_REG GPIOR0
-
-/* USICR */
-#define USITC_REG USICR
-#define USICLK_REG USICR
-#define USICS0_REG USICR
-#define USICS1_REG USICR
-#define USIWM0_REG USICR
-#define USIWM1_REG USICR
-#define USIOIE_REG USICR
-#define USISIE_REG USICR
-
-/* MCUSR */
-#define PORF_REG MCUSR
-#define EXTRF_REG MCUSR
-#define BORF_REG MCUSR
-#define WDRF_REG MCUSR
-
-/* EECR */
-#define EERE_REG EECR
-#define EEPE_REG EECR
-#define EEMPE_REG EECR
-#define EERIE_REG EECR
-#define EEPM0_REG EECR
-#define EEPM1_REG EECR
-
-/* SPMCSR */
-#define SPMEN_REG SPMCSR
-#define PGERS_REG SPMCSR
-#define PGWRT_REG SPMCSR
-#define RFLB_REG SPMCSR
-#define CTPB_REG SPMCSR
-
-/* OSCCAL */
-#define CAL0_REG OSCCAL
-#define CAL1_REG OSCCAL
-#define CAL2_REG OSCCAL
-#define CAL3_REG OSCCAL
-#define CAL4_REG OSCCAL
-#define CAL5_REG OSCCAL
-#define CAL6_REG OSCCAL
-#define CAL7_REG OSCCAL
-
-/* ADCL */
-#define ADCL0_REG ADCL
-#define ADCL1_REG ADCL
-#define ADCL2_REG ADCL
-#define ADCL3_REG ADCL
-#define ADCL4_REG ADCL
-#define ADCL5_REG ADCL
-#define ADCL6_REG ADCL
-#define ADCL7_REG ADCL
-
-/* USISR */
-#define USICNT0_REG USISR
-#define USICNT1_REG USISR
-#define USICNT2_REG USISR
-#define USICNT3_REG USISR
-#define USIDC_REG USISR
-#define USIPF_REG USISR
-#define USIOIF_REG USISR
-#define USISIF_REG USISR
-
-/* PORTB */
-#define PORTB0_REG PORTB
-#define PORTB1_REG PORTB
-#define PORTB2_REG PORTB
-#define PORTB3_REG PORTB
-#define PORTB4_REG PORTB
-#define PORTB5_REG PORTB
-#define PORTB6_REG PORTB
-#define PORTB7_REG PORTB
-
-/* ADCH */
-#define ADCH0_REG ADCH
-#define ADCH1_REG ADCH
-#define ADCH2_REG ADCH
-#define ADCH3_REG ADCH
-#define ADCH4_REG ADCH
-#define ADCH5_REG ADCH
-#define ADCH6_REG ADCH
-#define ADCH7_REG ADCH
-
-/* PORTA */
-#define PORTA0_REG PORTA
-#define PORTA1_REG PORTA
-#define PORTA2_REG PORTA
-#define PORTA3_REG PORTA
-#define PORTA4_REG PORTA
-#define PORTA5_REG PORTA
-#define PORTA6_REG PORTA
-#define PORTA7_REG PORTA
-
-/* ACSRA */
-#define ACIS0_REG ACSRA
-#define ACIS1_REG ACSRA
-#define ACME_REG ACSRA
-#define ACIE_REG ACSRA
-#define ACI_REG ACSRA
-#define ACO_REG ACSRA
-#define ACBG_REG ACSRA
-#define ACD_REG ACSRA
-
-/* TCNT1 */
-#define TC1H_0_REG TCNT1
-#define TC1H_1_REG TCNT1
-#define TC1H_2_REG TCNT1
-#define TC1H_3_REG TCNT1
-#define TC1H_4_REG TCNT1
-#define TC1H_5_REG TCNT1
-#define TC1H_6_REG TCNT1
-#define TC1H_7_REG TCNT1
-
-/* EEARL */
-#define EEAR0_REG EEARL
-#define EEAR1_REG EEARL
-#define EEAR2_REG EEARL
-#define EEAR3_REG EEARL
-#define EEAR4_REG EEARL
-#define EEAR5_REG EEARL
-#define EEAR6_REG EEARL
-#define EEAR7_REG EEARL
-
-/* SREG */
-#define C_REG SREG
-#define Z_REG SREG
-#define N_REG SREG
-#define V_REG SREG
-#define S_REG SREG
-#define H_REG SREG
-#define T_REG SREG
-#define I_REG SREG
-
-/* TCCR0B */
-#define CS00_REG TCCR0B
-#define CS01_REG TCCR0B
-#define CS02_REG TCCR0B
-#define PSR0_REG TCCR0B
-#define TSM_REG TCCR0B
-
-/* TIFR */
-#define ICF0_REG TIFR
-#define TOV0_REG TIFR
-#define OCF0B_REG TIFR
-#define OCF0A_REG TIFR
-#define TOV1_REG TIFR
-#define OCF1B_REG TIFR
-#define OCF1A_REG TIFR
-#define OCF1D_REG TIFR
-
-/* TCCR0A */
-#define WGM00_REG TCCR0A
-#define ACIC0_REG TCCR0A
-#define ICES0_REG TCCR0A
-#define ICNC0_REG TCCR0A
-#define ICEN0_REG TCCR0A
-#define TCW0_REG TCCR0A
-
-/* EEARH */
-#define EEAR8_REG EEARH
-
-/* PLLCSR */
-#define PLOCK_REG PLLCSR
-#define PLLE_REG PLLCSR
-#define PCKE_REG PLLCSR
-#define LSM_REG PLLCSR
-
-/* GPIOR2 */
-#define GPIOR20_REG GPIOR2
-#define GPIOR21_REG GPIOR2
-#define GPIOR22_REG GPIOR2
-#define GPIOR23_REG GPIOR2
-#define GPIOR24_REG GPIOR2
-#define GPIOR25_REG GPIOR2
-#define GPIOR26_REG GPIOR2
-#define GPIOR27_REG GPIOR2
-
-/* PCMSK0 */
-#define PCINT0_REG PCMSK0
-#define PCINT1_REG PCMSK0
-#define PCINT2_REG PCMSK0
-#define PCINT3_REG PCMSK0
-#define PCINT4_REG PCMSK0
-#define PCINT5_REG PCMSK0
-#define PCINT6_REG PCMSK0
-#define PCINT7_REG PCMSK0
-
-/* PCMSK1 */
-#define PCINT8_REG PCMSK1
-#define PCINT9_REG PCMSK1
-#define PCINT10_REG PCMSK1
-#define PCINT11_REG PCMSK1
-#define PCINT12_REG PCMSK1
-#define PCINT13_REG PCMSK1
-#define PCINT14_REG PCMSK1
-#define PCINT15_REG PCMSK1
-
-/* DWDR */
-#define DWDR0_REG DWDR
-#define DWDR1_REG DWDR
-#define DWDR2_REG DWDR
-#define DWDR3_REG DWDR
-#define DWDR4_REG DWDR
-#define DWDR5_REG DWDR
-#define DWDR6_REG DWDR
-#define DWDR7_REG DWDR
-
-/* OCR1D */
-#define OCR1D0_REG OCR1D
-#define OCR1D1_REG OCR1D
-#define OCR1D2_REG OCR1D
-#define OCR1D3_REG OCR1D
-#define OCR1D4_REG OCR1D
-#define OCR1D5_REG OCR1D
-#define OCR1D6_REG OCR1D
-/* #define OCR1C7_REG OCR1D */ /* dup in OCR1C */
-
-/* OCR1B */
-#define OCR1B0_REG OCR1B
-#define OCR1B1_REG OCR1B
-#define OCR1B2_REG OCR1B
-#define OCR1B3_REG OCR1B
-#define OCR1B4_REG OCR1B
-#define OCR1B5_REG OCR1B
-#define OCR1B6_REG OCR1B
-#define OCR1B7_REG OCR1B
-
-/* OCR1C */
-#define OCR1C0_REG OCR1C
-#define OCR1C1_REG OCR1C
-#define OCR1C2_REG OCR1C
-#define OCR1C3_REG OCR1C
-#define OCR1C4_REG OCR1C
-#define OCR1C5_REG OCR1C
-#define OCR1C6_REG OCR1C
-/* #define OCR1C7_REG OCR1C */ /* dup in OCR1D */
-
-/* OCR1A */
-#define OCR1A0_REG OCR1A
-#define OCR1A1_REG OCR1A
-#define OCR1A2_REG OCR1A
-#define OCR1A3_REG OCR1A
-#define OCR1A4_REG OCR1A
-#define OCR1A5_REG OCR1A
-#define OCR1A6_REG OCR1A
-#define OCR1A7_REG OCR1A
-
-/* USIPP */
-#define USIPOS_REG USIPP
-
-/* PINB */
-#define PINB0_REG PINB
-#define PINB1_REG PINB
-#define PINB2_REG PINB
-#define PINB3_REG PINB
-#define PINB4_REG PINB
-#define PINB5_REG PINB
-#define PINB6_REG PINB
-#define PINB7_REG PINB
-
-/* USIBR */
-#define USIBR0_REG USIBR
-#define USIBR1_REG USIBR
-#define USIBR2_REG USIBR
-#define USIBR3_REG USIBR
-#define USIBR4_REG USIBR
-#define USIBR5_REG USIBR
-#define USIBR6_REG USIBR
-#define USIBR7_REG USIBR
-
-/* DT1 */
-#define DT1L0_REG DT1
-#define DT1L1_REG DT1
-#define DT1L2_REG DT1
-#define DT1L3_REG DT1
-#define DT1H0_REG DT1
-#define DT1H1_REG DT1
-#define DT1H2_REG DT1
-#define DT1H3_REG DT1
-
-/* PINA */
-#define PINA0_REG PINA
-#define PINA1_REG PINA
-#define PINA2_REG PINA
-#define PINA3_REG PINA
-#define PINA4_REG PINA
-#define PINA5_REG PINA
-#define PINA6_REG PINA
-#define PINA7_REG PINA
-
-/* USIDR */
-#define USIDR0_REG USIDR
-#define USIDR1_REG USIDR
-#define USIDR2_REG USIDR
-#define USIDR3_REG USIDR
-#define USIDR4_REG USIDR
-#define USIDR5_REG USIDR
-#define USIDR6_REG USIDR
-#define USIDR7_REG USIDR
-
-/* DIDR1 */
-#define ADC7D_REG DIDR1
-#define ADC8D_REG DIDR1
-#define ADC9D_REG DIDR1
-#define ADC10D_REG DIDR1
-
-/* pins mapping */
-
git.droids-corp.org / protos / xbee-avr.git / blobdiff