2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_8 2
50 #define TIMER1_PRESCALER_DIV_64 3
51 #define TIMER1_PRESCALER_DIV_256 4
52 #define TIMER1_PRESCALER_DIV_1024 5
53 #define TIMER1_PRESCALER_DIV_FALL 6
54 #define TIMER1_PRESCALER_DIV_RISE 7
56 #define TIMER1_PRESCALER_REG_0 0
57 #define TIMER1_PRESCALER_REG_1 1
58 #define TIMER1_PRESCALER_REG_2 8
59 #define TIMER1_PRESCALER_REG_3 64
60 #define TIMER1_PRESCALER_REG_4 256
61 #define TIMER1_PRESCALER_REG_5 1024
62 #define TIMER1_PRESCALER_REG_6 -1
63 #define TIMER1_PRESCALER_REG_7 -2
66 /* available timers */
67 #define TIMER0_AVAILABLE
68 #define TIMER0B_AVAILABLE
69 #define TIMER1_AVAILABLE
70 #define TIMER1A_AVAILABLE
71 #define TIMER1B_AVAILABLE
73 /* overflow interrupt number */
74 #define SIG_OVERFLOW0_NUM 0
75 #define SIG_OVERFLOW1_NUM 1
76 #define SIG_OVERFLOW_TOTAL_NUM 2
78 /* output compare interrupt number */
79 #define SIG_OUTPUT_COMPARE0_NUM 0
80 #define SIG_OUTPUT_COMPARE0B_NUM 1
81 #define SIG_OUTPUT_COMPARE1A_NUM 2
82 #define SIG_OUTPUT_COMPARE1B_NUM 3
83 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
90 #define PWM_TOTAL_NUM 4
92 /* input capture interrupt number */
93 #define SIG_INPUT_CAPTURE1_NUM 0
94 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
98 #define EUDR0_REG EUDR
99 #define EUDR1_REG EUDR
100 #define EUDR2_REG EUDR
101 #define EUDR3_REG EUDR
102 #define EUDR4_REG EUDR
103 #define EUDR5_REG EUDR
104 #define EUDR6_REG EUDR
105 #define EUDR7_REG EUDR
108 #define MUX0_REG ADMUX
109 #define MUX1_REG ADMUX
110 #define MUX2_REG ADMUX
111 #define MUX3_REG ADMUX
112 #define ADLAR_REG ADMUX
113 #define REFS0_REG ADMUX
114 #define REFS1_REG ADMUX
127 #define OCR2SB_8_REG OCR2SBH
128 #define OCR2SB_9_REG OCR2SBH
129 #define OCR2SB_10_REG OCR2SBH
130 #define OCR2SB_11_REG OCR2SBH
133 #define OCR2SB_0_REG OCR2SBL
134 #define OCR2SB_1_REG OCR2SBL
135 #define OCR2SB_2_REG OCR2SBL
136 #define OCR2SB_3_REG OCR2SBL
137 #define OCR2SB_4_REG OCR2SBL
138 #define OCR2SB_5_REG OCR2SBL
139 #define OCR2SB_6_REG OCR2SBL
140 #define OCR2SB_7_REG OCR2SBL
143 #define WDP0_REG WDTCSR
144 #define WDP1_REG WDTCSR
145 #define WDP2_REG WDTCSR
146 #define WDE_REG WDTCSR
147 #define WDCE_REG WDTCSR
148 #define WDP3_REG WDTCSR
149 #define WDIE_REG WDTCSR
150 #define WDIF_REG WDTCSR
153 #define EEDR0_REG EEDR
154 #define EEDR1_REG EEDR
155 #define EEDR2_REG EEDR
156 #define EEDR3_REG EEDR
157 #define EEDR4_REG EEDR
158 #define EEDR5_REG EEDR
159 #define EEDR6_REG EEDR
160 #define EEDR7_REG EEDR
163 /* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */
164 /* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */
165 /* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */
166 /* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */
167 /* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */
168 /* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */
169 /* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */
170 /* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */
173 #define SPDR0_REG SPDR
174 #define SPDR1_REG SPDR
175 #define SPDR2_REG SPDR
176 #define SPDR3_REG SPDR
177 #define SPDR4_REG SPDR
178 #define SPDR5_REG SPDR
179 #define SPDR6_REG SPDR
180 #define SPDR7_REG SPDR
183 #define SPI2X_REG SPSR
184 #define WCOL_REG SPSR
185 #define SPIF_REG SPSR
188 #define ICR1H0_REG ICR1H
189 #define ICR1H1_REG ICR1H
190 #define ICR1H2_REG ICR1H
191 #define ICR1H3_REG ICR1H
192 #define ICR1H4_REG ICR1H
193 #define ICR1H5_REG ICR1H
194 #define ICR1H6_REG ICR1H
195 #define ICR1H7_REG ICR1H
198 #define MPCM_REG UCSRA
199 #define U2X_REG UCSRA
200 #define UPE_REG UCSRA
201 #define DOR_REG UCSRA
203 #define UDRE_REG UCSRA
204 #define TXC_REG UCSRA
205 #define RXC_REG UCSRA
208 #define TXB8_REG UCSRB
209 #define RXB8_REG UCSRB
210 #define UCSZ2_REG UCSRB
211 #define TXEN_REG UCSRB
212 #define RXEN_REG UCSRB
213 #define UDRIE_REG UCSRB
214 #define TXCIE_REG UCSRB
215 #define RXCIE_REG UCSRB
218 #define UCPOL_REG UCSRC
219 #define UCSZ0_REG UCSRC
220 #define UCSZ1_REG UCSRC
221 #define USBS_REG UCSRC
222 #define UPM0_REG UCSRC
223 #define UPM1_REG UCSRC
224 #define UMSEL0_REG UCSRC
227 #define ICR1L0_REG ICR1L
228 #define ICR1L1_REG ICR1L
229 #define ICR1L2_REG ICR1L
230 #define ICR1L3_REG ICR1L
231 #define ICR1L4_REG ICR1L
232 #define ICR1L5_REG ICR1L
233 #define ICR1L6_REG ICR1L
234 #define ICR1L7_REG ICR1L
237 #define AC1M0_REG AC1CON
238 #define AC1M1_REG AC1CON
239 #define AC1M2_REG AC1CON
240 #define AC1ICE_REG AC1CON
241 #define AC1IS0_REG AC1CON
242 #define AC1IS1_REG AC1CON
243 #define AC1IE_REG AC1CON
244 #define AC1EN_REG AC1CON
247 #define PRADC_REG PRR
248 #define PRUSART0_REG PRR
249 #define PRSPI_REG PRR
250 #define PRTIM0_REG PRR
251 #define PRTIM1_REG PRR
252 #define PRPSC0_REG PRR
253 #define PRPSC1_REG PRR
254 #define PRPSC2_REG PRR
257 #define PCLKSEL0_REG PCNF0
258 #define POP0_REG PCNF0
259 #define PMODE00_REG PCNF0
260 #define PMODE01_REG PCNF0
261 #define PLOCK0_REG PCNF0
262 #define PALOCK0_REG PCNF0
263 #define PFIFTY0_REG PCNF0
266 #define PCLKSEL1_REG PCNF1
267 #define POP1_REG PCNF1
268 #define PMODE10_REG PCNF1
269 #define PMODE11_REG PCNF1
270 #define PLOCK1_REG PCNF1
271 #define PALOCK1_REG PCNF1
272 #define PFIFTY1_REG PCNF1
275 #define POME2_REG PCNF2
276 #define PCLKSEL2_REG PCNF2
277 #define POP2_REG PCNF2
278 #define PMODE20_REG PCNF2
279 #define PMODE21_REG PCNF2
280 #define PLOCK2_REG PCNF2
281 #define PALOCK2_REG PCNF2
282 #define PFIFTY2_REG PCNF2
285 #define TCNT1L0_REG TCNT1L
286 #define TCNT1L1_REG TCNT1L
287 #define TCNT1L2_REG TCNT1L
288 #define TCNT1L3_REG TCNT1L
289 #define TCNT1L4_REG TCNT1L
290 #define TCNT1L5_REG TCNT1L
291 #define TCNT1L6_REG TCNT1L
292 #define TCNT1L7_REG TCNT1L
295 #define PORTD0_REG PORTD
296 #define PORTD1_REG PORTD
297 #define PORTD2_REG PORTD
298 #define PORTD3_REG PORTD
299 #define PORTD4_REG PORTD
300 #define PORTD5_REG PORTD
301 #define PORTD6_REG PORTD
302 #define PORTD7_REG PORTD
305 #define PORTE0_REG PORTE
306 #define PORTE1_REG PORTE
307 #define PORTE2_REG PORTE
310 #define TCNT1H0_REG TCNT1H
311 #define TCNT1H1_REG TCNT1H
312 #define TCNT1H2_REG TCNT1H
313 #define TCNT1H3_REG TCNT1H
314 #define TCNT1H4_REG TCNT1H
315 #define TCNT1H5_REG TCNT1H
316 #define TCNT1H6_REG TCNT1H
317 #define TCNT1H7_REG TCNT1H
320 #define PORTC0_REG PORTC
321 #define PORTC1_REG PORTC
322 #define PORTC2_REG PORTC
323 #define PORTC3_REG PORTC
324 #define PORTC4_REG PORTC
325 #define PORTC5_REG PORTC
326 #define PORTC6_REG PORTC
327 #define PORTC7_REG PORTC
330 #define AMP1TS0_REG AMP1CSR
331 #define AMP1TS1_REG AMP1CSR
332 #define AMP1G0_REG AMP1CSR
333 #define AMP1G1_REG AMP1CSR
334 #define AMP1IS_REG AMP1CSR
335 #define AMP1EN_REG AMP1CSR
338 #define AC2M0_REG AC2CON
339 #define AC2M1_REG AC2CON
340 #define AC2M2_REG AC2CON
341 #define AC2IS0_REG AC2CON
342 #define AC2IS1_REG AC2CON
343 #define AC2IE_REG AC2CON
344 #define AC2EN_REG AC2CON
347 #define INT0_REG EIMSK
348 #define INT1_REG EIMSK
349 #define INT2_REG EIMSK
350 #define INT3_REG EIMSK
353 #define PRFM0A0_REG PFRC0A
354 #define PRFM0A1_REG PFRC0A
355 #define PRFM0A2_REG PFRC0A
356 #define PRFM0A3_REG PFRC0A
357 #define PFLTE0A_REG PFRC0A
358 #define PELEV0A_REG PFRC0A
359 #define PISEL0A_REG PFRC0A
360 #define PCAE0A_REG PFRC0A
363 #define PRFM0B0_REG PFRC0B
364 #define PRFM0B1_REG PFRC0B
365 #define PRFM0B2_REG PFRC0B
366 #define PRFM0B3_REG PFRC0B
367 #define PFLTE0B_REG PFRC0B
368 #define PELEV0B_REG PFRC0B
369 #define PISEL0B_REG PFRC0B
370 #define PCAE0B_REG PFRC0B
373 #define PICR1_8_REG PICR1H
374 #define PICR1_9_REG PICR1H
375 #define PICR1_10_REG PICR1H
376 #define PICR1_11_REG PICR1H
377 #define PCST1_REG PICR1H
380 #define PICR1_0_REG PICR1L
381 #define PICR1_1_REG PICR1L
382 #define PICR1_2_REG PICR1L
383 #define PICR1_3_REG PICR1L
384 #define PICR1_4_REG PICR1L
385 #define PICR1_5_REG PICR1L
386 #define PICR1_6_REG PICR1L
387 #define PICR1_7_REG PICR1L
390 #define ISC00_REG EICRA
391 #define ISC01_REG EICRA
392 #define ISC10_REG EICRA
393 #define ISC11_REG EICRA
394 #define ISC20_REG EICRA
395 #define ISC21_REG EICRA
396 #define ISC30_REG EICRA
397 #define ISC31_REG EICRA
400 #define ADC0D_REG DIDR0
401 #define ADC1D_REG DIDR0
402 #define ADC2D_REG DIDR0
403 #define ADC3D_REG DIDR0
404 #define ADC4D_REG DIDR0
405 #define ADC5D_REG DIDR0
406 #define ADC6D_REG DIDR0
407 #define ADC7D_REG DIDR0
410 #define ADC8D_REG DIDR1
411 #define ADC9D_REG DIDR1
412 #define ADC10D_REG DIDR1
413 #define AMP0ND_REG DIDR1
414 #define AMP0PD_REG DIDR1
415 #define ACMP0D_REG DIDR1
418 #define OCR1RA_8_REG OCR1RAH
419 #define OCR1RA_9_REG OCR1RAH
420 #define OCR1RA_10_REG OCR1RAH
421 #define OCR1RA_11_REG OCR1RAH
424 #define OCR1RA_0_REG OCR1RAL
425 #define OCR1RA_1_REG OCR1RAL
426 #define OCR1RA_2_REG OCR1RAL
427 #define OCR1RA_3_REG OCR1RAL
428 #define OCR1RA_4_REG OCR1RAL
429 #define OCR1RA_5_REG OCR1RAL
430 #define OCR1RA_6_REG OCR1RAL
431 #define OCR1RA_7_REG OCR1RAL
434 #define CLKPS0_REG CLKPR
435 #define CLKPS1_REG CLKPR
436 #define CLKPS2_REG CLKPR
437 #define CLKPS3_REG CLKPR
438 #define CLKPCE_REG CLKPR
441 #define OCR0RB_8_REG OCR0RBH
442 #define OCR0RB_9_REG OCR0RBH
443 #define OCR0RB_00_REG OCR0RBH
444 #define OCR0RB_01_REG OCR0RBH
445 #define OCR0RB_02_REG OCR0RBH
446 #define OCR0RB_03_REG OCR0RBH
447 #define OCR0RB_04_REG OCR0RBH
448 #define OCR0RB_05_REG OCR0RBH
451 #define OCR0RB_0_REG OCR0RBL
452 #define OCR0RB_1_REG OCR0RBL
453 #define OCR0RB_2_REG OCR0RBL
454 #define OCR0RB_3_REG OCR0RBL
455 #define OCR0RB_4_REG OCR0RBL
456 #define OCR0RB_5_REG OCR0RBL
457 #define OCR0RB_6_REG OCR0RBL
458 #define OCR0RB_7_REG OCR0RBL
461 #define DDB0_REG DDRB
462 #define DDB1_REG DDRB
463 #define DDB2_REG DDRB
464 #define DDB3_REG DDRB
465 #define DDB4_REG DDRB
466 #define DDB5_REG DDRB
467 #define DDB6_REG DDRB
468 #define DDB7_REG DDRB
471 #define SPMEN_REG SPMCSR
472 #define PGERS_REG SPMCSR
473 #define PGWRT_REG SPMCSR
474 #define BLBSET_REG SPMCSR
475 #define RWWSRE_REG SPMCSR
476 #define RWWSB_REG SPMCSR
477 #define SPMIE_REG SPMCSR
480 #define WGM10_REG TCCR1A
481 #define WGM11_REG TCCR1A
482 #define COM1B0_REG TCCR1A
483 #define COM1B1_REG TCCR1A
484 #define COM1A0_REG TCCR1A
485 #define COM1A1_REG TCCR1A
488 #define FOC1B_REG TCCR1C
489 #define FOC1A_REG TCCR1C
492 #define CS10_REG TCCR1B
493 #define CS11_REG TCCR1B
494 #define CS12_REG TCCR1B
495 #define WGM12_REG TCCR1B
496 #define WGM13_REG TCCR1B
497 #define ICES1_REG TCCR1B
498 #define ICNC1_REG TCCR1B
501 #define CAL0_REG OSCCAL
502 #define CAL1_REG OSCCAL
503 #define CAL2_REG OSCCAL
504 #define CAL3_REG OSCCAL
505 #define CAL4_REG OSCCAL
506 #define CAL5_REG OSCCAL
507 #define CAL6_REG OSCCAL
510 #define OCR0RA_0_REG OCR0RAL
511 #define OCR0RA_1_REG OCR0RAL
512 #define OCR0RA_2_REG OCR0RAL
513 #define OCR0RA_3_REG OCR0RAL
514 #define OCR0RA_4_REG OCR0RAL
515 #define OCR0RA_5_REG OCR0RAL
516 #define OCR0RA_6_REG OCR0RAL
517 #define OCR0RA_7_REG OCR0RAL
520 #define DDD0_REG DDRD
521 #define DDD1_REG DDRD
522 #define DDD2_REG DDRD
523 #define DDD3_REG DDRD
524 #define DDD4_REG DDRD
525 #define DDD5_REG DDRD
526 #define DDD6_REG DDRD
527 #define DDD7_REG DDRD
530 #define GPIOR10_REG GPIOR1
531 #define GPIOR11_REG GPIOR1
532 #define GPIOR12_REG GPIOR1
533 #define GPIOR13_REG GPIOR1
534 #define GPIOR14_REG GPIOR1
535 #define GPIOR15_REG GPIOR1
536 #define GPIOR16_REG GPIOR1
537 #define GPIOR17_REG GPIOR1
540 #define GPIOR00_REG GPIOR0
541 #define GPIOR01_REG GPIOR0
542 #define GPIOR02_REG GPIOR0
543 #define GPIOR03_REG GPIOR0
544 #define GPIOR04_REG GPIOR0
545 #define GPIOR05_REG GPIOR0
546 #define GPIOR06_REG GPIOR0
547 #define GPIOR07_REG GPIOR0
550 #define GPIOR30_REG GPIOR3
551 #define GPIOR31_REG GPIOR3
552 #define GPIOR32_REG GPIOR3
553 #define GPIOR33_REG GPIOR3
554 #define GPIOR34_REG GPIOR3
555 #define GPIOR35_REG GPIOR3
556 #define GPIOR36_REG GPIOR3
557 #define GPIOR37_REG GPIOR3
560 #define GPIOR20_REG GPIOR2
561 #define GPIOR21_REG GPIOR2
562 #define GPIOR22_REG GPIOR2
563 #define GPIOR23_REG GPIOR2
564 #define GPIOR24_REG GPIOR2
565 #define GPIOR25_REG GPIOR2
566 #define GPIOR26_REG GPIOR2
567 #define GPIOR27_REG GPIOR2
570 #define ADCL0_REG ADCL
571 #define ADCL1_REG ADCL
572 #define ADCL2_REG ADCL
573 #define ADCL3_REG ADCL
574 #define ADCL4_REG ADCL
575 #define ADCL5_REG ADCL
576 #define ADCL6_REG ADCL
577 #define ADCL7_REG ADCL
580 #define DDE0_REG DDRE
581 #define DDE1_REG DDRE
582 #define DDE2_REG DDRE
585 #define TCNT0_0_REG TCNT0
586 #define TCNT0_1_REG TCNT0
587 #define TCNT0_2_REG TCNT0
588 #define TCNT0_3_REG TCNT0
589 #define TCNT0_4_REG TCNT0
590 #define TCNT0_5_REG TCNT0
591 #define TCNT0_6_REG TCNT0
592 #define TCNT0_7_REG TCNT0
595 #define CS00_REG TCCR0B
596 #define CS01_REG TCCR0B
597 #define CS02_REG TCCR0B
598 #define WGM02_REG TCCR0B
599 #define FOC0B_REG TCCR0B
600 #define FOC0A_REG TCCR0B
603 #define WGM00_REG TCCR0A
604 #define WGM01_REG TCCR0A
605 #define COM0B0_REG TCCR0A
606 #define COM0B1_REG TCCR0A
607 #define COM0A0_REG TCCR0A
608 #define COM0A1_REG TCCR0A
611 #define PRFM2B0_REG PFRC2B
612 #define PRFM2B1_REG PFRC2B
613 #define PRFM2B2_REG PFRC2B
614 #define PRFM2B3_REG PFRC2B
615 #define PFLTE2B_REG PFRC2B
616 #define PELEV2B_REG PFRC2B
617 #define PISEL2B_REG PFRC2B
618 #define PCAE2B_REG PFRC2B
621 #define PRFM2A0_REG PFRC2A
622 #define PRFM2A1_REG PFRC2A
623 #define PRFM2A2_REG PFRC2A
624 #define PRFM2A3_REG PFRC2A
625 #define PFLTE2A_REG PFRC2A
626 #define PELEV2A_REG PFRC2A
627 #define PISEL2A_REG PFRC2A
628 #define PCAE2A_REG PFRC2A
631 #define OCR2SA_0_REG OCR2SAL
632 #define OCR2SA_1_REG OCR2SAL
633 #define OCR2SA_2_REG OCR2SAL
634 #define OCR2SA_3_REG OCR2SAL
635 #define OCR2SA_4_REG OCR2SAL
636 #define OCR2SA_5_REG OCR2SAL
637 #define OCR2SA_6_REG OCR2SAL
638 #define OCR2SA_7_REG OCR2SAL
641 #define URxS0_REG EUCSRA
642 #define URxS1_REG EUCSRA
643 #define URxS2_REG EUCSRA
644 #define URxS3_REG EUCSRA
645 #define UTxS0_REG EUCSRA
646 #define UTxS1_REG EUCSRA
647 #define UTxS2_REG EUCSRA
648 #define UTxS3_REG EUCSRA
651 #define BODR_REG EUCSRB
652 #define EMCH_REG EUCSRB
653 #define EUSBS_REG EUCSRB
654 #define EUSART_REG EUCSRB
657 #define STP0_REG EUCSRC
658 #define STP1_REG EUCSRC
659 #define F1617_REG EUCSRC
660 #define FEM_REG EUCSRC
663 #define PRUN0_REG PCTL0
664 #define PCCYC0_REG PCTL0
665 #define PARUN0_REG PCTL0
666 #define PAOC0A_REG PCTL0
667 #define PAOC0B_REG PCTL0
668 #define PBFM0_REG PCTL0
669 #define PPRE00_REG PCTL0
670 #define PPRE01_REG PCTL0
673 #define PRUN1_REG PCTL1
674 #define PCCYC1_REG PCTL1
675 #define PARUN1_REG PCTL1
676 #define PAOC1A_REG PCTL1
677 #define PAOC1B_REG PCTL1
678 #define PBFM1_REG PCTL1
679 #define PPRE10_REG PCTL1
680 #define PPRE11_REG PCTL1
683 #define PRUN2_REG PCTL2
684 #define PCCYC2_REG PCTL2
685 #define PARUN2_REG PCTL2
686 #define PAOC2A_REG PCTL2
687 #define PAOC2B_REG PCTL2
688 #define PBFM2_REG PCTL2
689 #define PPRE20_REG PCTL2
690 #define PPRE21_REG PCTL2
693 #define SPR0_REG SPCR
694 #define SPR1_REG SPCR
695 #define CPHA_REG SPCR
696 #define CPOL_REG SPCR
697 #define MSTR_REG SPCR
698 #define DORD_REG SPCR
700 #define SPIE_REG SPCR
703 #define TOV1_REG TIFR1
704 #define OCF1A_REG TIFR1
705 #define OCF1B_REG TIFR1
706 #define ICF1_REG TIFR1
709 #define PSR10_REG GTCCR
710 #define ICPSEL1_REG GTCCR
711 #define TSM_REG GTCCR
712 #define PSRSYNC_REG GTCCR
725 #define POMV2A0_REG POM2
726 #define POMV2A1_REG POM2
727 #define POMV2A2_REG POM2
728 #define POMV2A3_REG POM2
729 #define POMV2B0_REG POM2
730 #define POMV2B1_REG POM2
731 #define POMV2B2_REG POM2
732 #define POMV2B3_REG POM2
735 #define OCR2RB_0_REG OCR2RBL
736 #define OCR2RB_1_REG OCR2RBL
737 #define OCR2RB_2_REG OCR2RBL
738 #define OCR2RB_3_REG OCR2RBL
739 #define OCR2RB_4_REG OCR2RBL
740 #define OCR2RB_5_REG OCR2RBL
741 #define OCR2RB_6_REG OCR2RBL
742 #define OCR2RB_7_REG OCR2RBL
745 #define PICR2_8_REG PICR2H
746 #define PICR2_9_REG PICR2H
747 #define PICR2_10_REG PICR2H
748 #define PICR2_11_REG PICR2H
749 #define PCST2_REG PICR2H
752 #define OCR2RB_8_REG OCR2RBH
753 #define OCR2RB_9_REG OCR2RBH
754 #define OCR2RB_10_REG OCR2RBH
755 #define OCR2RB_11_REG OCR2RBH
756 #define OCR2RB_12_REG OCR2RBH
757 #define OCR2RB_13_REG OCR2RBH
758 #define OCR2RB_14_REG OCR2RBH
759 #define OCR2RB_15_REG OCR2RBH
762 #define PICR2_0_REG PICR2L
763 #define PICR2_1_REG PICR2L
764 #define PICR2_2_REG PICR2L
765 #define PICR2_3_REG PICR2L
766 #define PICR2_4_REG PICR2L
767 #define PICR2_5_REG PICR2L
768 #define PICR2_6_REG PICR2L
769 #define PICR2_7_REG PICR2L
772 #define OCR1BL0_REG OCR1BL
773 #define OCR1BL1_REG OCR1BL
774 #define OCR1BL2_REG OCR1BL
775 #define OCR1BL3_REG OCR1BL
776 #define OCR1BL4_REG OCR1BL
777 #define OCR1BL5_REG OCR1BL
778 #define OCR1BL6_REG OCR1BL
779 #define OCR1BL7_REG OCR1BL
782 #define OCR1BH0_REG OCR1BH
783 #define OCR1BH1_REG OCR1BH
784 #define OCR1BH2_REG OCR1BH
785 #define OCR1BH3_REG OCR1BH
786 #define OCR1BH4_REG OCR1BH
787 #define OCR1BH5_REG OCR1BH
788 #define OCR1BH6_REG OCR1BH
789 #define OCR1BH7_REG OCR1BH
802 #define PORF_REG MCUSR
803 #define EXTRF_REG MCUSR
804 #define BORF_REG MCUSR
805 #define WDRF_REG MCUSR
808 #define EERE_REG EECR
809 #define EEWE_REG EECR
810 #define EEMWE_REG EECR
811 #define EERIE_REG EECR
820 #define PLOCK_REG PLLCSR
821 #define PLLE_REG PLLCSR
822 #define PLLF_REG PLLCSR
825 #define OCR2RA_8_REG OCR2RAH
826 #define OCR2RA_9_REG OCR2RAH
827 #define OCR2RA_10_REG OCR2RAH
828 #define OCR2RA_11_REG OCR2RAH
831 #define OCR2RA_0_REG OCR2RAL
832 #define OCR2RA_1_REG OCR2RAL
833 #define OCR2RA_2_REG OCR2RAL
834 #define OCR2RA_3_REG OCR2RAL
835 #define OCR2RA_4_REG OCR2RAL
836 #define OCR2RA_5_REG OCR2RAL
837 #define OCR2RA_6_REG OCR2RAL
838 #define OCR2RA_7_REG OCR2RAL
841 #define OCR0SA_0_REG OCR0SAL
842 #define OCR0SA_1_REG OCR0SAL
843 #define OCR0SA_2_REG OCR0SAL
844 #define OCR0SA_3_REG OCR0SAL
845 #define OCR0SA_4_REG OCR0SAL
846 #define OCR0SA_5_REG OCR0SAL
847 #define OCR0SA_6_REG OCR0SAL
848 #define OCR0SA_7_REG OCR0SAL
851 #define OCR0SA_8_REG OCR0SAH
852 #define OCR0SA_9_REG OCR0SAH
853 #define OCR0SA_00_REG OCR0SAH
854 #define OCR0SA_01_REG OCR0SAH
857 #define EEAR8_REG EEARH
858 #define EEAR9_REG EEARH
859 #define EEAR10_REG EEARH
860 #define EEAR11_REG EEARH
863 #define EEARL0_REG EEARL
864 #define EEARL1_REG EEARL
865 #define EEARL2_REG EEARL
866 #define EEARL3_REG EEARL
867 #define EEARL4_REG EEARL
868 #define EEARL5_REG EEARL
869 #define EEARL6_REG EEARL
870 #define EEARL7_REG EEARL
873 #define IVCE_REG MCUCR
874 #define IVSEL_REG MCUCR
875 #define PUD_REG MCUCR
876 #define SPIPS_REG MCUCR
879 #define PICR0_8_REG PICR0H
880 #define PICR0_9_REG PICR0H
881 #define PICR0_10_REG PICR0H
882 #define PICR0_11_REG PICR0H
883 #define PCST0_REG PICR0H
886 #define INTF0_REG EIFR
887 #define INTF1_REG EIFR
888 #define INTF2_REG EIFR
889 #define INTF3_REG EIFR
892 #define MUBRR0_REG MUBRRL
893 #define MUBRR1_REG MUBRRL
894 #define MUBRR2_REG MUBRRL
895 #define MUBRR3_REG MUBRRL
896 #define MUBRR4_REG MUBRRL
897 #define MUBRR5_REG MUBRRL
898 #define MUBRR6_REG MUBRRL
899 #define MUBRR7_REG MUBRRL
902 #define MUBRR8_REG MUBRRH
903 #define MUBRR9_REG MUBRRH
904 #define MUBRR10_REG MUBRRH
905 #define MUBRR11_REG MUBRRH
906 #define MUBRR12_REG MUBRRH
907 #define MUBRR13_REG MUBRRH
908 #define MUBRR14_REG MUBRRH
909 #define MUBRR15_REG MUBRRH
912 #define OCR2SA_8_REG OCR2SAH
913 #define OCR2SA_9_REG OCR2SAH
914 #define OCR2SA_10_REG OCR2SAH
915 #define OCR2SA_11_REG OCR2SAH
918 #define OCR0SB_0_REG OCR0SBL
919 #define OCR0SB_1_REG OCR0SBL
920 #define OCR0SB_2_REG OCR0SBL
921 #define OCR0SB_3_REG OCR0SBL
922 #define OCR0SB_4_REG OCR0SBL
923 #define OCR0SB_5_REG OCR0SBL
924 #define OCR0SB_6_REG OCR0SBL
925 #define OCR0SB_7_REG OCR0SBL
928 #define OCR0SB_8_REG OCR0SBH
929 #define OCR0SB_9_REG OCR0SBH
930 #define OCR0SB_00_REG OCR0SBH
931 #define OCR0SB_01_REG OCR0SBH
934 #define DDC0_REG DDRC
935 #define DDC1_REG DDRC
936 #define DDC2_REG DDRC
937 #define DDC3_REG DDRC
938 #define DDC4_REG DDRC
939 #define DDC5_REG DDRC
940 #define DDC6_REG DDRC
941 #define DDC7_REG DDRC
944 #define PRFM1B0_REG PFRC1B
945 #define PRFM1B1_REG PFRC1B
946 #define PRFM1B2_REG PFRC1B
947 #define PRFM1B3_REG PFRC1B
948 #define PFLTE1B_REG PFRC1B
949 #define PELEV1B_REG PFRC1B
950 #define PISEL1B_REG PFRC1B
951 #define PCAE1B_REG PFRC1B
954 #define PRFM1A0_REG PFRC1A
955 #define PRFM1A1_REG PFRC1A
956 #define PRFM1A2_REG PFRC1A
957 #define PRFM1A3_REG PFRC1A
958 #define PFLTE1A_REG PFRC1A
959 #define PELEV1A_REG PFRC1A
960 #define PISEL1A_REG PFRC1A
961 #define PCAE1A_REG PFRC1A
964 #define PICR0_0_REG PICR0L
965 #define PICR0_1_REG PICR0L
966 #define PICR0_2_REG PICR0L
967 #define PICR0_3_REG PICR0L
968 #define PICR0_4_REG PICR0L
969 #define PICR0_5_REG PICR0L
970 #define PICR0_6_REG PICR0L
971 #define PICR0_7_REG PICR0L
974 #define OCR1SA_0_REG OCR1SAL
975 #define OCR1SA_1_REG OCR1SAL
976 #define OCR1SA_2_REG OCR1SAL
977 #define OCR1SA_3_REG OCR1SAL
978 #define OCR1SA_4_REG OCR1SAL
979 #define OCR1SA_5_REG OCR1SAL
980 #define OCR1SA_6_REG OCR1SAL
981 #define OCR1SA_7_REG OCR1SAL
984 #define ADPS0_REG ADCSRA
985 #define ADPS1_REG ADCSRA
986 #define ADPS2_REG ADCSRA
987 #define ADIE_REG ADCSRA
988 #define ADIF_REG ADCSRA
989 #define ADATE_REG ADCSRA
990 #define ADSC_REG ADCSRA
991 #define ADEN_REG ADCSRA
994 #define POEN0A_REG PSOC0
995 #define POEN0B_REG PSOC0
996 #define PSYNC00_REG PSOC0
997 #define PSYNC01_REG PSOC0
1000 #define POEN1A_REG PSOC1
1001 #define POEN1B_REG PSOC1
1002 #define PSYNC1_0_REG PSOC1
1003 #define PSYNC1_1_REG PSOC1
1006 /* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */
1007 /* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */
1008 /* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */
1009 /* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */
1010 /* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */
1011 /* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */
1012 /* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */
1013 /* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */
1016 #define AC0O_REG ACSR
1017 #define AC1O_REG ACSR
1018 #define AC2O_REG ACSR
1019 #define AC0IF_REG ACSR
1020 #define AC1IF_REG ACSR
1021 #define AC2IF_REG ACSR
1022 #define ACCKDIV_REG ACSR
1025 #define OCR1RB_0_REG OCR1RBL
1026 #define OCR1RB_1_REG OCR1RBL
1027 #define OCR1RB_2_REG OCR1RBL
1028 #define OCR1RB_3_REG OCR1RBL
1029 #define OCR1RB_4_REG OCR1RBL
1030 #define OCR1RB_5_REG OCR1RBL
1031 #define OCR1RB_6_REG OCR1RBL
1032 #define OCR1RB_7_REG OCR1RBL
1035 #define OCR1SB_8_REG OCR1SBH
1036 #define OCR1SB_9_REG OCR1SBH
1037 #define OCR1SB_10_REG OCR1SBH
1038 #define OCR1SB_11_REG OCR1SBH
1041 #define OCR1RB_8_REG OCR1RBH
1042 #define OCR1RB_9_REG OCR1RBH
1043 #define OCR1RB_10_REG OCR1RBH
1044 #define OCR1RB_11_REG OCR1RBH
1045 #define OCR1RB_12_REG OCR1RBH
1046 #define OCR1RB_13_REG OCR1RBH
1047 #define OCR1RB_14_REG OCR1RBH
1048 #define OCR1RB_15_REG OCR1RBH
1051 #define OCR1SB_0_REG OCR1SBL
1052 #define OCR1SB_1_REG OCR1SBL
1053 #define OCR1SB_2_REG OCR1SBL
1054 #define OCR1SB_3_REG OCR1SBL
1055 #define OCR1SB_4_REG OCR1SBL
1056 #define OCR1SB_5_REG OCR1SBL
1057 #define OCR1SB_6_REG OCR1SBL
1058 #define OCR1SB_7_REG OCR1SBL
1061 #define OCR1SA_8_REG OCR1SAH
1062 #define OCR1SA_9_REG OCR1SAH
1063 #define OCR1SA_10_REG OCR1SAH
1064 #define OCR1SA_11_REG OCR1SAH
1067 #define UBRR8_REG UBRRH
1068 #define UBRR9_REG UBRRH
1069 #define UBRR10_REG UBRRH
1070 #define UBRR11_REG UBRRH
1073 #define DACL0_REG DACL
1074 #define DACL1_REG DACL
1075 #define DACL2_REG DACL
1076 #define DACL3_REG DACL
1077 #define DACL4_REG DACL
1078 #define DACL5_REG DACL
1079 #define DACL6_REG DACL
1080 #define DACL7_REG DACL
1083 #define UBRR0_REG UBRRL
1084 #define UBRR1_REG UBRRL
1085 #define UBRR2_REG UBRRL
1086 #define UBRR3_REG UBRRL
1087 #define UBRR4_REG UBRRL
1088 #define UBRR5_REG UBRRL
1089 #define UBRR6_REG UBRRL
1090 #define UBRR7_REG UBRRL
1093 #define DACH0_REG DACH
1094 #define DACH1_REG DACH
1095 #define DACH2_REG DACH
1096 #define DACH3_REG DACH
1097 #define DACH4_REG DACH
1098 #define DACH5_REG DACH
1099 #define DACH6_REG DACH
1100 #define DACH7_REG DACH
1103 #define OCR0RA_8_REG OCR0RAH
1104 #define OCR0RA_9_REG OCR0RAH
1105 #define OCR0RA_00_REG OCR0RAH
1106 #define OCR0RA_01_REG OCR0RAH
1109 #define PEOPE2_REG PIM2
1110 #define PEVE2A_REG PIM2
1111 #define PEVE2B_REG PIM2
1112 #define PSEIE2_REG PIM2
1115 #define PEOPE0_REG PIM0
1116 #define PEVE0A_REG PIM0
1117 #define PEVE0B_REG PIM0
1118 #define PSEIE0_REG PIM0
1121 #define PEOPE1_REG PIM1
1122 #define PEVE1A_REG PIM1
1123 #define PEVE1B_REG PIM1
1124 #define PSEIE1_REG PIM1
1127 #define PEOP2_REG PIFR2
1128 #define PRN20_REG PIFR2
1129 #define PRN21_REG PIFR2
1130 #define PEV2A_REG PIFR2
1131 #define PEV2B_REG PIFR2
1132 #define PSEI2_REG PIFR2
1133 #define POAC2A_REG PIFR2
1134 #define POAC2B_REG PIFR2
1137 #define PORTB0_REG PORTB
1138 #define PORTB1_REG PORTB
1139 #define PORTB2_REG PORTB
1140 #define PORTB3_REG PORTB
1141 #define PORTB4_REG PORTB
1142 #define PORTB5_REG PORTB
1143 #define PORTB6_REG PORTB
1144 #define PORTB7_REG PORTB
1147 #define PEOP0_REG PIFR0
1148 #define PRN00_REG PIFR0
1149 #define PRN01_REG PIFR0
1150 #define PEV0A_REG PIFR0
1151 #define PEV0B_REG PIFR0
1152 #define PSEI0_REG PIFR0
1153 #define POAC0A_REG PIFR0
1154 #define POAC0B_REG PIFR0
1157 #define PEOP1_REG PIFR1
1158 #define PRN10_REG PIFR1
1159 #define PRN11_REG PIFR1
1160 #define PEV1A_REG PIFR1
1161 #define PEV1B_REG PIFR1
1162 #define PSEI1_REG PIFR1
1163 #define POAC1A_REG PIFR1
1164 #define POAC1B_REG PIFR1
1167 #define ADCH0_REG ADCH
1168 #define ADCH1_REG ADCH
1169 #define ADCH2_REG ADCH
1170 #define ADCH3_REG ADCH
1171 #define ADCH4_REG ADCH
1172 #define ADCH5_REG ADCH
1173 #define ADCH6_REG ADCH
1174 #define ADCH7_REG ADCH
1177 #define POEN2A_REG PSOC2
1178 #define POEN2C_REG PSOC2
1179 #define POEN2B_REG PSOC2
1180 #define POEN2D_REG PSOC2
1181 #define PSYNC2_0_REG PSOC2
1182 #define PSYNC2_1_REG PSOC2
1183 #define POS22_REG PSOC2
1184 #define POS23_REG PSOC2
1187 #define TOIE0_REG TIMSK0
1188 #define OCIE0A_REG TIMSK0
1189 #define OCIE0B_REG TIMSK0
1192 #define TOIE1_REG TIMSK1
1193 #define OCIE1A_REG TIMSK1
1194 #define OCIE1B_REG TIMSK1
1195 #define ICIE1_REG TIMSK1
1198 #define AMP0TS0_REG AMP0CSR
1199 #define AMP0TS1_REG AMP0CSR
1200 #define AMP0G0_REG AMP0CSR
1201 #define AMP0G1_REG AMP0CSR
1202 #define AMP0IS_REG AMP0CSR
1203 #define AMP0EN_REG AMP0CSR
1206 #define UDR0_REG UDR
1207 #define UDR1_REG UDR
1208 #define UDR2_REG UDR
1209 #define UDR3_REG UDR
1210 #define UDR4_REG UDR
1211 #define UDR5_REG UDR
1212 #define UDR6_REG UDR
1213 #define UDR7_REG UDR
1216 #define DAEN_REG DACON
1217 #define DALA_REG DACON
1218 #define DATS0_REG DACON
1219 #define DATS1_REG DACON
1220 #define DATS2_REG DACON
1221 #define DAATE_REG DACON
1224 #define PINC0_REG PINC
1225 #define PINC1_REG PINC
1226 #define PINC2_REG PINC
1227 #define PINC3_REG PINC
1228 #define PINC4_REG PINC
1229 #define PINC5_REG PINC
1230 #define PINC6_REG PINC
1231 #define PINC7_REG PINC
1234 #define PINB0_REG PINB
1235 #define PINB1_REG PINB
1236 #define PINB2_REG PINB
1237 #define PINB3_REG PINB
1238 #define PINB4_REG PINB
1239 #define PINB5_REG PINB
1240 #define PINB6_REG PINB
1241 #define PINB7_REG PINB
1244 #define AC0M0_REG AC0CON
1245 #define AC0M1_REG AC0CON
1246 #define AC0M2_REG AC0CON
1247 #define AC0IS0_REG AC0CON
1248 #define AC0IS1_REG AC0CON
1249 #define AC0IE_REG AC0CON
1250 #define AC0EN_REG AC0CON
1253 #define ADTS0_REG ADCSRB
1254 #define ADTS1_REG ADCSRB
1255 #define ADTS2_REG ADCSRB
1256 #define ADTS3_REG ADCSRB
1257 #define ADASCR_REG ADCSRB
1258 #define ADHSM_REG ADCSRB
1261 #define PINE0_REG PINE
1262 #define PINE1_REG PINE
1263 #define PINE2_REG PINE
1266 #define PIND0_REG PIND
1267 #define PIND1_REG PIND
1268 #define PIND2_REG PIND
1269 #define PIND3_REG PIND
1270 #define PIND4_REG PIND
1271 #define PIND5_REG PIND
1272 #define PIND6_REG PIND
1273 #define PIND7_REG PIND
1276 #define OCR1AH0_REG OCR1AH
1277 #define OCR1AH1_REG OCR1AH
1278 #define OCR1AH2_REG OCR1AH
1279 #define OCR1AH3_REG OCR1AH
1280 #define OCR1AH4_REG OCR1AH
1281 #define OCR1AH5_REG OCR1AH
1282 #define OCR1AH6_REG OCR1AH
1283 #define OCR1AH7_REG OCR1AH
1286 #define OCR1AL0_REG OCR1AL
1287 #define OCR1AL1_REG OCR1AL
1288 #define OCR1AL2_REG OCR1AL
1289 #define OCR1AL3_REG OCR1AL
1290 #define OCR1AL4_REG OCR1AL
1291 #define OCR1AL5_REG OCR1AL
1292 #define OCR1AL6_REG OCR1AL
1293 #define OCR1AL7_REG OCR1AL
1296 #define TOV0_REG TIFR0
1297 #define OCF0A_REG TIFR0
1298 #define OCF0B_REG TIFR0
1301 #define MISO_PORT PORTB
1303 #define PSCOUT20_PORT PORTB
1304 #define PSCOUT20_BIT 0
1306 #define MOSI_PORT PORTB
1308 #define PSCOUT21_PORT PORTB
1309 #define PSCOUT21_BIT 1
1311 #define ADC5_PORT PORTB
1313 #define INT1_PORT PORTB
1316 #define AMP0-_PORT PORTB
1319 #define AMP0+_PORT PORTB
1322 #define ADC6_PORT PORTB
1324 #define INT2_PORT PORTB
1327 #define ADC7_PORT PORTB
1329 #define PSCOUT11_PORT PORTB
1330 #define PSCOUT11_BIT 6
1331 #define ICP1B_PORT PORTB
1334 #define ADC4_PORT PORTB
1336 #define PSCOUT01_PORT PORTB
1337 #define PSCOUT01_BIT 7
1338 #define SCK_PORT PORTB
1341 #define INT3_PORT PORTC
1343 #define PSCOUT10_PORT PORTC
1344 #define PSCOUT10_BIT 0
1346 #define PSCIN1_PORT PORTC
1347 #define PSCIN1_BIT 1
1348 #define OC1B_PORT PORTC
1351 #define T0_PORT PORTC
1353 #define PSCOUT22_PORT PORTC
1354 #define PSCOUT22_BIT 2
1356 #define T1_PORT PORTC
1358 #define PSCOUT23_PORT PORTC
1359 #define PSCOUT23_BIT 3
1361 #define ADC8_PORT PORTC
1363 #define AMP1-_PORT PORTC
1366 #define ADC9_PORT PORTC
1368 #define AMP1+_PORT PORTC
1371 #define ADC10_PORT PORTC
1373 #define ACMP1_PORT PORTC
1376 #define D2A_PORT PORTC
1379 #define PSCOUT00_PORT PORTD
1380 #define PSCOUT00_BIT 0
1381 #define XCK_PORT PORTD
1383 #define SSA_PORT PORTD
1386 #define PSCIN0_PORT PORTD
1387 #define PSCIN0_BIT 1
1388 #define CLK0_PORT PORTD
1391 #define PSCIN2_PORT PORTD
1392 #define PSCIN2_BIT 2
1393 #define OC1A_PORT PORTD
1395 #define MISO_A_PORT PORTD
1396 #define MISO_A_BIT 2
1398 #define TXD_PORT PORTD
1400 #define DALI_PORT PORTD
1402 #define OC0A_PORT PORTD
1404 #define SS_PORT PORTD
1406 #define MOSI_A_PORT PORTD
1407 #define MOSI_A_BIT 3
1409 #define ADC1_PORT PORTD
1411 #define RXD_PORT PORTD
1413 #define DALI_PORT PORTD
1415 #define ICP1_PORT PORTD
1417 #define SCK_A_PORT PORTD
1420 #define ADC2_PORT PORTD
1422 #define ACOMP2_PORT PORTD
1423 #define ACOMP2_BIT 5
1425 #define ADC3_PORT PORTD
1427 #define ACMPM_PORT PORTD
1429 #define INT0_PORT PORTD
1432 #define ACMP0_PORT PORTD
1435 #define RESET_PORT PORTE
1437 #define OCD_PORT PORTE
1440 #define OC0B_PORT PORTE
1442 #define XTAL1_PORT PORTE
1445 #define ADC0_PORT PORTE
1447 #define XTAL2_PORT PORTE