2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_8 2
50 #define TIMER1_PRESCALER_DIV_64 3
51 #define TIMER1_PRESCALER_DIV_256 4
52 #define TIMER1_PRESCALER_DIV_1024 5
53 #define TIMER1_PRESCALER_DIV_FALL 6
54 #define TIMER1_PRESCALER_DIV_RISE 7
56 #define TIMER1_PRESCALER_REG_0 0
57 #define TIMER1_PRESCALER_REG_1 1
58 #define TIMER1_PRESCALER_REG_2 8
59 #define TIMER1_PRESCALER_REG_3 64
60 #define TIMER1_PRESCALER_REG_4 256
61 #define TIMER1_PRESCALER_REG_5 1024
62 #define TIMER1_PRESCALER_REG_6 -1
63 #define TIMER1_PRESCALER_REG_7 -2
65 /* prescalers timer 2 */
66 #define TIMER2_PRESCALER_DIV_0 0
67 #define TIMER2_PRESCALER_DIV_1 1
68 #define TIMER2_PRESCALER_DIV_8 2
69 #define TIMER2_PRESCALER_DIV_32 3
70 #define TIMER2_PRESCALER_DIV_64 4
71 #define TIMER2_PRESCALER_DIV_128 5
72 #define TIMER2_PRESCALER_DIV_256 6
73 #define TIMER2_PRESCALER_DIV_1024 7
75 #define TIMER2_PRESCALER_REG_0 0
76 #define TIMER2_PRESCALER_REG_1 1
77 #define TIMER2_PRESCALER_REG_2 8
78 #define TIMER2_PRESCALER_REG_3 32
79 #define TIMER2_PRESCALER_REG_4 64
80 #define TIMER2_PRESCALER_REG_5 128
81 #define TIMER2_PRESCALER_REG_6 256
82 #define TIMER2_PRESCALER_REG_7 1024
84 /* prescalers timer 3 */
85 #define TIMER3_PRESCALER_DIV_0 0
86 #define TIMER3_PRESCALER_DIV_1 1
87 #define TIMER3_PRESCALER_DIV_8 2
88 #define TIMER3_PRESCALER_DIV_64 3
89 #define TIMER3_PRESCALER_DIV_256 4
90 #define TIMER3_PRESCALER_DIV_1024 5
91 #define TIMER3_PRESCALER_DIV_16 6
92 #define TIMER3_PRESCALER_DIV_32 7
94 #define TIMER3_PRESCALER_REG_0 0
95 #define TIMER3_PRESCALER_REG_1 1
96 #define TIMER3_PRESCALER_REG_2 8
97 #define TIMER3_PRESCALER_REG_3 64
98 #define TIMER3_PRESCALER_REG_4 256
99 #define TIMER3_PRESCALER_REG_5 1024
100 #define TIMER3_PRESCALER_REG_6 16
101 #define TIMER3_PRESCALER_REG_7 32
104 /* available timers */
105 #define TIMER0_AVAILABLE
106 #define TIMER1_AVAILABLE
107 #define TIMER1A_AVAILABLE
108 #define TIMER1B_AVAILABLE
109 #define TIMER2_AVAILABLE
110 #define TIMER3_AVAILABLE
111 #define TIMER3A_AVAILABLE
112 #define TIMER3B_AVAILABLE
114 /* overflow interrupt number */
115 #define SIG_OVERFLOW0_NUM 0
116 #define SIG_OVERFLOW1_NUM 1
117 #define SIG_OVERFLOW2_NUM 2
118 #define SIG_OVERFLOW3_NUM 3
119 #define SIG_OVERFLOW_TOTAL_NUM 4
121 /* output compare interrupt number */
122 #define SIG_OUTPUT_COMPARE0_NUM 0
123 #define SIG_OUTPUT_COMPARE1A_NUM 1
124 #define SIG_OUTPUT_COMPARE1B_NUM 2
125 #define SIG_OUTPUT_COMPARE2_NUM 3
126 #define SIG_OUTPUT_COMPARE3A_NUM 4
127 #define SIG_OUTPUT_COMPARE3B_NUM 5
128 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 6
137 #define PWM_TOTAL_NUM 6
139 /* input capture interrupt number */
140 #define SIG_INPUT_CAPTURE1_NUM 0
141 #define SIG_INPUT_CAPTURE3_NUM 1
142 #define SIG_INPUT_CAPTURE_TOTAL_NUM 2
146 #define SPDR0_REG SPDR
147 #define SPDR1_REG SPDR
148 #define SPDR2_REG SPDR
149 #define SPDR3_REG SPDR
150 #define SPDR4_REG SPDR
151 #define SPDR5_REG SPDR
152 #define SPDR6_REG SPDR
153 #define SPDR7_REG SPDR
156 #define CLKPS0_REG CLKPR
157 #define CLKPS1_REG CLKPR
158 #define CLKPS2_REG CLKPR
159 #define CLKPS3_REG CLKPR
160 #define CLKPCE_REG CLKPR
163 #define WDP0_REG WDTCR
164 #define WDP1_REG WDTCR
165 #define WDP2_REG WDTCR
166 #define WDE_REG WDTCR
167 #define WDCE_REG WDTCR
170 #define ICR1H0_REG ICR1H
171 #define ICR1H1_REG ICR1H
172 #define ICR1H2_REG ICR1H
173 #define ICR1H3_REG ICR1H
174 #define ICR1H4_REG ICR1H
175 #define ICR1H5_REG ICR1H
176 #define ICR1H6_REG ICR1H
177 #define ICR1H7_REG ICR1H
180 #define TXB81_REG UCSR1B
181 #define RXB81_REG UCSR1B
182 #define UCSZ12_REG UCSR1B
183 #define TXEN1_REG UCSR1B
184 #define RXEN1_REG UCSR1B
185 #define UDRIE1_REG UCSR1B
186 #define TXCIE1_REG UCSR1B
187 #define RXCIE1_REG UCSR1B
190 #define UCPOL1_REG UCSR1C
191 #define UCSZ10_REG UCSR1C
192 #define UCSZ11_REG UCSR1C
193 #define USBS1_REG UCSR1C
194 #define UPM10_REG UCSR1C
195 #define UPM11_REG UCSR1C
196 #define UMSEL1_REG UCSR1C
197 #define URSEL1_REG UCSR1C
200 #define MPCM1_REG UCSR1A
201 #define U2X1_REG UCSR1A
202 #define UPE1_REG UCSR1A
203 #define DOR1_REG UCSR1A
204 #define FE1_REG UCSR1A
205 #define UDRE1_REG UCSR1A
206 #define TXC1_REG UCSR1A
207 #define RXC1_REG UCSR1A
210 #define CS00_REG TCCR0
211 #define CS01_REG TCCR0
212 #define CS02_REG TCCR0
213 #define WGM01_REG TCCR0
214 #define COM00_REG TCCR0
215 #define COM01_REG TCCR0
216 #define WGM00_REG TCCR0
217 #define FOC0_REG TCCR0
230 #define DDB0_REG DDRB
231 #define DDB1_REG DDRB
232 #define DDB2_REG DDRB
233 #define DDB3_REG DDRB
234 #define DDB4_REG DDRB
235 #define DDB5_REG DDRB
236 #define DDB6_REG DDRB
237 #define DDB7_REG DDRB
240 #define IVCE_REG GICR
241 #define IVSEL_REG GICR
242 #define PCIE0_REG GICR
243 #define PCIE1_REG GICR
244 #define INT2_REG GICR
245 #define INT0_REG GICR
246 #define INT1_REG GICR
249 #define SPI2X_REG SPSR
250 #define WCOL_REG SPSR
251 #define SPIF_REG SPSR
254 #define DDC0_REG DDRC
255 #define DDC1_REG DDRC
256 #define DDC2_REG DDRC
257 #define DDC3_REG DDRC
258 #define DDC4_REG DDRC
259 #define DDC5_REG DDRC
260 #define DDC6_REG DDRC
261 #define DDC7_REG DDRC
264 #define EEDR0_REG EEDR
265 #define EEDR1_REG EEDR
266 #define EEDR2_REG EEDR
267 #define EEDR3_REG EEDR
268 #define EEDR4_REG EEDR
269 #define EEDR5_REG EEDR
270 #define EEDR6_REG EEDR
271 #define EEDR7_REG EEDR
274 #define TOIE3_REG ETIMSK
275 #define OCIE3B_REG ETIMSK
276 #define OCIE3A_REG ETIMSK
277 #define TICIE3_REG ETIMSK
280 #define OCR3AL0_REG OCR3AL
281 #define OCR3AL1_REG OCR3AL
282 #define OCR3AL2_REG OCR3AL
283 #define OCR3AL3_REG OCR3AL
284 #define OCR3AL4_REG OCR3AL
285 #define OCR3AL5_REG OCR3AL
286 #define OCR3AL6_REG OCR3AL
287 #define OCR3AL7_REG OCR3AL
290 #define DDA0_REG DDRA
291 #define DDA1_REG DDRA
292 #define DDA2_REG DDRA
293 #define DDA3_REG DDRA
294 #define DDA4_REG DDRA
295 #define DDA5_REG DDRA
296 #define DDA6_REG DDRA
297 #define DDA7_REG DDRA
300 /* #define UBRR8_REG UBRR1H */ /* dup in UBRR0H */
301 /* #define UBRR9_REG UBRR1H */ /* dup in UBRR0H */
302 /* #define UBRR10_REG UBRR1H */ /* dup in UBRR0H */
303 /* #define UBRR11_REG UBRR1H */ /* dup in UBRR0H */
306 #define OCR3AH0_REG OCR3AH
307 #define OCR3AH1_REG OCR3AH
308 #define OCR3AH2_REG OCR3AH
309 #define OCR3AH3_REG OCR3AH
310 #define OCR3AH4_REG OCR3AH
311 #define OCR3AH5_REG OCR3AH
312 #define OCR3AH6_REG OCR3AH
313 #define OCR3AH7_REG OCR3AH
316 #define CS10_REG TCCR1B
317 #define CS11_REG TCCR1B
318 #define CS12_REG TCCR1B
319 #define WGM12_REG TCCR1B
320 #define WGM13_REG TCCR1B
321 #define ICES1_REG TCCR1B
322 #define ICNC1_REG TCCR1B
325 #define PCIF0_REG GIFR
326 #define PCIF1_REG GIFR
327 #define INTF2_REG GIFR
328 #define INTF0_REG GIFR
329 #define INTF1_REG GIFR
332 #define TICIE1_REG TIMSK
333 #define OCIE1B_REG TIMSK
334 #define OCIE1A_REG TIMSK
335 #define TOIE1_REG TIMSK
336 #define TOIE2_REG TIMSK
337 #define OCIE2_REG TIMSK
338 #define OCIE0_REG TIMSK
339 #define TOIE0_REG TIMSK
342 /* #define UBRR8_REG UBRR0H */ /* dup in UBRR1H */
343 /* #define UBRR9_REG UBRR0H */ /* dup in UBRR1H */
344 /* #define UBRR10_REG UBRR0H */ /* dup in UBRR1H */
345 /* #define UBRR11_REG UBRR0H */ /* dup in UBRR1H */
346 /* #define URSEL0_REG UBRR0H */ /* dup in UCSR0C */
349 #define CS30_REG TCCR3B
350 #define CS31_REG TCCR3B
351 #define CS32_REG TCCR3B
352 #define WGM32_REG TCCR3B
353 #define WGM33_REG TCCR3B
354 #define ICES3_REG TCCR3B
355 #define ICNC3_REG TCCR3B
358 #define WGM30_REG TCCR3A
359 #define WGM31_REG TCCR3A
360 #define FOC3B_REG TCCR3A
361 #define FOC3A_REG TCCR3A
362 #define COM3B0_REG TCCR3A
363 #define COM3B1_REG TCCR3A
364 #define COM3A0_REG TCCR3A
365 #define COM3A1_REG TCCR3A
368 #define WGM10_REG TCCR1A
369 #define WGM11_REG TCCR1A
370 #define FOC1B_REG TCCR1A
371 #define FOC1A_REG TCCR1A
372 #define COM1B0_REG TCCR1A
373 #define COM1B1_REG TCCR1A
374 #define COM1A0_REG TCCR1A
375 #define COM1A1_REG TCCR1A
378 #define ICR1L0_REG ICR1L
379 #define ICR1L1_REG ICR1L
380 #define ICR1L2_REG ICR1L
381 #define ICR1L3_REG ICR1L
382 #define ICR1L4_REG ICR1L
383 #define ICR1L5_REG ICR1L
384 #define ICR1L6_REG ICR1L
385 #define ICR1L7_REG ICR1L
388 #define PSR310_REG SFIOR
389 #define PSR2_REG SFIOR
390 #define PUD_REG SFIOR
391 #define XMM0_REG SFIOR
392 #define XMM1_REG SFIOR
393 #define XMM2_REG SFIOR
394 #define XMBK_REG SFIOR
395 #define TSM_REG SFIOR
398 #define UDR0_0_REG UDR0
399 #define UDR0_1_REG UDR0
400 #define UDR0_2_REG UDR0
401 #define UDR0_3_REG UDR0
402 #define UDR0_4_REG UDR0
403 #define UDR0_5_REG UDR0
404 #define UDR0_6_REG UDR0
405 #define UDR0_7_REG UDR0
418 #define OCR1BL0_REG OCR1BL
419 #define OCR1BL1_REG OCR1BL
420 #define OCR1BL2_REG OCR1BL
421 #define OCR1BL3_REG OCR1BL
422 #define OCR1BL4_REG OCR1BL
423 #define OCR1BL5_REG OCR1BL
424 #define OCR1BL6_REG OCR1BL
425 #define OCR1BL7_REG OCR1BL
428 #define TCNT3H0_REG TCNT3H
429 #define TCNT3H1_REG TCNT3H
430 #define TCNT3H2_REG TCNT3H
431 #define TCNT3H3_REG TCNT3H
432 #define TCNT3H4_REG TCNT3H
433 #define TCNT3H5_REG TCNT3H
434 #define TCNT3H6_REG TCNT3H
435 #define TCNT3H7_REG TCNT3H
438 #define ISC2_REG EMCUCR
439 #define SRW11_REG EMCUCR
440 #define SRW00_REG EMCUCR
441 #define SRW01_REG EMCUCR
442 #define SRL0_REG EMCUCR
443 #define SRL1_REG EMCUCR
444 #define SRL2_REG EMCUCR
445 #define SM0_REG EMCUCR
458 #define OCR1BH0_REG OCR1BH
459 #define OCR1BH1_REG OCR1BH
460 #define OCR1BH2_REG OCR1BH
461 #define OCR1BH3_REG OCR1BH
462 #define OCR1BH4_REG OCR1BH
463 #define OCR1BH5_REG OCR1BH
464 #define OCR1BH6_REG OCR1BH
465 #define OCR1BH7_REG OCR1BH
468 #define TCNT3L0_REG TCNT3L
469 #define TCNT3L1_REG TCNT3L
470 #define TCNT3L2_REG TCNT3L
471 #define TCNT3L3_REG TCNT3L
472 #define TCNT3L4_REG TCNT3L
473 #define TCNT3L5_REG TCNT3L
474 #define TCNT3L6_REG TCNT3L
475 #define TCNT3L7_REG TCNT3L
478 #define PIND0_REG PIND
479 #define PIND1_REG PIND
480 #define PIND2_REG PIND
481 #define PIND3_REG PIND
482 #define PIND4_REG PIND
483 #define PIND5_REG PIND
484 #define PIND6_REG PIND
485 #define PIND7_REG PIND
488 #define DDD0_REG DDRD
489 #define DDD1_REG DDRD
490 #define DDD2_REG DDRD
491 #define DDD3_REG DDRD
492 #define DDD4_REG DDRD
493 #define DDD5_REG DDRD
494 #define DDD6_REG DDRD
495 #define DDD7_REG DDRD
498 #define SPMEN_REG SPMCR
499 #define PGERS_REG SPMCR
500 #define PGWRT_REG SPMCR
501 #define BLBSET_REG SPMCR
502 #define RWWSRE_REG SPMCR
503 #define RWWSB_REG SPMCR
504 #define SPMIE_REG SPMCR
507 #define ICR3H0_REG ICR3H
508 #define ICR3H1_REG ICR3H
509 #define ICR3H2_REG ICR3H
510 #define ICR3H3_REG ICR3H
511 #define ICR3H4_REG ICR3H
512 #define ICR3H5_REG ICR3H
513 #define ICR3H6_REG ICR3H
514 #define ICR3H7_REG ICR3H
517 #define DDE0_REG DDRE
518 #define DDE1_REG DDRE
519 #define DDE2_REG DDRE
522 #define PORTD0_REG PORTD
523 #define PORTD1_REG PORTD
524 #define PORTD2_REG PORTD
525 #define PORTD3_REG PORTD
526 #define PORTD4_REG PORTD
527 #define PORTD5_REG PORTD
528 #define PORTD6_REG PORTD
529 #define PORTD7_REG PORTD
532 #define ICR3L0_REG ICR3L
533 #define ICR3L1_REG ICR3L
534 #define ICR3L2_REG ICR3L
535 #define ICR3L3_REG ICR3L
536 #define ICR3L4_REG ICR3L
537 #define ICR3L5_REG ICR3L
538 #define ICR3L6_REG ICR3L
539 #define ICR3L7_REG ICR3L
542 #define ACIS0_REG ACSR
543 #define ACIS1_REG ACSR
544 #define ACIC_REG ACSR
545 #define ACIE_REG ACSR
548 #define ACBG_REG ACSR
552 #define EERE_REG EECR
553 #define EEWE_REG EECR
554 #define EEMWE_REG EECR
555 #define EERIE_REG EECR
558 #define PORTE0_REG PORTE
559 #define PORTE1_REG PORTE
560 #define PORTE2_REG PORTE
563 #define CAL0_REG OSCCAL
564 #define CAL1_REG OSCCAL
565 #define CAL2_REG OSCCAL
566 #define CAL3_REG OSCCAL
567 #define CAL4_REG OSCCAL
568 #define CAL5_REG OSCCAL
569 #define CAL6_REG OSCCAL
572 #define TCNT1L0_REG TCNT1L
573 #define TCNT1L1_REG TCNT1L
574 #define TCNT1L2_REG TCNT1L
575 #define TCNT1L3_REG TCNT1L
576 #define TCNT1L4_REG TCNT1L
577 #define TCNT1L5_REG TCNT1L
578 #define TCNT1L6_REG TCNT1L
579 #define TCNT1L7_REG TCNT1L
582 #define PORTB0_REG PORTB
583 #define PORTB1_REG PORTB
584 #define PORTB2_REG PORTB
585 #define PORTB3_REG PORTB
586 #define PORTB4_REG PORTB
587 #define PORTB5_REG PORTB
588 #define PORTB6_REG PORTB
589 #define PORTB7_REG PORTB
592 #define UCPOL0_REG UCSR0C
593 #define UCSZ00_REG UCSR0C
594 #define UCSZ01_REG UCSR0C
595 #define USBS0_REG UCSR0C
596 #define UPM00_REG UCSR0C
597 #define UPM01_REG UCSR0C
598 #define UMSEL0_REG UCSR0C
599 /* #define URSEL0_REG UCSR0C */ /* dup in UBRR0H */
602 #define TXB80_REG UCSR0B
603 #define RXB80_REG UCSR0B
604 #define UCSZ02_REG UCSR0B
605 #define TXEN0_REG UCSR0B
606 #define RXEN0_REG UCSR0B
607 #define UDRIE0_REG UCSR0B
608 #define TXCIE0_REG UCSR0B
609 #define RXCIE0_REG UCSR0B
612 #define TCNT1H0_REG TCNT1H
613 #define TCNT1H1_REG TCNT1H
614 #define TCNT1H2_REG TCNT1H
615 #define TCNT1H3_REG TCNT1H
616 #define TCNT1H4_REG TCNT1H
617 #define TCNT1H5_REG TCNT1H
618 #define TCNT1H6_REG TCNT1H
619 #define TCNT1H7_REG TCNT1H
622 #define PORTC0_REG PORTC
623 #define PORTC1_REG PORTC
624 #define PORTC2_REG PORTC
625 #define PORTC3_REG PORTC
626 #define PORTC4_REG PORTC
627 #define PORTC5_REG PORTC
628 #define PORTC6_REG PORTC
629 #define PORTC7_REG PORTC
632 #define PORTA0_REG PORTA
633 #define PORTA1_REG PORTA
634 #define PORTA2_REG PORTA
635 #define PORTA3_REG PORTA
636 #define PORTA4_REG PORTA
637 #define PORTA5_REG PORTA
638 #define PORTA6_REG PORTA
639 #define PORTA7_REG PORTA
642 #define TCNT2_0_REG TCNT2
643 #define TCNT2_1_REG TCNT2
644 #define TCNT2_2_REG TCNT2
645 #define TCNT2_3_REG TCNT2
646 #define TCNT2_4_REG TCNT2
647 #define TCNT2_5_REG TCNT2
648 #define TCNT2_6_REG TCNT2
649 #define TCNT2_7_REG TCNT2
652 #define TCNT0_0_REG TCNT0
653 #define TCNT0_1_REG TCNT0
654 #define TCNT0_2_REG TCNT0
655 #define TCNT0_3_REG TCNT0
656 #define TCNT0_4_REG TCNT0
657 #define TCNT0_5_REG TCNT0
658 #define TCNT0_6_REG TCNT0
659 #define TCNT0_7_REG TCNT0
662 #define OCR3BL0_REG OCR3BL
663 #define OCR3BL1_REG OCR3BL
664 #define OCR3BL2_REG OCR3BL
665 #define OCR3BL3_REG OCR3BL
666 #define OCR3BL4_REG OCR3BL
667 #define OCR3BL5_REG OCR3BL
668 #define OCR3BL6_REG OCR3BL
669 #define OCR3BL7_REG OCR3BL
672 #define PORF_REG MCUCSR
673 #define EXTRF_REG MCUCSR
674 #define BORF_REG MCUCSR
675 #define WDRF_REG MCUCSR
676 #define JTRF_REG MCUCSR
677 #define SM2_REG MCUCSR
678 #define JDT_REG MCUCSR
679 #define JTD_REG MCUCSR
682 #define OCR3BH0_REG OCR3BH
683 #define OCR3BH1_REG OCR3BH
684 #define OCR3BH2_REG OCR3BH
685 #define OCR3BH3_REG OCR3BH
686 #define OCR3BH4_REG OCR3BH
687 #define OCR3BH5_REG OCR3BH
688 #define OCR3BH6_REG OCR3BH
689 #define OCR3BH7_REG OCR3BH
692 #define MPCM0_REG UCSR0A
693 #define U2X0_REG UCSR0A
694 #define UPE0_REG UCSR0A
695 #define DOR0_REG UCSR0A
696 #define FE0_REG UCSR0A
697 #define UDRE0_REG UCSR0A
698 #define TXC0_REG UCSR0A
699 #define RXC0_REG UCSR0A
702 #define EEAR0_REG EEARL
703 #define EEAR1_REG EEARL
704 #define EEAR2_REG EEARL
705 #define EEAR3_REG EEARL
706 #define EEAR4_REG EEARL
707 #define EEAR5_REG EEARL
708 #define EEAR6_REG EEARL
709 #define EEAR7_REG EEARL
712 #define UBRR1L0_REG UBRR1L
713 #define UBRR1L1_REG UBRR1L
714 #define UBRR1L2_REG UBRR1L
715 #define UBRR1L3_REG UBRR1L
716 #define UBRR1L4_REG UBRR1L
717 #define UBRR1L5_REG UBRR1L
718 #define UBRR1L6_REG UBRR1L
719 #define UBRR1L7_REG UBRR1L
722 #define CS20_REG TCCR2
723 #define CS21_REG TCCR2
724 #define CS22_REG TCCR2
725 #define WGM21_REG TCCR2
726 #define COM20_REG TCCR2
727 #define COM21_REG TCCR2
728 #define WGM20_REG TCCR2
729 #define FOC2_REG TCCR2
732 #define UDR1_0_REG UDR1
733 #define UDR1_1_REG UDR1
734 #define UDR1_2_REG UDR1
735 #define UDR1_3_REG UDR1
736 #define UDR1_4_REG UDR1
737 #define UDR1_5_REG UDR1
738 #define UDR1_6_REG UDR1
739 #define UDR1_7_REG UDR1
742 #define ICF1_REG TIFR
743 #define OCF1B_REG TIFR
744 #define OCF1A_REG TIFR
745 #define TOV1_REG TIFR
746 #define TOV2_REG TIFR
747 #define OCF2_REG TIFR
748 #define OCF0_REG TIFR
749 #define TOV0_REG TIFR
752 #define UBRR0_REG UBRR0L
753 #define UBRR1_REG UBRR0L
754 #define UBRR2_REG UBRR0L
755 #define UBRR3_REG UBRR0L
756 #define UBRR4_REG UBRR0L
757 #define UBRR5_REG UBRR0L
758 #define UBRR6_REG UBRR0L
759 #define UBRR7_REG UBRR0L
762 #define EEAR8_REG EEARH
765 #define OCDR0_REG OCDR
766 #define OCDR1_REG OCDR
767 #define OCDR2_REG OCDR
768 #define OCDR3_REG OCDR
769 #define OCDR4_REG OCDR
770 #define OCDR5_REG OCDR
771 #define OCDR6_REG OCDR
772 #define OCDR7_REG OCDR
775 #define PCINT0_REG PCMSK0
776 #define PCINT1_REG PCMSK0
777 #define PCINT2_REG PCMSK0
778 #define PCINT3_REG PCMSK0
779 #define PCINT4_REG PCMSK0
780 #define PCINT5_REG PCMSK0
781 #define PCINT6_REG PCMSK0
782 #define PCINT7_REG PCMSK0
785 #define PCINT8_REG PCMSK1
786 #define PCINT9_REG PCMSK1
787 #define PCINT10_REG PCMSK1
788 #define PCINT11_REG PCMSK1
789 #define PCINT12_REG PCMSK1
790 #define PCINT13_REG PCMSK1
791 #define PCINT14_REG PCMSK1
792 #define PCINT15_REG PCMSK1
795 #define PINC0_REG PINC
796 #define PINC1_REG PINC
797 #define PINC2_REG PINC
798 #define PINC3_REG PINC
799 #define PINC4_REG PINC
800 #define PINC5_REG PINC
801 #define PINC6_REG PINC
802 #define PINC7_REG PINC
805 #define PINB0_REG PINB
806 #define PINB1_REG PINB
807 #define PINB2_REG PINB
808 #define PINB3_REG PINB
809 #define PINB4_REG PINB
810 #define PINB5_REG PINB
811 #define PINB6_REG PINB
812 #define PINB7_REG PINB
815 #define PINA0_REG PINA
816 #define PINA1_REG PINA
817 #define PINA2_REG PINA
818 #define PINA3_REG PINA
819 #define PINA4_REG PINA
820 #define PINA5_REG PINA
821 #define PINA6_REG PINA
822 #define PINA7_REG PINA
825 #define PINE0_REG PINE
826 #define PINE1_REG PINE
827 #define PINE2_REG PINE
828 #define PINE3_REG PINE
831 #define ISC00_REG MCUCR
832 #define ISC01_REG MCUCR
833 #define ISC10_REG MCUCR
834 #define ISC11_REG MCUCR
835 #define SM1_REG MCUCR
837 #define SRW10_REG MCUCR
838 #define SRE_REG MCUCR
841 #define OCR1AH0_REG OCR1AH
842 #define OCR1AH1_REG OCR1AH
843 #define OCR1AH2_REG OCR1AH
844 #define OCR1AH3_REG OCR1AH
845 #define OCR1AH4_REG OCR1AH
846 #define OCR1AH5_REG OCR1AH
847 #define OCR1AH6_REG OCR1AH
848 #define OCR1AH7_REG OCR1AH
851 #define OCR1AL0_REG OCR1AL
852 #define OCR1AL1_REG OCR1AL
853 #define OCR1AL2_REG OCR1AL
854 #define OCR1AL3_REG OCR1AL
855 #define OCR1AL4_REG OCR1AL
856 #define OCR1AL5_REG OCR1AL
857 #define OCR1AL6_REG OCR1AL
858 #define OCR1AL7_REG OCR1AL
861 #define SPR0_REG SPCR
862 #define SPR1_REG SPCR
863 #define CPHA_REG SPCR
864 #define CPOL_REG SPCR
865 #define MSTR_REG SPCR
866 #define DORD_REG SPCR
868 #define SPIE_REG SPCR
871 #define OCR0_0_REG OCR0
872 #define OCR0_1_REG OCR0
873 #define OCR0_2_REG OCR0
874 #define OCR0_3_REG OCR0
875 #define OCR0_4_REG OCR0
876 #define OCR0_5_REG OCR0
877 #define OCR0_6_REG OCR0
878 #define OCR0_7_REG OCR0
881 #define TOV3_REG ETIFR
882 #define OCF3B_REG ETIFR
883 #define OCF3A_REG ETIFR
884 #define ICF3_REG ETIFR
887 #define OCR2_0_REG OCR2
888 #define OCR2_1_REG OCR2
889 #define OCR2_2_REG OCR2
890 #define OCR2_3_REG OCR2
891 #define OCR2_4_REG OCR2
892 #define OCR2_5_REG OCR2
893 #define OCR2_6_REG OCR2
894 #define OCR2_7_REG OCR2
897 #define TCR2UB_REG ASSR
898 #define OCR2UB_REG ASSR
899 #define TCN2UB_REG ASSR
903 #define PCINT0_PORT PORTA
905 #define AD0_PORT PORTA
908 #define PCINT1_PORT PORTA
910 #define AD1_PORT PORTA
913 #define PCINT2_PORT PORTA
915 #define AD2_PORT PORTA
918 #define PCINT3_PORT PORTA
920 #define AD3_PORT PORTA
923 #define PCINT4_PORT PORTA
925 #define AD4_PORT PORTA
928 #define PCINT5_PORT PORTA
930 #define AD5_PORT PORTA
933 #define PCINT6_PORT PORTA
935 #define AD6_PORT PORTA
938 #define PCINT7_PORT PORTA
940 #define AD7_PORT PORTA
943 #define OC0_PORT PORTB
945 #define T0_PORT PORTB
948 #define OC2_PORT PORTB
950 #define T1_PORT PORTB
953 #define RXD1_PORT PORTB
955 #define AIN0_PORT PORTB
958 #define TXD1_PORT PORTB
960 #define AIN1_PORT PORTB
963 #define OC3B_PORT PORTB
965 #define SS_PORT PORTB
968 #define MOSI_PORT PORTB
971 #define MISO_PORT PORTB
975 #define PCINT8_PORT PORTC
977 #define A8_PORT PORTC
980 #define PCINT9_PORT PORTC
982 #define A9_PORT PORTC
985 #define PCINT10_PORT PORTC
986 #define PCINT10_BIT 2
987 #define A10_PORT PORTC
990 #define PCINT11_PORT PORTC
991 #define PCINT11_BIT 3
992 #define A11_PORT PORTC
995 #define PCINT12_PORT PORTC
996 #define PCINT12_BIT 4
997 #define A12_PORT PORTC
999 #define TCK_PORT PORTC
1002 #define PCINT13_PORT PORTC
1003 #define PCINT13_BIT 5
1004 #define A13_PORT PORTC
1006 #define TMS_PORT PORTC
1009 #define PCINT14_PORT PORTC
1010 #define PCINT14_BIT 6
1011 #define A14_PORT PORTC
1013 #define TDO_PORT PORTC
1016 #define PCINT15_PORT PORTC
1017 #define PCINT15_BIT 7
1018 #define A15_PORT PORTC
1020 #define TDI_PORT PORTC
1023 #define TXD0_PORT PORTD
1026 #define INT0_PORT PORTD
1028 #define XCK1_PORT PORTD
1031 #define INT1_PORT PORTD
1033 #define XCK1_PORT PORTD
1036 #define TOSC1_PORT PORTD
1038 #define XCK0_PORT PORTD
1040 #define OC3A_PORT PORTD
1043 #define OC1A_PORT PORTD
1045 #define TOSC2_PORT PORTD
1048 #define WR_PORT PORTD
1051 #define RD_PORT PORTD
1054 #define ICP1_PORT PORTE
1056 #define INT2_PORT PORTE
1059 #define ALE_PORT PORTE
1062 #define OC1B_PORT PORTE