2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_64 3
32 #define TIMER0_PRESCALER_DIV_256 4
33 #define TIMER0_PRESCALER_DIV_1024 5
34 #define TIMER0_PRESCALER_DIV_FALL 6
35 #define TIMER0_PRESCALER_DIV_RISE 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 64
41 #define TIMER0_PRESCALER_REG_4 256
42 #define TIMER0_PRESCALER_REG_5 1024
43 #define TIMER0_PRESCALER_REG_6 -1
44 #define TIMER0_PRESCALER_REG_7 -2
47 /* available timers */
49 /* overflow interrupt number */
50 #define SIG_OVERFLOW_TOTAL_NUM 0
52 /* output compare interrupt number */
53 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
56 #define PWM_TOTAL_NUM 0
58 /* input capture interrupt number */
59 #define SIG_INPUT_CAPTURE_TOTAL_NUM 0
63 #define CLKPS0_REG CLKPR
64 #define CLKPS1_REG CLKPR
65 #define CLKPS2_REG CLKPR
66 #define CLKPS3_REG CLKPR
67 #define CLKPCE_REG CLKPR
70 #define WDP0_REG WDTCR
71 #define WDP1_REG WDTCR
72 #define WDP2_REG WDTCR
74 #define WDCE_REG WDTCR
75 #define WDP3_REG WDTCR
76 #define WDTIE_REG WDTCR
77 #define WDTIF_REG WDTCR
80 #define PCIE_REG GIMSK
81 #define INT0_REG GIMSK
84 #define MUX0_REG ADMUX
85 #define MUX1_REG ADMUX
86 #define ADLAR_REG ADMUX
87 #define REFS0_REG ADMUX
100 #define DDB0_REG DDRB
101 #define DDB1_REG DDRB
102 #define DDB2_REG DDRB
103 #define DDB3_REG DDRB
104 #define DDB4_REG DDRB
105 #define DDB5_REG DDRB
108 #define EEDR0_REG EEDR
109 #define EEDR1_REG EEDR
110 #define EEDR2_REG EEDR
111 #define EEDR3_REG EEDR
112 #define EEDR4_REG EEDR
113 #define EEDR5_REG EEDR
114 #define EEDR6_REG EEDR
115 #define EEDR7_REG EEDR
118 #define ACIS0_REG ACSR
119 #define ACIS1_REG ACSR
120 #define ACIE_REG ACSR
123 #define ACBG_REG ACSR
127 #define PSR10_REG GTCCR
128 #define TSM_REG GTCCR
131 #define PCIF_REG GIFR
132 #define INTF0_REG GIFR
135 #define CAL0_REG OSCCAL
136 #define CAL1_REG OSCCAL
137 #define CAL2_REG OSCCAL
138 #define CAL3_REG OSCCAL
139 #define CAL4_REG OSCCAL
140 #define CAL5_REG OSCCAL
141 #define CAL6_REG OSCCAL
144 #define ADPS0_REG ADCSRA
145 #define ADPS1_REG ADCSRA
146 #define ADPS2_REG ADCSRA
147 #define ADIE_REG ADCSRA
148 #define ADIF_REG ADCSRA
149 #define ADATE_REG ADCSRA
150 #define ADSC_REG ADCSRA
151 #define ADEN_REG ADCSRA
154 #define ADTS0_REG ADCSRB
155 #define ADTS1_REG ADCSRB
156 #define ADTS2_REG ADCSRB
157 #define ACME_REG ADCSRB
160 #define OCR0A_0_REG OCR0A
161 #define OCR0A_1_REG OCR0A
162 #define OCR0A_2_REG OCR0A
163 #define OCR0A_3_REG OCR0A
164 #define OCR0A_4_REG OCR0A
165 #define OCR0A_5_REG OCR0A
166 #define OCR0A_6_REG OCR0A
167 #define OCR0A_7_REG OCR0A
170 #define OCR0B_0_REG OCR0B
171 #define OCR0B_1_REG OCR0B
172 #define OCR0B_2_REG OCR0B
173 #define OCR0B_3_REG OCR0B
174 #define OCR0B_4_REG OCR0B
175 #define OCR0B_5_REG OCR0B
176 #define OCR0B_6_REG OCR0B
177 #define OCR0B_7_REG OCR0B
190 #define PRADC_REG PRR
191 #define PRTIM0_REG PRR
194 #define PORF_REG MCUSR
195 #define EXTRF_REG MCUSR
196 #define BORF_REG MCUSR
197 #define WDRF_REG MCUSR
200 #define EERE_REG EECR
201 #define EEWE_REG EECR
202 #define EEMWE_REG EECR
203 #define EERIE_REG EECR
204 #define EEPM0_REG EECR
205 #define EEPM1_REG EECR
208 #define PCINT0_REG PCMSK
209 #define PCINT1_REG PCMSK
210 #define PCINT2_REG PCMSK
211 #define PCINT3_REG PCMSK
212 #define PCINT4_REG PCMSK
213 #define PCINT5_REG PCMSK
216 #define SPMEN_REG SPMCSR
217 #define PGERS_REG SPMCSR
218 #define PGWRT_REG SPMCSR
219 #define RFLB_REG SPMCSR
220 #define CTPB_REG SPMCSR
223 #define ADCL0_REG ADCL
224 #define ADCL1_REG ADCL
225 #define ADCL2_REG ADCL
226 #define ADCL3_REG ADCL
227 #define ADCL4_REG ADCL
228 #define ADCL5_REG ADCL
229 #define ADCL6_REG ADCL
230 #define ADCL7_REG ADCL
233 #define EEAR0_REG EEAR
234 #define EEAR1_REG EEAR
235 #define EEAR2_REG EEAR
236 #define EEAR3_REG EEAR
237 #define EEAR4_REG EEAR
238 #define EEAR5_REG EEAR
241 #define PORTB0_REG PORTB
242 #define PORTB1_REG PORTB
243 #define PORTB2_REG PORTB
244 #define PORTB3_REG PORTB
245 #define PORTB4_REG PORTB
246 #define PORTB5_REG PORTB
249 #define BPDSE_REG BODCR
250 #define BPDS_REG BODCR
253 #define ADCH0_REG ADCH
254 #define ADCH1_REG ADCH
255 #define ADCH2_REG ADCH
256 #define ADCH3_REG ADCH
257 #define ADCH4_REG ADCH
258 #define ADCH5_REG ADCH
259 #define ADCH6_REG ADCH
260 #define ADCH7_REG ADCH
263 #define TCNT0_0_REG TCNT0
264 #define TCNT0_1_REG TCNT0
265 #define TCNT0_2_REG TCNT0
266 #define TCNT0_3_REG TCNT0
267 #define TCNT0_4_REG TCNT0
268 #define TCNT0_5_REG TCNT0
269 #define TCNT0_6_REG TCNT0
270 #define TCNT0_7_REG TCNT0
273 #define TOIE0_REG TIMSK0
274 #define OCIE0A_REG TIMSK0
275 #define OCIE0B_REG TIMSK0
278 #define CS00_REG TCCR0B
279 #define CS01_REG TCCR0B
280 #define CS02_REG TCCR0B
281 #define WGM02_REG TCCR0B
282 #define FOC0B_REG TCCR0B
283 #define FOC0A_REG TCCR0B
286 #define WGM00_REG TCCR0A
287 #define WGM01_REG TCCR0A
288 #define COM0B0_REG TCCR0A
289 #define COM0B1_REG TCCR0A
290 #define COM0A0_REG TCCR0A
291 #define COM0A1_REG TCCR0A
294 #define DWDR0_REG DWDR
295 #define DWDR1_REG DWDR
296 #define DWDR2_REG DWDR
297 #define DWDR3_REG DWDR
298 #define DWDR4_REG DWDR
299 #define DWDR5_REG DWDR
300 #define DWDR6_REG DWDR
301 #define DWDR7_REG DWDR
304 #define ADC1D_REG DIDR0
305 #define ADC3D_REG DIDR0
306 #define ADC2D_REG DIDR0
307 #define ADC0D_REG DIDR0
308 #define AIN0D_REG DIDR0
309 #define AIN1D_REG DIDR0
312 #define ISC00_REG MCUCR
313 #define ISC01_REG MCUCR
314 #define SM0_REG MCUCR
315 #define SM1_REG MCUCR
317 #define PUD_REG MCUCR
320 #define PINB0_REG PINB
321 #define PINB1_REG PINB
322 #define PINB2_REG PINB
323 #define PINB3_REG PINB
324 #define PINB4_REG PINB
325 #define PINB5_REG PINB
328 #define TOV0_REG TIFR0
329 #define OCF0A_REG TIFR0
330 #define OCF0B_REG TIFR0
333 #define MOSI_PORT PORTB
335 #define AIN0_PORT PORTB
337 #define OC0A_PORT PORTB
339 #define TXD_PORT PORTB
341 #define PCINT0_PORT PORTB
344 #define MISO_PORT PORTB
346 #define INT0_PORT PORTB
348 #define AIN1_PORT PORTB
350 #define OC0B_PORT PORTB
352 #define INT0_PORT PORTB
354 #define RXD_PORT PORTB
356 #define PCINT1_PORT PORTB
359 #define SCK_PORT PORTB
361 #define ADC1_PORT PORTB
363 #define T0_PORT PORTB
365 #define PCINT2_PORT PORTB