2 * Copyright Droids Corporation, Microb Technology, Eirbot (2009)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* WARNING : this file is automatically generated by scripts.
23 * You should not edit it. If you find something wrong in it,
24 * write to zer0@droids-corp.org */
27 /* prescalers timer 0 */
28 #define TIMER0_PRESCALER_DIV_0 0
29 #define TIMER0_PRESCALER_DIV_1 1
30 #define TIMER0_PRESCALER_DIV_8 2
31 #define TIMER0_PRESCALER_DIV_32 3
32 #define TIMER0_PRESCALER_DIV_64 4
33 #define TIMER0_PRESCALER_DIV_128 5
34 #define TIMER0_PRESCALER_DIV_256 6
35 #define TIMER0_PRESCALER_DIV_1024 7
37 #define TIMER0_PRESCALER_REG_0 0
38 #define TIMER0_PRESCALER_REG_1 1
39 #define TIMER0_PRESCALER_REG_2 8
40 #define TIMER0_PRESCALER_REG_3 32
41 #define TIMER0_PRESCALER_REG_4 64
42 #define TIMER0_PRESCALER_REG_5 128
43 #define TIMER0_PRESCALER_REG_6 256
44 #define TIMER0_PRESCALER_REG_7 1024
46 /* prescalers timer 1 */
47 #define TIMER1_PRESCALER_DIV_0 0
48 #define TIMER1_PRESCALER_DIV_1 1
49 #define TIMER1_PRESCALER_DIV_8 2
50 #define TIMER1_PRESCALER_DIV_64 3
51 #define TIMER1_PRESCALER_DIV_256 4
52 #define TIMER1_PRESCALER_DIV_1024 5
53 #define TIMER1_PRESCALER_DIV_FALL 6
54 #define TIMER1_PRESCALER_DIV_RISE 7
56 #define TIMER1_PRESCALER_REG_0 0
57 #define TIMER1_PRESCALER_REG_1 1
58 #define TIMER1_PRESCALER_REG_2 8
59 #define TIMER1_PRESCALER_REG_3 64
60 #define TIMER1_PRESCALER_REG_4 256
61 #define TIMER1_PRESCALER_REG_5 1024
62 #define TIMER1_PRESCALER_REG_6 -1
63 #define TIMER1_PRESCALER_REG_7 -2
66 /* available timers */
67 #define TIMER0_AVAILABLE
68 #define TIMER0A_AVAILABLE
69 #define TIMER1_AVAILABLE
70 #define TIMER1A_AVAILABLE
71 #define TIMER1B_AVAILABLE
73 /* overflow interrupt number */
74 #define SIG_OVERFLOW0_NUM 0
75 #define SIG_OVERFLOW1_NUM 1
76 #define SIG_OVERFLOW_TOTAL_NUM 2
78 /* output compare interrupt number */
79 #define SIG_OUTPUT_COMPARE0A_NUM 0
80 #define SIG_OUTPUT_COMPARE1A_NUM 1
81 #define SIG_OUTPUT_COMPARE1B_NUM 2
82 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 3
88 #define PWM_TOTAL_NUM 3
90 /* input capture interrupt number */
91 #define SIG_INPUT_CAPTURE1_NUM 0
92 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
96 #define PORTB0_REG PORTB
97 #define PORTB1_REG PORTB
98 #define PORTB2_REG PORTB
99 #define PORTB3_REG PORTB
100 #define PORTB4_REG PORTB
101 #define PORTB5_REG PORTB
102 #define PORTB6_REG PORTB
103 #define PORTB7_REG PORTB
106 #define LID0_REG LINIDR
107 #define LID1_REG LINIDR
108 #define LID2_REG LINIDR
109 #define LID3_REG LINIDR
110 #define LID4_REG LINIDR
111 #define LID5_REG LINIDR
112 #define LP0_REG LINIDR
113 #define LP1_REG LINIDR
116 #define CLKPS0_REG CLKPR
117 #define CLKPS1_REG CLKPR
118 #define CLKPS2_REG CLKPR
119 #define CLKPS3_REG CLKPR
120 #define CLKPCE_REG CLKPR
128 #define WDP0_REG WDTCR
129 #define WDP1_REG WDTCR
130 #define WDP2_REG WDTCR
131 #define WDE_REG WDTCR
132 #define WDCE_REG WDTCR
133 #define WDP3_REG WDTCR
134 #define WDIE_REG WDTCR
135 #define WDIF_REG WDTCR
138 #define PCIF0_REG PCIFR
139 #define PCIF1_REG PCIFR
142 #define LBT0_REG LINBTR
143 #define LBT1_REG LINBTR
144 #define LBT2_REG LINBTR
145 #define LBT3_REG LINBTR
146 #define LBT4_REG LINBTR
147 #define LBT5_REG LINBTR
148 #define LDISR_REG LINBTR
151 #define MUX0_REG ADMUX
152 #define MUX1_REG ADMUX
153 #define MUX2_REG ADMUX
154 #define MUX3_REG ADMUX
155 #define MUX4_REG ADMUX
156 #define ADLAR_REG ADMUX
157 #define REFS0_REG ADMUX
158 #define REFS1_REG ADMUX
161 #define ISC00_REG EICRA
162 #define ISC01_REG EICRA
163 #define ISC10_REG EICRA
164 #define ISC11_REG EICRA
167 #define PUDA_REG PORTCR
168 #define PUDB_REG PORTCR
169 #define BBMA_REG PORTCR
170 #define BBMB_REG PORTCR
183 #define DDB0_REG DDRB
184 #define DDB1_REG DDRB
185 #define DDB2_REG DDRB
186 #define DDB3_REG DDRB
187 #define DDB4_REG DDRB
188 #define DDB5_REG DDRB
189 #define DDB6_REG DDRB
190 #define DDB7_REG DDRB
193 #define XREFEN_REG AMISCR
194 #define AREFEN_REG AMISCR
195 #define ISRCEN_REG AMISCR
198 #define CSEL0_REG CLKSELR
199 #define CSEL1_REG CLKSELR
200 #define CSEL2_REG CLKSELR
201 #define CSEL3_REG CLKSELR
202 #define CSUT0_REG CLKSELR
203 #define CSUT1_REG CLKSELR
204 #define COUT_REG CLKSELR
207 #define EEDR0_REG EEDR
208 #define EEDR1_REG EEDR
209 #define EEDR2_REG EEDR
210 #define EEDR3_REG EEDR
211 #define EEDR4_REG EEDR
212 #define EEDR5_REG EEDR
213 #define EEDR6_REG EEDR
214 #define EEDR7_REG EEDR
217 #define OC1AU_REG TCCR1D
218 #define OC1AV_REG TCCR1D
219 #define OC1AW_REG TCCR1D
220 #define OC1AX_REG TCCR1D
221 #define OC1BU_REG TCCR1D
222 #define OC1BV_REG TCCR1D
223 #define OC1BW_REG TCCR1D
224 #define OC1BX_REG TCCR1D
227 #define DDA0_REG DDRA
228 #define DDA1_REG DDRA
229 #define DDA2_REG DDRA
230 #define DDA3_REG DDRA
231 #define DDA4_REG DDRA
232 #define DDA5_REG DDRA
233 #define DDA6_REG DDRA
234 #define DDA7_REG DDRA
237 #define WGM10_REG TCCR1A
238 #define WGM11_REG TCCR1A
239 #define COM1B0_REG TCCR1A
240 #define COM1B1_REG TCCR1A
241 #define COM1A0_REG TCCR1A
242 #define COM1A1_REG TCCR1A
245 #define LINDX0_REG LINSEL
246 #define LINDX1_REG LINSEL
247 #define LINDX2_REG LINSEL
248 #define LAINC_REG LINSEL
251 #define FOC1B_REG TCCR1C
252 #define FOC1A_REG TCCR1C
255 #define LCMD0_REG LINCR
256 #define LCMD1_REG LINCR
257 #define LCMD2_REG LINCR
258 #define LENA_REG LINCR
259 #define LCONF0_REG LINCR
260 #define LCONF1_REG LINCR
261 #define LIN13_REG LINCR
262 #define LSWRES_REG LINCR
265 #define TOV1_REG TIFR1
266 #define OCF1A_REG TIFR1
267 #define OCF1B_REG TIFR1
268 #define ICF1_REG TIFR1
271 #define ICR1H0_REG ICR1H
272 #define ICR1H1_REG ICR1H
273 #define ICR1H2_REG ICR1H
274 #define ICR1H3_REG ICR1H
275 #define ICR1H4_REG ICR1H
276 #define ICR1H5_REG ICR1H
277 #define ICR1H6_REG ICR1H
278 #define ICR1H7_REG ICR1H
281 #define PSR1_REG GTCCR
282 #define PSR0_REG GTCCR
283 #define TSM_REG GTCCR
286 #define ADPS0_REG ADCSRA
287 #define ADPS1_REG ADCSRA
288 #define ADPS2_REG ADCSRA
289 #define ADIE_REG ADCSRA
290 #define ADIF_REG ADCSRA
291 #define ADATE_REG ADCSRA
292 #define ADSC_REG ADCSRA
293 #define ADEN_REG ADCSRA
296 #define ADTS0_REG ADCSRB
297 #define ADTS1_REG ADCSRB
298 #define ADTS2_REG ADCSRB
299 #define BIN_REG ADCSRB
300 #define ACIR0_REG ADCSRB
301 #define ACIR1_REG ADCSRB
302 #define ACME_REG ADCSRB
305 #define SPDR0_REG SPDR
306 #define SPDR1_REG SPDR
307 #define SPDR2_REG SPDR
308 #define SPDR3_REG SPDR
309 #define SPDR4_REG SPDR
310 #define SPDR5_REG SPDR
311 #define SPDR6_REG SPDR
312 #define SPDR7_REG SPDR
315 #define OCR00_REG OCR0A
316 #define OCR01_REG OCR0A
317 #define OCR02_REG OCR0A
318 #define OCR03_REG OCR0A
319 #define OCR04_REG OCR0A
320 #define OCR05_REG OCR0A
321 #define OCR06_REG OCR0A
322 #define OCR07_REG OCR0A
325 #define SPI2X_REG SPSR
326 #define WCOL_REG SPSR
327 #define SPIF_REG SPSR
330 #define ACIS0_REG ACSR
331 #define ACIS1_REG ACSR
332 #define ACIC_REG ACSR
333 #define ACIE_REG ACSR
336 #define ACIRS_REG ACSR
340 #define USIPOS_REG USIPP
343 /* #define OCR1AL0_REG OCR1BL */ /* dup in OCR1AL */
344 /* #define OCR1AL1_REG OCR1BL */ /* dup in OCR1AL */
345 /* #define OCR1AL2_REG OCR1BL */ /* dup in OCR1AL */
346 /* #define OCR1AL3_REG OCR1BL */ /* dup in OCR1AL */
347 /* #define OCR1AL4_REG OCR1BL */ /* dup in OCR1AL */
348 /* #define OCR1AL5_REG OCR1BL */ /* dup in OCR1AL */
349 /* #define OCR1AL6_REG OCR1BL */ /* dup in OCR1AL */
350 /* #define OCR1AL7_REG OCR1BL */ /* dup in OCR1AL */
353 #define ICR1L0_REG ICR1L
354 #define ICR1L1_REG ICR1L
355 #define ICR1L2_REG ICR1L
356 #define ICR1L3_REG ICR1L
357 #define ICR1L4_REG ICR1L
358 #define ICR1L5_REG ICR1L
359 #define ICR1L6_REG ICR1L
360 #define ICR1L7_REG ICR1L
363 /* #define OCR1AH0_REG OCR1BH */ /* dup in OCR1AH */
364 /* #define OCR1AH1_REG OCR1BH */ /* dup in OCR1AH */
365 /* #define OCR1AH2_REG OCR1BH */ /* dup in OCR1AH */
366 /* #define OCR1AH3_REG OCR1BH */ /* dup in OCR1AH */
367 /* #define OCR1AH4_REG OCR1BH */ /* dup in OCR1AH */
368 /* #define OCR1AH5_REG OCR1BH */ /* dup in OCR1AH */
369 /* #define OCR1AH6_REG OCR1BH */ /* dup in OCR1AH */
370 /* #define OCR1AH7_REG OCR1BH */ /* dup in OCR1AH */
373 #define PRADC_REG PRR
374 #define PRUSI_REG PRR
375 #define PRTIM0_REG PRR
376 #define PRTIM1_REG PRR
377 #define PRSPI_REG PRR
378 #define PRLIN_REG PRR
381 #define GPIOR10_REG GPIOR1
382 #define GPIOR11_REG GPIOR1
383 #define GPIOR12_REG GPIOR1
384 #define GPIOR13_REG GPIOR1
385 #define GPIOR14_REG GPIOR1
386 #define GPIOR15_REG GPIOR1
387 #define GPIOR16_REG GPIOR1
388 #define GPIOR17_REG GPIOR1
401 #define USITC_REG USICR
402 #define USICLK_REG USICR
403 #define USICS0_REG USICR
404 #define USICS1_REG USICR
405 #define USIWM0_REG USICR
406 #define USIWM1_REG USICR
407 #define USIOIE_REG USICR
408 #define USISIE_REG USICR
411 #define SPMEN_REG SPMCSR
412 #define PGERS_REG SPMCSR
413 #define PGWRT_REG SPMCSR
414 #define RFLB_REG SPMCSR
415 #define CTPB_REG SPMCSR
416 #define SIGRD_REG SPMCSR
417 #define RWWSB_REG SPMCSR
420 #define ADCL0_REG ADCL
421 #define ADCL1_REG ADCL
422 #define ADCL2_REG ADCL
423 #define ADCL3_REG ADCL
424 #define ADCL4_REG ADCL
425 #define ADCL5_REG ADCL
426 #define ADCL6_REG ADCL
427 #define ADCL7_REG ADCL
430 #define PORF_REG MCUSR
431 #define EXTRF_REG MCUSR
432 #define BORF_REG MCUSR
433 #define WDRF_REG MCUSR
436 #define LDIV0_REG LINBRRL
437 #define LDIV1_REG LINBRRL
438 #define LDIV2_REG LINBRRL
439 #define LDIV3_REG LINBRRL
440 #define LDIV4_REG LINBRRL
441 #define LDIV5_REG LINBRRL
442 #define LDIV6_REG LINBRRL
443 #define LDIV7_REG LINBRRL
446 #define EERE_REG EECR
447 #define EEPE_REG EECR
448 #define EEMPE_REG EECR
449 #define EERIE_REG EECR
450 #define EEPM0_REG EECR
451 #define EEPM1_REG EECR
459 #define LDIV8_REG LINBRRH
460 #define LDIV9_REG LINBRRH
461 #define LDIV10_REG LINBRRH
462 #define LDIV11_REG LINBRRH
465 #define LDATA0_REG LINDAT
466 #define LDATA1_REG LINDAT
467 #define LDATA2_REG LINDAT
468 #define LDATA3_REG LINDAT
469 #define LDATA4_REG LINDAT
470 #define LDATA5_REG LINDAT
471 #define LDATA6_REG LINDAT
472 #define LDATA7_REG LINDAT
475 #define CAL0_REG OSCCAL
476 #define CAL1_REG OSCCAL
477 #define CAL2_REG OSCCAL
478 #define CAL3_REG OSCCAL
479 #define CAL4_REG OSCCAL
480 #define CAL5_REG OSCCAL
481 #define CAL6_REG OSCCAL
482 #define CAL7_REG OSCCAL
485 #define TCNT1L0_REG TCNT1L
486 #define TCNT1L1_REG TCNT1L
487 #define TCNT1L2_REG TCNT1L
488 #define TCNT1L3_REG TCNT1L
489 #define TCNT1L4_REG TCNT1L
490 #define TCNT1L5_REG TCNT1L
491 #define TCNT1L6_REG TCNT1L
492 #define TCNT1L7_REG TCNT1L
495 #define TCNT1H0_REG TCNT1H
496 #define TCNT1H1_REG TCNT1H
497 #define TCNT1H2_REG TCNT1H
498 #define TCNT1H3_REG TCNT1H
499 #define TCNT1H4_REG TCNT1H
500 #define TCNT1H5_REG TCNT1H
501 #define TCNT1H6_REG TCNT1H
502 #define TCNT1H7_REG TCNT1H
505 #define LENRXOK_REG LINENIR
506 #define LENTXOK_REG LINENIR
507 #define LENIDOK_REG LINENIR
508 #define LENERR_REG LINENIR
511 #define USICNT0_REG USISR
512 #define USICNT1_REG USISR
513 #define USICNT2_REG USISR
514 #define USICNT3_REG USISR
515 #define USIDC_REG USISR
516 #define USIPF_REG USISR
517 #define USIOIF_REG USISR
518 #define USISIF_REG USISR
521 #define LBERR_REG LINERR
522 #define LCERR_REG LINERR
523 #define LPERR_REG LINERR
524 #define LSERR_REG LINERR
525 #define LFERR_REG LINERR
526 #define LOVERR_REG LINERR
527 #define LTOERR_REG LINERR
528 #define LABORT_REG LINERR
531 #define ADCH0_REG ADCH
532 #define ADCH1_REG ADCH
533 #define ADCH2_REG ADCH
534 #define ADCH3_REG ADCH
535 #define ADCH4_REG ADCH
536 #define ADCH5_REG ADCH
537 #define ADCH6_REG ADCH
538 #define ADCH7_REG ADCH
541 #define PORTA0_REG PORTA
542 #define PORTA1_REG PORTA
543 #define PORTA2_REG PORTA
544 #define PORTA3_REG PORTA
545 #define PORTA4_REG PORTA
546 #define PORTA5_REG PORTA
547 #define PORTA6_REG PORTA
548 #define PORTA7_REG PORTA
551 #define TOV0_REG TIFR0
552 #define OCF0A_REG TIFR0
555 #define TCNT00_REG TCNT0
556 #define TCNT01_REG TCNT0
557 #define TCNT02_REG TCNT0
558 #define TCNT03_REG TCNT0
559 #define TCNT04_REG TCNT0
560 #define TCNT05_REG TCNT0
561 #define TCNT06_REG TCNT0
562 #define TCNT07_REG TCNT0
565 #define PCIE0_REG PCICR
566 #define PCIE1_REG PCICR
569 #define GPIOR00_REG GPIOR0
570 #define GPIOR01_REG GPIOR0
571 #define GPIOR02_REG GPIOR0
572 #define GPIOR03_REG GPIOR0
573 #define GPIOR04_REG GPIOR0
574 #define GPIOR05_REG GPIOR0
575 #define GPIOR06_REG GPIOR0
576 #define GPIOR07_REG GPIOR0
579 #define EEAR0_REG EEARL
580 #define EEAR1_REG EEARL
581 #define EEAR2_REG EEARL
582 #define EEAR3_REG EEARL
583 #define EEAR4_REG EEARL
584 #define EEAR5_REG EEARL
585 #define EEAR6_REG EEARL
586 #define EEAR7_REG EEARL
589 #define TOIE0_REG TIMSK0
590 #define OCIE0A_REG TIMSK0
593 #define TOIE1_REG TIMSK1
594 #define OCIE1A_REG TIMSK1
595 #define OCIE1B_REG TIMSK1
596 #define ICIE1_REG TIMSK1
599 #define CS00_REG TCCR0B
600 #define CS01_REG TCCR0B
601 #define CS02_REG TCCR0B
602 #define FOC0A_REG TCCR0B
605 #define WGM00_REG TCCR0A
606 #define WGM01_REG TCCR0A
607 #define COM0A0_REG TCCR0A
608 #define COM0A1_REG TCCR0A
611 #define EEAR8_REG EEARH
614 #define GPIOR20_REG GPIOR2
615 #define GPIOR21_REG GPIOR2
616 #define GPIOR22_REG GPIOR2
617 #define GPIOR23_REG GPIOR2
618 #define GPIOR24_REG GPIOR2
619 #define GPIOR25_REG GPIOR2
620 #define GPIOR26_REG GPIOR2
621 #define GPIOR27_REG GPIOR2
624 #define PCINT0_REG PCMSK0
625 #define PCINT1_REG PCMSK0
626 #define PCINT2_REG PCMSK0
627 #define PCINT3_REG PCMSK0
628 #define PCINT4_REG PCMSK0
629 #define PCINT5_REG PCMSK0
630 #define PCINT6_REG PCMSK0
631 #define PCINT7_REG PCMSK0
634 #define PCINT8_REG PCMSK1
635 #define PCINT9_REG PCMSK1
636 #define PCINT10_REG PCMSK1
637 #define PCINT11_REG PCMSK1
638 #define PCINT12_REG PCMSK1
639 #define PCINT13_REG PCMSK1
640 #define PCINT14_REG PCMSK1
641 #define PCINT15_REG PCMSK1
644 #define LRXDL0_REG LINDLR
645 #define LRXDL1_REG LINDLR
646 #define LRXDL2_REG LINDLR
647 #define LRXDL3_REG LINDLR
648 #define LTXDL0_REG LINDLR
649 #define LTXDL1_REG LINDLR
650 #define LTXDL2_REG LINDLR
651 #define LTXDL3_REG LINDLR
654 #define DWDR0_REG DWDR
655 #define DWDR1_REG DWDR
656 #define DWDR2_REG DWDR
657 #define DWDR3_REG DWDR
658 #define DWDR4_REG DWDR
659 #define DWDR5_REG DWDR
660 #define DWDR6_REG DWDR
661 #define DWDR7_REG DWDR
664 #define INTF0_REG EIFR
665 #define INTF1_REG EIFR
668 #define LRXOK_REG LINSIR
669 #define LTXOK_REG LINSIR
670 #define LIDOK_REG LINSIR
671 #define LERR_REG LINSIR
672 #define LBUSY_REG LINSIR
673 #define LIDST0_REG LINSIR
674 #define LIDST1_REG LINSIR
675 #define LIDST2_REG LINSIR
678 #define ADC0D_REG DIDR0
679 #define ADC1D_REG DIDR0
680 #define ADC2D_REG DIDR0
681 #define ADC3D_REG DIDR0
682 #define ADC4D_REG DIDR0
683 #define ADC5D_REG DIDR0
684 #define ADC6D_REG DIDR0
685 #define ADC7D_REG DIDR0
688 #define ADC8D_REG DIDR1
689 #define ADC9D_REG DIDR1
690 #define ADC10D_REG DIDR1
693 #define CLKC0_REG CLKCSR
694 #define CLKC1_REG CLKCSR
695 #define CLKC2_REG CLKCSR
696 #define CLKC3_REG CLKCSR
697 #define CLKRDY_REG CLKCSR
698 #define CLKCCE_REG CLKCSR
701 #define PUD_REG MCUCR
702 #define BODS_REG MCUCR
703 #define BODSE_REG MCUCR
706 /* #define OCR1AH0_REG OCR1AH */ /* dup in OCR1BH */
707 /* #define OCR1AH1_REG OCR1AH */ /* dup in OCR1BH */
708 /* #define OCR1AH2_REG OCR1AH */ /* dup in OCR1BH */
709 /* #define OCR1AH3_REG OCR1AH */ /* dup in OCR1BH */
710 /* #define OCR1AH4_REG OCR1AH */ /* dup in OCR1BH */
711 /* #define OCR1AH5_REG OCR1AH */ /* dup in OCR1BH */
712 /* #define OCR1AH6_REG OCR1AH */ /* dup in OCR1BH */
713 /* #define OCR1AH7_REG OCR1AH */ /* dup in OCR1BH */
716 /* #define OCR1AL0_REG OCR1AL */ /* dup in OCR1BL */
717 /* #define OCR1AL1_REG OCR1AL */ /* dup in OCR1BL */
718 /* #define OCR1AL2_REG OCR1AL */ /* dup in OCR1BL */
719 /* #define OCR1AL3_REG OCR1AL */ /* dup in OCR1BL */
720 /* #define OCR1AL4_REG OCR1AL */ /* dup in OCR1BL */
721 /* #define OCR1AL5_REG OCR1AL */ /* dup in OCR1BL */
722 /* #define OCR1AL6_REG OCR1AL */ /* dup in OCR1BL */
723 /* #define OCR1AL7_REG OCR1AL */ /* dup in OCR1BL */
726 #define SPR0_REG SPCR
727 #define SPR1_REG SPCR
728 #define CPHA_REG SPCR
729 #define CPOL_REG SPCR
730 #define MSTR_REG SPCR
731 #define DORD_REG SPCR
733 #define SPIE_REG SPCR
736 #define PINB0_REG PINB
737 #define PINB1_REG PINB
738 #define PINB2_REG PINB
739 #define PINB3_REG PINB
740 #define PINB4_REG PINB
741 #define PINB5_REG PINB
742 #define PINB6_REG PINB
743 #define PINB7_REG PINB
746 #define USIBR0_REG USIBR
747 #define USIBR1_REG USIBR
748 #define USIBR2_REG USIBR
749 #define USIBR3_REG USIBR
750 #define USIBR4_REG USIBR
751 #define USIBR5_REG USIBR
752 #define USIBR6_REG USIBR
753 #define USIBR7_REG USIBR
756 #define INT0_REG EIMSK
757 #define INT1_REG EIMSK
760 #define CS10_REG TCCR1B
761 #define CS11_REG TCCR1B
762 #define CS12_REG TCCR1B
763 #define WGM12_REG TCCR1B
764 #define WGM13_REG TCCR1B
765 #define ICES1_REG TCCR1B
766 #define ICNC1_REG TCCR1B
769 #define PINA0_REG PINA
770 #define PINA1_REG PINA
771 #define PINA2_REG PINA
772 #define PINA3_REG PINA
773 #define PINA4_REG PINA
774 #define PINA5_REG PINA
775 #define PINA6_REG PINA
776 #define PINA7_REG PINA
779 #define USIDR0_REG USIDR
780 #define USIDR1_REG USIDR
781 #define USIDR2_REG USIDR
782 #define USIDR3_REG USIDR
783 #define USIDR4_REG USIDR
784 #define USIDR5_REG USIDR
785 #define USIDR6_REG USIDR
786 #define USIDR7_REG USIDR
789 #define TCR0BUB_REG ASSR
790 #define TCR0AUB_REG ASSR
791 #define OCR0AUB_REG ASSR
792 #define TCN0UB_REG ASSR
794 #define EXCLK_REG ASSR